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![Simon Glass](/assets/img/avatar_default.png)
At present stdio device functions do not get any clue as to which stdio device is being acted on. Some implementations go to great lengths to work around this, such as defining a whole separate set of functions for each possible device. For driver model we need to associate a stdio_dev with a device. It doesn't seem possible to continue with this work-around approach. Instead, add a stdio_dev pointer to each of the stdio member functions. Note: The serial drivers have the same problem, but it is not strictly necessary to fix that to get driver model running. Also, if we convert serial over to driver model the problem will go away. Code size increases by 244 bytes for Thumb2 and 428 for PowerPC. 22: stdio: Pass device pointer to stdio methods arm: (for 2/2 boards) all +244.0 bss -4.0 text +248.0 powerpc: (for 1/1 boards) all +428.0 text +428.0 Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Marek Vasut <marex@denx.de>
601 lines
17 KiB
C
601 lines
17 KiB
C
/*
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* (C) Copyright 2003
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* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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* Atapted for PATI
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* Denis Peter, d.peter@mpl.ch
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/***********************************************************************************
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* Bits for the SDRAM controller
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* -----------------------------
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*
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* CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
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* the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
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* controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
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* RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
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* tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
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* WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
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* If set to 1 tWR must be equal or less 50ns.
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* RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
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* 25ns. If set to 1 tRP must be equal or less 50ns.
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* RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
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* or less 75ns. If set to 1 tRC must be equal or less 100ns.
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* LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
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* is the Load Mode Register Command.
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* IIP: Init in progress. Set to 1 for starting the init sequence
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* (Precharge All). As long this bit is set, the Precharge All is still in progress.
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* After command has completed, wait at least for 8 refresh (200usec) before proceed.
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**********************************************************************************/
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#include <common.h>
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#include <mpc5xx.h>
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#include <stdio_dev.h>
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#include <pci_ids.h>
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#define PLX9056_LOC
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#include "plx9056.h"
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#include "pati.h"
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#if defined(__APPLE__)
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/* Leading underscore on symbols */
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# define SYM_CHAR "_"
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#else /* No leading character on symbols */
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# define SYM_CHAR
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#endif
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#undef SDRAM_DEBUG
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/*
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* Macros to generate global absolutes.
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*/
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#define GEN_SYMNAME(str) SYM_CHAR #str
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#define GEN_VALUE(str) #str
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#define GEN_ABS(name, value) \
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asm (".globl " GEN_SYMNAME(name)); \
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asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
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/************************************************************************
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* Early debug routines
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*/
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void write_hex (unsigned char i)
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{
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char cc;
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cc = i >> 4;
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cc &= 0xf;
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if (cc > 9)
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serial_putc (cc + 55);
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else
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serial_putc (cc + 48);
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cc = i & 0xf;
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if (cc > 9)
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serial_putc (cc + 55);
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else
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serial_putc (cc + 48);
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}
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#if defined(SDRAM_DEBUG)
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void write_4hex (unsigned long val)
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{
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write_hex ((unsigned char) (val >> 24));
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write_hex ((unsigned char) (val >> 16));
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write_hex ((unsigned char) (val >> 8));
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write_hex ((unsigned char) val);
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}
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#endif
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unsigned long in32(unsigned long addr)
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{
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unsigned long *p=(unsigned long *)addr;
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return *p;
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}
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void out32(unsigned long addr,unsigned long data)
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{
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unsigned long *p=(unsigned long *)addr;
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*p=data;
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}
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typedef struct {
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unsigned short boardtype; /* Board revision and Population Options */
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unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */
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unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/
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unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */
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unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */
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unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */
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unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
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} sdram_t;
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const sdram_t sdram_table[] = {
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{ 0x0000, /* PATI Rev A, 16MByte -1 Board */
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1, /* Case Latenty = 3 */
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0, /* ras to cas delay 0 (20ns) */
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0, /* write recovery 0:<25ns 1:<50ns*/
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0, /* Precharge Command Time 0 (20ns) */
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0, /* Auto Refresh to Active Time 0 (68) */
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2 /* log binary => Size 2 = 16MByte, 1=8 */
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},
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{ 0xffff, /* terminator */
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0xff,
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0xff,
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0xff,
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0xff,
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0xff,
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0xff }
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};
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extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
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/*
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* Get RAM size.
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*/
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phys_size_t initdram(int board_type)
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{
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unsigned char board_rev;
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unsigned long reg;
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unsigned long lmr;
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int i,timeout;
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#if defined(SDRAM_DEBUG)
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reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
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puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
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puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
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puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg));
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puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
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reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
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puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg));
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putc('\n');
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#endif
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reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
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board_rev=(unsigned char)(SYSCNTR_BREV(reg));
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i=0;
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while(1) {
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if(sdram_table[i].boardtype==0xffff) {
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puts("ERROR, found no table for Board 0x");
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write_hex(board_rev);
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while(1);
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}
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if(sdram_table[i].boardtype==(unsigned char)board_rev)
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break;
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i++;
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}
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/* Set CAL, RCD, WREQ, PR and RC Bits */
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#if defined(SDRAM_DEBUG)
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puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
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#endif
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/* mask bits */
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reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
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SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) |
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SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
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/* set bits */
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reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
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SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
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SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
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SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
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SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
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out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
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/* step 2 set IIP */
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#if defined(SDRAM_DEBUG)
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puts("step 2 set IIP\n");
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#endif
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/* step 2 set IIP */
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reg |= SET_REG_BIT(1,SDRAM_IIP);
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timeout=0;
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while (timeout!=0xffff) {
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__asm__ volatile("eieio");
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reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
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if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
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break;
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timeout++;
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udelay(1);
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}
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/* wait for at least 8 refresh */
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udelay(1000);
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/* set LMR */
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reg |= SET_REG_BIT(1,SDRAM_LMR);
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out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
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__asm__ volatile("eieio");
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lmr=0x00000002; /* sequential burst 4 data */
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if(sdram_table[i].cal==1)
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lmr|=0x00000030; /* cal = 3 */
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else
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lmr|=0000000020; /* cal = 2 */
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/* rest standard operation programmed write burst length */
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/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
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lmr<<=2;
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in32(CONFIG_SYS_SDRAM_BASE + lmr);
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/* ok, we're done, return SDRAM size */
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return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */
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}
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void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
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{
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unsigned long reg;
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reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
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reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
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SET_REG_BIT(1,SYSCNTR_FL_VPP) |
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SET_REG_BIT(1,SYSCNTR_FL_WP));
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reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
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SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
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SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
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out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
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udelay(100);
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}
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void show_pld_regs(void)
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{
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unsigned long reg,reg1;
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reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
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printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
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printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
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reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
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printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
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printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg));
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printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n",
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GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
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GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
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GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
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GET_REG_BIT(reg,SDRAM_IIP));
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reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
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reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
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printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n",
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GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
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GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
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GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
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GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
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printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg),
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GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
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GET_SYSCNTR_CFG(reg1));
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printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
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GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
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GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
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}
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/****************************************************************
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* Setting IOs
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* -----------
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* GPIO6 is User LED1
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* GPIO7 is Interrupt PLX (Output)
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* GPIO5 is User LED0
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* GPIO2 is PLX USERi (Output)
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* GPIO1 is PLX Interrupt (Input)
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****************************************************************/
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void init_ios(void)
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{
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volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
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unsigned long reg;
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reg=sysconf->sc_sgpiocr; /* Data direction register */
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reg &= ~0x67000000;
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reg |= 0x27000000; /* set outpupts */
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sysconf->sc_sgpiocr=reg; /* Data direction register */
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reg=sysconf->sc_sgpiodt2; /* Data register */
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/* set output to 0 */
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reg &= ~0x27000000;
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/* set IRQ and USERi to 1 */
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reg |= 0x28000000;
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sysconf->sc_sgpiodt2=reg; /* Data register */
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}
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void user_led0(int led_on)
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{
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volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
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unsigned long reg;
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reg=sysconf->sc_sgpiodt2; /* Data register */
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if(led_on) /* set output to 1 */
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reg |= 0x04000000;
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else
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reg &= ~0x04000000;
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sysconf->sc_sgpiodt2=reg; /* Data register */
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}
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void user_led1(int led_on)
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{
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volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
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volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
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unsigned long reg;
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reg=sysconf->sc_sgpiodt2; /* Data register */
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if(led_on) /* set output to 1 */
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reg |= 0x02000000;
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else
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reg &= ~0x02000000;
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sysconf->sc_sgpiodt2=reg; /* Data register */
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}
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/****************************************************************
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* Last Stage Init
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****************************************************************/
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int last_stage_init (void)
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{
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init_ios();
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return 0;
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}
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/****************************************************************
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* Check the board
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****************************************************************/
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#define BOARD_NAME "PATI"
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int checkboard (void)
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{
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char s[50];
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ulong reg;
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char rev;
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int i;
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puts ("\nBoard: ");
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reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
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rev=(char)(SYSCNTR_BREV(reg)+'A');
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i = getenv_f("serial#", s, 32);
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if ((i == -1)) {
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puts ("### No HW ID - assuming " BOARD_NAME);
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printf(" Rev. %c\n",rev);
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}
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else {
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s[sizeof(BOARD_NAME)-1] = 0;
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printf ("%s-1 Rev %c SN: %s\n", s,rev,
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&s[sizeof(BOARD_NAME)]);
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}
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set_flash_vpp(1,0,0); /* set Flash VPP */
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return 0;
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}
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#ifdef CONFIG_SYS_PCI_CON_DEVICE
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/************************************************************************
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* PCI Communication
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*
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* Alive (Pinging):
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* ----------------
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* PCI Host sends message ALIVE, Local acknowledges with ALIVE
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*
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* PCI_CON console over PCI:
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* -------------------------
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* Local side:
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* - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
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* data is avaible (PCIMSG_CONN)
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* - uses PCI9056_MAILBOX1 to send data
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* - uses PCI9056_MAILBOX0 to receive data
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* PCI side:
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* - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
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* data is avaible (PCIMSG_CONN)
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* - uses PCI9056_MAILBOX0 to send data
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* - uses PCI9056_MAILBOX1 to receive data
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*
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* How it works:
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* Send:
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* - check if PCICON_TRANSMIT_REG is empty
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* - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
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* - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
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* is waiting
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* Receive:
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* - get an interrupt via the PCICON_ACK_REG register message
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* PCIMSG_CONN
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* - write the data from the PCICON_RECEIVE_REG into the receive
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* buffer and if the receive buffer is not full, clear the
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* PCICON_RECEIVE_REG (this allows the counterpart to write more data)
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* - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
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*
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* The PCICON_RECEIVE_REG must be cleared by the routine which reads
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* the receive buffer if the buffer is not full any more
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*
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*/
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#undef PCI_CON_DEBUG
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#ifdef PCI_CON_DEBUG
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#define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args)
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#else
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#define PCI_CON_PRINTF(fmt,args...)
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#endif
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/*********************************************************
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* we work only with a receive buffer on eiter side.
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* Transmit buffer is free, if mailbox is cleared.
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* Transmit character is or'ed with 0x80000000
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* PATI receive register MAILBOX0
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* PATI transmit register MAILBOX1
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*********************************************************/
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#define PCICON_RECEIVE_REG PCI9056_MAILBOX0
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#define PCICON_TRANSMIT_REG PCI9056_MAILBOX1
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#define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL
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#define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL
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#define PCIMSG_ALIVE 0x1
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#define PCIMSG_CONN 0x2
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#define PCIMSG_DISC 0x3
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#define PCIMSG_CON_DATA 0x5
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#define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE))
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#define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y))
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#define PCICON_TX_FLAG 0x80000000
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#define REC_BUFFER_SIZE 0x100
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int recbuf[REC_BUFFER_SIZE];
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static int r_ptr = 0;
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int w_ptr;
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struct stdio_dev pci_con_dev;
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int conn=0;
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int buff_full=0;
|
|
|
|
void pci_con_put_it(const char c)
|
|
{
|
|
/* Test for completition */
|
|
unsigned long reg;
|
|
do {
|
|
reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
|
|
}while(reg);
|
|
reg=PCICON_TX_FLAG + c;
|
|
PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
|
|
PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
|
|
}
|
|
|
|
void pci_con_putc(struct stdio_dev *dev, const char c)
|
|
{
|
|
pci_con_put_it(c);
|
|
if(c == '\n')
|
|
pci_con_put_it('\r');
|
|
}
|
|
|
|
|
|
int pci_con_getc(struct stdio_dev *dev)
|
|
{
|
|
int res;
|
|
int diff;
|
|
while(r_ptr==(volatile int)w_ptr);
|
|
res=recbuf[r_ptr++];
|
|
if(r_ptr==REC_BUFFER_SIZE)
|
|
r_ptr=0;
|
|
if(w_ptr<r_ptr)
|
|
diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
|
|
else
|
|
diff=r_ptr-w_ptr;
|
|
if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
|
|
/* clear Mail box */
|
|
buff_full=0;
|
|
PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
|
|
}
|
|
return res;
|
|
}
|
|
|
|
int pci_con_tstc(struct stdio_dev *dev)
|
|
{
|
|
if(r_ptr==(volatile int)w_ptr)
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
void pci_con_puts(struct stdio_dev *dev, const char *s)
|
|
{
|
|
while (*s) {
|
|
pci_con_putc(*s);
|
|
++s;
|
|
}
|
|
}
|
|
|
|
void pci_con_init (void)
|
|
{
|
|
w_ptr = 0;
|
|
r_ptr = 0;
|
|
PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
|
|
conn=1;
|
|
}
|
|
|
|
/*******************************************
|
|
* IRQ routine
|
|
******************************************/
|
|
int pci_dorbell_irq(void)
|
|
{
|
|
unsigned long reg,data;
|
|
int diff;
|
|
reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
|
|
PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
|
|
if(reg & (1<<20) ) {
|
|
/* read doorbell */
|
|
reg=PCICON_GET_REG(PCICON_ACK_REG);
|
|
switch(reg) {
|
|
case PCIMSG_ALIVE:
|
|
PCI_CON_PRINTF(" Alive\n");
|
|
PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
|
|
break;
|
|
case PCIMSG_CONN:
|
|
PCI_CON_PRINTF(" Conn %d",conn);
|
|
w_ptr = 0;
|
|
r_ptr = 0;
|
|
buff_full=0;
|
|
PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
|
|
conn=1;
|
|
PCI_CON_PRINTF(" ... %d\n",conn);
|
|
break;
|
|
case PCIMSG_CON_DATA:
|
|
data=PCICON_GET_REG(PCICON_RECEIVE_REG);
|
|
recbuf[w_ptr++]=(int)(data&0xff);
|
|
PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
|
|
r_ptr,w_ptr,recbuf[w_ptr-1]);
|
|
if(w_ptr==REC_BUFFER_SIZE)
|
|
w_ptr=0;
|
|
if(w_ptr<r_ptr)
|
|
diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
|
|
else
|
|
diff=r_ptr-w_ptr;
|
|
if(diff>(REC_BUFFER_SIZE-4))
|
|
buff_full=1;
|
|
else
|
|
/* clear Mail box */
|
|
PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
|
|
break;
|
|
default:
|
|
serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
|
|
}
|
|
/* clear IRQ */
|
|
PCICON_SET_REG(PCICON_ACK_REG,~0L);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void pci_con_connect(void)
|
|
{
|
|
unsigned long reg;
|
|
conn=0;
|
|
reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
|
|
/* default 0x0f010180 */
|
|
reg &= 0xff000000;
|
|
reg |= 0x00030000; /* enable local dorbell */
|
|
reg |= 0x00000300; /* enable PCI dorbell */
|
|
PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
|
|
irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
|
|
memset (&pci_con_dev, 0, sizeof (pci_con_dev));
|
|
strcpy (pci_con_dev.name, "pci_con");
|
|
pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
|
|
pci_con_dev.putc = pci_con_putc;
|
|
pci_con_dev.puts = pci_con_puts;
|
|
pci_con_dev.getc = pci_con_getc;
|
|
pci_con_dev.tstc = pci_con_tstc;
|
|
stdio_register (&pci_con_dev);
|
|
printf("PATI ready for PCI connection, type ctrl-c for exit\n");
|
|
do {
|
|
udelay(10);
|
|
if((volatile int)conn)
|
|
break;
|
|
if(ctrlc()) {
|
|
irq_free_handler(0x2);
|
|
return;
|
|
}
|
|
}while(1);
|
|
console_assign(stdin,"pci_con");
|
|
console_assign(stderr,"pci_con");
|
|
console_assign(stdout,"pci_con");
|
|
}
|
|
|
|
void pci_con_disc(void)
|
|
{
|
|
console_assign(stdin,"serial");
|
|
console_assign(stderr,"serial");
|
|
console_assign(stdout,"serial");
|
|
PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
|
|
/* reconnection */
|
|
irq_free_handler(0x02);
|
|
pci_con_connect();
|
|
}
|
|
#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
|
|
|
|
/*
|
|
* Absolute environment address for linker file.
|
|
*/
|
|
GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
|