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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'mpc8349ads'
This commit is contained in:
commit
b443f7b628
@ -2,7 +2,6 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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<<<<<<< HEAD/CHANGELOG
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* Fixed PCI indirect config ops to handle multiple PCI controllers
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We need to adjust the bus number we are trying to access based
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on which PCI controller its on
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@ -136,6 +136,7 @@ pci_init_board(void)
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volatile pciconf8349_t * pci_conf;
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u16 reg16;
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u32 reg32;
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u32 dev;
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struct pci_controller * hose;
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immr = (immap_t *)CFG_IMMRBAR;
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@ -200,7 +201,7 @@ pci_init_board(void)
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/* PCI1 IO space */
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pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
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/* PCI1 mmio - non-prefetch mem space */
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pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
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@ -261,21 +262,17 @@ pci_init_board(void)
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* Write to Command register
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*/
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reg16 = 0xff;
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pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
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®16);
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
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reg16);
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
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0xffff);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
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0x80);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
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0x08);
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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@ -300,7 +297,7 @@ pci_init_board(void)
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/* PCI2 IO space */
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pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
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/* PCI2 mmio - non-prefetch mem space */
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pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
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@ -361,21 +358,17 @@ pci_init_board(void)
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* Write to Command register
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*/
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reg16 = 0xff;
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pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
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®16);
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dev = PCI_BDF(hose->first_busno, 0, 0);
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pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
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reg16);
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pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
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0xffff);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
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0x80);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
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0x08);
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pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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/*
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* Hose scan.
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@ -332,7 +332,7 @@
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#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xe2000000
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#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
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#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
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#define CFG_PCI2_MEM_BASE 0xa0000000
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#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
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@ -341,8 +341,8 @@
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#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
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#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI2_IO_BASE 0x00000000
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#define CFG_PCI2_IO_PHYS 0xe3000000
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#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
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#define CFG_PCI2_IO_PHYS 0xe2100000
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#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
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#if defined(CONFIG_PCI)
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#define PCI_ALL_PCI1
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