mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
Merge branch 'mpc8349ads'
This commit is contained in:
Kumar Gala
commit
06508f1c9b
@ -2,6 +2,7 @@
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Changes since U-Boot 1.1.4:
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======================================================================
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<<<<<<< HEAD/CHANGELOG
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* Fixed PCI indirect config ops to handle multiple PCI controllers
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We need to adjust the bus number we are trying to access based
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on which PCI controller its on
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@ -23,6 +23,7 @@
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#include <common.h>
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#include <asm/global_data.h>
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#include <pci.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#ifdef CONFIG_PCI
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@ -163,7 +164,20 @@ pci_init_board(void)
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pci_ctrl[0].gcr = 0;
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udelay(2000);
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pci_ctrl[0].gcr = 1;
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#ifdef CONFIG_MPC83XX_PCI2
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pci_ctrl[1].gcr = 0;
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udelay(2000);
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pci_ctrl[1].gcr = 1;
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#endif
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/* We need to wait at least a 1sec based on PCI specs */
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{
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int i;
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for (i = 0; i < 1000; ++i)
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udelay (1000);
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}
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/*
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* Configure PCI Local Access Windows
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@ -178,16 +192,21 @@ pci_init_board(void)
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI1 mem space */
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/* PCI1 mem space - prefetch */
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pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
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pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI1 IO space */
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pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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/* PCI1 mmio - non-prefetch mem space */
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pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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@ -197,33 +216,40 @@ pci_init_board(void)
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pci_ctrl[0].pitar1 = 0x0;
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pci_ctrl[0].pibar1 = 0x0;
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pci_ctrl[0].piebar1 = 0x0;
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pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G;
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pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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/* PCI memory space */
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MMIO_BASE,
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CFG_PCI1_MMIO_PHYS,
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CFG_PCI1_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 2,
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 3;
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CFG_IMMRBAR+0x8300),
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@ -248,6 +274,8 @@ pci_init_board(void)
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0xffff);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
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0x80);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
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0x08);
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#ifdef CONFIG_PCI_SCAN_SHOW
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printf("PCI: Bus Dev VenId DevId Class Int\n");
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@ -256,5 +284,104 @@ pci_init_board(void)
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#ifdef CONFIG_MPC83XX_PCI2
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hose = &pci_hose[1];
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/*
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* Configure PCI Outbound Translation Windows
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*/
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/* PCI2 mem space - prefetch */
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pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
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/* PCI2 IO space */
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pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
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/* PCI2 mmio - non-prefetch mem space */
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pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
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pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
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pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
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/*
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* Configure PCI Inbound Translation Windows
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*/
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/* we need RAM mapped to PCI space for the devices to
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* access main memory */
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pci_ctrl[1].pitar1 = 0x0;
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pci_ctrl[1].pibar1 = 0x0;
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pci_ctrl[1].piebar1 = 0x0;
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pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
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hose->first_busno = pci_hose[0].last_busno + 1;
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hose->last_busno = 0xff;
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/* PCI memory prefetch space */
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pci_set_region(hose->regions + 0,
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CFG_PCI2_MEM_BASE,
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CFG_PCI2_MEM_PHYS,
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CFG_PCI2_MEM_SIZE,
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PCI_REGION_MEM|PCI_REGION_PREFETCH);
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/* PCI memory space */
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pci_set_region(hose->regions + 1,
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CFG_PCI2_MMIO_BASE,
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CFG_PCI2_MMIO_PHYS,
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CFG_PCI2_MMIO_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 2,
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CFG_PCI2_IO_BASE,
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CFG_PCI2_IO_PHYS,
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CFG_PCI2_IO_SIZE,
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PCI_REGION_IO);
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/* System memory space */
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pci_set_region(hose->regions + 3,
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CONFIG_PCI_SYS_MEM_BUS,
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CONFIG_PCI_SYS_MEM_PHYS,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 4;
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pci_setup_indirect(hose,
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(CFG_IMMRBAR+0x8380),
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(CFG_IMMRBAR+0x8384));
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pci_register_hose(hose);
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/*
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* Write to Command register
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*/
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reg16 = 0xff;
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pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND,
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®16);
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reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND,
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reg16);
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/*
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* Clear non-reserved bits in status register.
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*/
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pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS,
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0xffff);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER,
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0x80);
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pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_CACHE_LINE_SIZE,
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0x08);
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/*
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* Hose scan.
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*/
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hose->last_busno = pci_hose_scan(hose);
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#endif
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}
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#endif /* CONFIG_PCI */
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@ -77,6 +77,7 @@
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#define POCMR_ENABLE 0x80000000
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#define POCMR_PCI_IO 0x40000000
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#define POCMR_PREFETCH_EN 0x20000000
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#define POCMR_PCI2 0x10000000
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/* Soft PCI reset */
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@ -42,6 +42,7 @@
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#define CONFIG_MPC8349ADS 1 /* MPC8349ADS board specific */
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#define CONFIG_PCI
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#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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@ -322,16 +323,23 @@
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_MMIO_BASE 0x90000000
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#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
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#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xe2000000
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#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
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#define CFG_PCI2_MEM_BASE 0xA0000000
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#define CFG_PCI2_MEM_BASE 0xa0000000
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#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
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#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI2_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI2_MMIO_BASE 0xb0000000
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#define CFG_PCI2_MMIO_PHYS CFG_PCI2_MMIO_BASE
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#define CFG_PCI2_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI2_IO_BASE 0x00000000
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#define CFG_PCI2_IO_PHYS 0xe3000000
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#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
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