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Merge branch 'master' of git://git.denx.de/u-boot

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This commit is contained in:
Stefano Babic 2015-03-05 16:05:10 +01:00
commit 9b5b60a05c
244 changed files with 6466 additions and 886 deletions
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18
Kconfig
View File

@ -96,6 +96,24 @@ config SPL
help
If you want to build SPL as well as the normal image, say Y.
config SPL_STACK_R
depends on SPL
bool "Enable SDRAM location for SPL stack"
help
SPL starts off execution in SRAM and thus typically has only a small
stack available. Since SPL sets up DRAM while in its board_init_f()
function, it is possible for the stack to move there before
board_init_r() is reached. This option enables a special SDRAM
location for the SPL stack. U-Boot SPL switches to this after
board_init_f() completes, and before board_init_r() starts.
config SPL_STACK_R_ADDR
depends on SPL_STACK_R
hex "SDRAM location for SPL stack"
help
Specify the address in SDRAM for the SPL stack. This will be set up
before board_init_r() is called.
config TPL
bool
depends on SPL && SUPPORT_TPL

14
MAINTAINERS
View File

@ -148,7 +148,7 @@ F: arch/arm/mach-tegra/
F: arch/arm/include/asm/arch-tegra*/
ARM TI
M: Tom Rini <trini@ti.com>
M: Tom Rini <trini@konsulko.com>
S: Maintained
T: git git://git.denx.de/u-boot-ti.git
F: arch/arm/cpu/arm926ejs/davinci/
@ -162,8 +162,7 @@ ARM UNIPHIER
M: Masahiro Yamada <yamada.m@jp.panasonic.com>
S: Maintained
T: git git://git.denx.de/u-boot-uniphier.git
F: arch/arm/cpu/armv7/uniphier/
F: arch/arm/include/asm/arch-uniphier/
F: arch/arm/mach-uniphier/
F: configs/ph1_*_defconfig
N: uniphier
@ -173,6 +172,12 @@ S: Maintained
F: arch/arm/cpu/armv7/zynq/
F: arch/arm/include/asm/arch-zynq/
ARM ZYNQMP
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
F: arch/arm/cpu/armv8/zynqmp/
F: arch/arm/include/asm/arch-zynqmp/
AVR32
M: Andreas Bießmann <andreas.devel@googlemail.com>
S: Maintained
@ -209,6 +214,7 @@ M: Lukasz Majewski <l.majewski@samsung.com>
S: Maintained
T: git git://git.denx.de/u-boot-dfu.git
F: drivers/dfu/
F: drivers/usb/gadget/
DRIVER MODEL
M: Simon Glass <sjg@chromium.org>
@ -411,7 +417,7 @@ T: git git://git.denx.de/u-boot-x86.git
F: arch/x86/
THE REST
M: Tom Rini <trini@ti.com>
M: Tom Rini <trini@konsulko.com>
L: u-boot@lists.denx.de
Q: http://patchwork.ozlabs.org/project/uboot/list/
S: Maintained

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2015
PATCHLEVEL = 04
SUBLEVEL =
EXTRAVERSION = -rc2
EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*

69
README
View File

@ -273,6 +273,75 @@ run some of U-Boot's tests.
See board/sandbox/README.sandbox for more details.
Board Initialisation Flow:
--------------------------
This is the intended start-up flow for boards. This should apply for both
SPL and U-Boot proper (i.e. they both follow the same rules). At present SPL
mostly uses a separate code path, but the funtion names and roles of each
function are the same. Some boards or architectures may not conform to this.
At least most ARM boards which use CONFIG_SPL_FRAMEWORK conform to this.
Execution starts with start.S with three functions called during init after
that. The purpose and limitations of each is described below.
lowlevel_init():
- purpose: essential init to permit execution to reach board_init_f()
- no global_data or BSS
- there is no stack (ARMv7 may have one but it will soon be removed)
- must not set up SDRAM or use console
- must only do the bare minimum to allow execution to continue to
board_init_f()
- this is almost never needed
- return normally from this function
board_init_f():
- purpose: set up the machine ready for running board_init_r():
i.e. SDRAM and serial UART
- global_data is available
- stack is in SRAM
- BSS is not available, so you cannot use global/static variables,
only stack variables and global_data
Non-SPL-specific notes:
- dram_init() is called to set up DRAM. If already done in SPL this
can do nothing
SPL-specific notes:
- you can override the entire board_init_f() function with your own
version as needed.
- preloader_console_init() can be called here in extremis
- should set up SDRAM, and anything needed to make the UART work
- these is no need to clear BSS, it will be done by crt0.S
- must return normally from this function (don't call board_init_r()
directly)
Here the BSS is cleared. For SPL, if CONFIG_SPL_STACK_R is defined, then at
this point the stack and global_data are relocated to below
CONFIG_SPL_STACK_R_ADDR. For non-SPL, U-Boot is relocated to run at the top of
memory.
board_init_r():
- purpose: main execution, common code
- global_data is available
- SDRAM is available
- BSS is available, all static/global variables can be used
- execution eventually continues to main_loop()
Non-SPL-specific notes:
- U-Boot is relocated to the top of memory and is now running from
there.
SPL-specific notes:
- stack is optionally in SDRAM, if CONFIG_SPL_STACK_R is defined and
CONFIG_SPL_STACK_R_ADDR points into SDRAM
- preloader_console_init() can be called here - typically this is
done by defining CONFIG_SPL_BOARD_INIT and then supplying a
spl_board_init() function containing this call
- loads U-Boot or (in falcon mode) Linux
Configuration Options:
----------------------

7
arch/arm/Kconfig
View File

@ -596,6 +596,10 @@ config ZYNQ
select CPU_V7
select SUPPORT_SPL
config TARGET_XILINX_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
select ARM64
config TEGRA
bool "NVIDIA Tegra"
select SUPPORT_SPL
@ -727,7 +731,7 @@ source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/cpu/armv7/uniphier/Kconfig"
source "arch/arm/mach-uniphier/Kconfig"
source "arch/arm/mach-versatile/Kconfig"
@ -845,6 +849,7 @@ source "board/wandboard/Kconfig"
source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/xaeniax/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"

1
arch/arm/Makefile
View File

@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_NOMADIK) += nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_TEGRA) += tegra
machine-$(CONFIG_ARCH_UNIPHIER) += uniphier
machine-$(CONFIG_ARCH_VERSATILE) += versatile
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))

1
arch/arm/cpu/armv7/Makefile
View File

@ -56,6 +56,5 @@ obj-$(CONFIG_SOCFPGA) += socfpga/
obj-$(if $(filter stv0991,$(SOC)),y) += stv0991/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_U8500) += u8500/
obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
obj-$(CONFIG_VF610) += vf610/
obj-$(CONFIG_ZYNQ) += zynq/

13
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -275,6 +275,14 @@ static void watchdog_disable(void)
;
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
board_early_init_f();
sdram_init();
}
#endif
void s_init(void)
{
/*
@ -290,6 +298,7 @@ void s_init(void)
setup_clocks_for_console();
uart_soft_reset();
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
/* TODO: This does not work, gd is not available yet */
gd->baudrate = CONFIG_BAUDRATE;
serial_init();
gd->have_console = 1;
@ -298,9 +307,5 @@ void s_init(void)
/* Enable RTC32K clock */
rtc32k_enable();
#endif
#ifdef CONFIG_SPL_BUILD
board_early_init_f();
sdram_init();
#endif
}
#endif

2
arch/arm/cpu/armv7/exynos/Makefile
View File

@ -7,6 +7,8 @@
obj-y += clock.o power.o soc.o system.o pinmux.o tzpc.o
obj-$(CONFIG_EXYNOS5420) += sec_boot.o
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_EXYNOS5) += clock_init_exynos5.o
obj-$(CONFIG_EXYNOS5) += dmc_common.o dmc_init_ddr3.o

62
arch/arm/cpu/armv7/exynos/common_setup.h
View File

@ -23,6 +23,8 @@
* MA 02111-1307 USA
*/
#include <asm/arch/system.h>
#define DMC_OFFSET 0x10000
/*
@ -43,3 +45,63 @@ void system_clock_init(void);
int do_lowlevel_init(void);
void sdelay(unsigned long);
enum l2_cache_params {
CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
CACHE_DATA_RAM_SETUP = (1 << 5),
CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
CACHE_TAG_RAM_SETUP = (1 << 9),
CACHE_ECC_AND_PARITY = (1 << 21),
CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
};
#ifndef CONFIG_SYS_L2CACHE_OFF
/*
* Configure L2CTLR to get timings that keep us from hanging/crashing.
*
* Must be inline here since low_power_start() is called without a
* stack (!).
*/
static inline void configure_l2_ctlr(void)
{
uint32_t val;
mrc_l2_ctlr(val);
val |= CACHE_TAG_RAM_SETUP |
CACHE_DATA_RAM_SETUP |
CACHE_TAG_RAM_LATENCY_2_CYCLES |
CACHE_DATA_RAM_LATENCY_2_CYCLES;
if (proid_is_exynos5420() || proid_is_exynos5800()) {
val |= CACHE_ECC_AND_PARITY |
CACHE_TAG_RAM_LATENCY_3_CYCLES |
CACHE_DATA_RAM_LATENCY_3_CYCLES;
}
mcr_l2_ctlr(val);
}
/*
* Configure L2ACTLR.
*
* Must be inline here since low_power_start() is called without a
* stack (!).
*/
static inline void configure_l2_actlr(void)
{
uint32_t val;
if (proid_is_exynos5420() || proid_is_exynos5800()) {
mrc_l2_aux_ctlr(val);
val |= CACHE_ENABLE_FORCE_L2_LOGIC |
CACHE_DISABLE_CLEAN_EVICT;
mcr_l2_aux_ctlr(val);
}
}
#endif

3
arch/arm/cpu/armv7/exynos/exynos5_setup.h
View File

@ -700,6 +700,9 @@
#define CLK_DIV_CPERI1_VAL NOT_AVAILABLE
#else
#define CPU_CONFIG_STATUS_OFFSET 0x80
#define CPU_RST_FLAG_VAL 0xFCBA0D10
#define PAD_RETENTION_DRAM_COREBLK_VAL 0x10000000
/* APLL_CON1 */

147
arch/arm/cpu/armv7/exynos/lowlevel_init.c
View File

@ -31,7 +31,10 @@
#include <asm/arch/tzpc.h>
#include <asm/arch/periph.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/system.h>
#include <asm/armv7.h>
#include "common_setup.h"
#include "exynos5_setup.h"
/* These are the things we can do during low-level init */
enum {
@ -42,6 +45,128 @@ enum {
DO_POWER = 1 << 4,
};
#ifdef CONFIG_EXYNOS5420
/*
* Power up secondary CPUs.
*/
static void secondary_cpu_start(void)
{
v7_enable_smp(EXYNOS5420_INFORM_BASE);
svc32_mode_en();
branch_bx(CONFIG_EXYNOS_RELOCATE_CODE_BASE);
}
/*
* This is the entry point of hotplug-in and
* cluster switching.
*/
static void low_power_start(void)
{
uint32_t val, reg_val;
reg_val = readl(EXYNOS5420_SPARE_BASE);
if (reg_val != CPU_RST_FLAG_VAL) {
writel(0x0, CONFIG_LOWPOWER_FLAG);
branch_bx(0x0);
}
reg_val = readl(CONFIG_PHY_IRAM_BASE + 0x4);
if (reg_val != (uint32_t)&low_power_start) {
/* Store jump address as low_power_start if not present */
writel((uint32_t)&low_power_start, CONFIG_PHY_IRAM_BASE + 0x4);
dsb();
sev();
}
/* Set the CPU to SVC32 mode */
svc32_mode_en();
#ifndef CONFIG_SYS_L2CACHE_OFF
/* Read MIDR for Primary Part Number */
mrc_midr(val);
val = (val >> 4);
val &= 0xf;
if (val == 0xf) {
configure_l2_ctlr();
configure_l2_actlr();
v7_enable_l2_hazard_detect();
}
#endif
/* Invalidate L1 & TLB */
val = 0x0;
mcr_tlb(val);
mcr_icache(val);
/* Disable MMU stuff and caches */
mrc_sctlr(val);
val &= ~((0x2 << 12) | 0x7);
val |= ((0x1 << 12) | (0x8 << 8) | 0x2);
mcr_sctlr(val);
/* CPU state is hotplug or reset */
secondary_cpu_start();
/* Core should not enter into WFI here */
wfi();
}
/*
* Pointer to this function is stored in iRam which is used
* for jump and power down of a specific core.
*/
static void power_down_core(void)
{
uint32_t tmp, core_id, core_config;
/* Get the unique core id */
/*
* Multiprocessor Affinity Register
* [11:8] Cluster ID
* [1:0] CPU ID
*/
mrc_mpafr(core_id);
tmp = core_id & 0x3;
core_id = (core_id >> 6) & ~3;
core_id |= tmp;
core_id &= 0x3f;
/* Set the status of the core to low */
core_config = (core_id * CPU_CONFIG_STATUS_OFFSET);
core_config += EXYNOS5420_CPU_CONFIG_BASE;
writel(0x0, core_config);
/* Core enter WFI */
wfi();
}
/*
* Configurations for secondary cores are inapt at this stage.
* Reconfigure secondary cores. Shutdown and change the status
* of all cores except the primary core.
*/
static void secondary_cores_configure(void)
{
/* Clear secondary boot iRAM base */
writel(0x0, (CONFIG_EXYNOS_RELOCATE_CODE_BASE + 0x1C));
/* set lowpower flag and address */
writel(CPU_RST_FLAG_VAL, CONFIG_LOWPOWER_FLAG);
writel((uint32_t)&low_power_start, CONFIG_LOWPOWER_ADDR);
writel(CPU_RST_FLAG_VAL, EXYNOS5420_SPARE_BASE);
/* Store jump address for power down */
writel((uint32_t)&power_down_core, CONFIG_PHY_IRAM_BASE + 0x4);
/* Need all core power down check */
dsb();
sev();
}
extern void relocate_wait_code(void);
#endif
int do_lowlevel_init(void)
{
uint32_t reset_status;
@ -49,6 +174,28 @@ int do_lowlevel_init(void)
arch_cpu_init();
#ifndef CONFIG_SYS_L2CACHE_OFF
/*
* Init L2 cache parameters here for use by boot and resume
*
* These are here instead of in v7_outer_cache_enable() so that the
* L2 cache settings get properly set even at resume time or if we're
* running U-Boot with the cache off. The kernel still needs us to
* set these for it.
*/
configure_l2_ctlr();
configure_l2_actlr();
dsb();
isb();
#endif
#ifdef CONFIG_EXYNOS5420
relocate_wait_code();
/* Reconfigure secondary cores */
secondary_cores_configure();
#endif
reset_status = get_reset_status();
switch (reset_status) {

128
arch/arm/cpu/armv7/exynos/sec_boot.S Normal file
View File

@ -0,0 +1,128 @@
/*
* Copyright (C) 2013 Samsung Electronics
* Akshay Saraswat <akshay.s@samsung.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <asm/arch/cpu.h>
.globl relocate_wait_code
relocate_wait_code:
adr r0, code_base @ r0: source address (start)
adr r1, code_end @ r1: source address (end)
ldr r2, =0x02073000 @ r2: target address
1:
ldmia r0!, {r3-r6}
stmia r2!, {r3-r6}
cmp r0, r1
blt 1b
b code_end
.ltorg
/*
* Secondary core waits here until Primary wake it up.
* Below code is copied to CONFIG_EXYNOS_RELOCATE_CODE_BASE.
* This is a workaround code which is supposed to act as a
* substitute/supplement to the iROM code.
*
* This workaround code is relocated to the address 0x02073000
* because that comes out to be the last 4KB of the iRAM
* (Base Address - 0x02020000, Limit Address - 0x020740000).
*
* U-boot and kernel are aware of this code and flags by the simple
* fact that we are implementing a workaround in the last 4KB
* of the iRAM and we have already defined these flag and address
* values in both kernel and U-boot for our use.
*/
code_base:
b 1f
/*
* These addresses are being used as flags in u-boot and kernel.
*
* Jump address for resume and flag to check for resume/reset:
* Resume address - 0x2073008
* Resume flag - 0x207300C
*
* Jump address for cluster switching:
* Switch address - 0x2073018
*
* Jump address for core hotplug:
* Hotplug address - 0x207301C
*
* Jump address for C2 state (Reserved for future not being used right now):
* C2 address - 0x2073024
*
* Managed per core status for the active cluster:
* CPU0 state - 0x2073028
* CPU1 state - 0x207302C
* CPU2 state - 0x2073030
* CPU3 state - 0x2073034
*
* Managed per core GIC status for the active cluster:
* CPU0 gic state - 0x2073038
* CPU1 gic state - 0x207303C
* CPU2 gic state - 0x2073040
* CPU3 gic state - 0x2073044
*
* Logic of the code:
* Step-1: Read current CPU status.
* Step-2: If it's a resume then continue, else jump to step 4.
* Step-3: Clear inform1 PMU register and jump to inform0 value.
* Step-4: If it's a switch, C2 or reset, get the hotplug address.
* Step-5: If address is not available, enter WFE.
* Step-6: If address is available, jump to that address.
*/
nop @ for backward compatibility
.word 0x0 @ REG0: RESUME_ADDR
.word 0x0 @ REG1: RESUME_FLAG
.word 0x0 @ REG2
.word 0x0 @ REG3
_switch_addr:
.word 0x0 @ REG4: SWITCH_ADDR
_hotplug_addr:
.word 0x0 @ REG5: CPU1_BOOT_REG
.word 0x0 @ REG6
_c2_addr:
.word 0x0 @ REG7: REG_C2_ADDR
_cpu_state:
.word 0x1 @ CPU0_STATE : RESET
.word 0x2 @ CPU1_STATE : SECONDARY RESET
.word 0x2 @ CPU2_STATE : SECONDARY RESET
.word 0x2 @ CPU3_STATE : SECONDARY RESET
_gic_state:
.word 0x0 @ CPU0 - GICD_IGROUPR0
.word 0x0 @ CPU1 - GICD_IGROUPR0
.word 0x0 @ CPU2 - GICD_IGROUPR0
.word 0x0 @ CPU3 - GICD_IGROUPR0
1:
adr r0, _cpu_state
mrc p15, 0, r7, c0, c0, 5 @ read MPIDR
and r7, r7, #0xf @ r7 = cpu id
/* Read the current cpu state */
ldr r10, [r0, r7, lsl #2]
svc_entry:
tst r10, #(1 << 4)
adrne r0, _switch_addr
bne wait_for_addr
/* Clear INFORM1 */
ldr r0, =(0x10040000 + 0x804)
ldr r1, [r0]
cmp r1, #0x0
movne r1, #0x0
strne r1, [r0]
/* Get INFORM0 */
ldrne r1, =(0x10040000 + 0x800)
ldrne pc, [r1]
tst r10, #(1 << 0)
ldrne pc, =0x23e00000
adr r0, _hotplug_addr
wait_for_addr:
ldr r1, [r0]
cmp r1, #0x0
bxne r1
wfe
b wait_for_addr
.ltorg
code_end:
mov pc, lr

35
arch/arm/cpu/armv7/exynos/soc.c
View File

@ -9,13 +9,6 @@
#include <asm/io.h>
#include <asm/system.h>
enum l2_cache_params {
CACHE_TAG_RAM_SETUP = (1 << 9),
CACHE_DATA_RAM_SETUP = (1 << 5),
CACHE_TAG_RAM_LATENCY = (2 << 6),
CACHE_DATA_RAM_LATENCY = (2 << 0)
};
void reset_cpu(ulong addr)
{
writel(0x1, samsung_get_base_swreset());
@ -28,31 +21,3 @@ void enable_caches(void)
dcache_enable();
}
#endif
#ifndef CONFIG_SYS_L2CACHE_OFF
/*
* Set L2 cache parameters
*/
static void exynos5_set_l2cache_params(void)
{
unsigned int val = 0;
asm volatile("mrc p15, 1, %0, c9, c0, 2\n" : "=r"(val));
val |= CACHE_TAG_RAM_SETUP |
CACHE_DATA_RAM_SETUP |
CACHE_TAG_RAM_LATENCY |
CACHE_DATA_RAM_LATENCY;
asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
}
/*
* Sets L2 cache related parameters before enabling data cache
*/
void v7_outer_cache_enable(void)
{
if (cpu_is_exynos5())
exynos5_set_l2cache_params();
}
#endif

22
arch/arm/cpu/armv7/lowlevel_init.S
View File

@ -17,16 +17,24 @@
ENTRY(lowlevel_init)
/*
* Setup a temporary stack
* Setup a temporary stack. Global data is not available yet.
*/
ldr sp, =CONFIG_SYS_INIT_SP_ADDR
bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
#ifdef CONFIG_DM
mov r9, #0
#else
/*
* Set up global data for boards that still need it. This will be
* removed soon.
*/
#ifdef CONFIG_SPL_BUILD
ldr r9, =gdata
#else
sub sp, sp, #GD_SIZE
bic sp, sp, #7
mov r9, sp
#endif
#endif
/*
* Save the old lr(passed in ip) and the current lr to stack
@ -34,7 +42,17 @@ ENTRY(lowlevel_init)
push {ip, lr}
/*
* go setup pll, mux, memory
* Call the very early init function. This should do only the
* absolute bare minimum to get started. It should not:
*
* - set up DRAM
* - use global_data
* - clear BSS
* - try to start a console
*
* For boards with SPL this should be empty since SPL can do all of
* this init in the SPL board_init_f() function which is called
* immediately after this.
*/
bl s_init
pop {ip, pc}

6
arch/arm/cpu/armv7/omap-common/hwinit-common.c
View File

@ -128,14 +128,18 @@ void s_init(void)
do_io_settings();
#endif
prcm_init();
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
#ifdef CONFIG_BOARD_EARLY_INIT_F
board_early_init_f();
#endif
/* For regular u-boot sdram_init() is called from dram_init() */
sdram_init();
#endif
}
#endif
/*
* Routine: wait_for_command_complete

12
arch/arm/cpu/armv7/omap3/board.c
View File

@ -240,8 +240,6 @@ void try_unlock_memory(void)
*****************************************************************************/
void s_init(void)
{
int in_sdram = is_running_in_sdram();
watchdog_init();
try_unlock_memory();
@ -264,11 +262,15 @@ void s_init(void)
#ifdef CONFIG_USB_EHCI_OMAP
ehci_clocks_enable();
#endif
if (!in_sdram)
mem_init();
}
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
mem_init();
}
#endif
/*
* Routine: misc_init_r
* Description: A basic misc_init_r that just displays the die ID

6
arch/arm/cpu/armv7/rmobile/Kconfig
View File

@ -24,6 +24,9 @@ config TARGET_ALT
config TARGET_SILK
bool "Silk board"
config TARGET_PORTER
bool "Porter board"
endchoice
config SYS_SOC
@ -31,7 +34,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool "Enable boot from RAM"
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK
depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK
default n
source "board/atmark-techno/armadillo-800eva/Kconfig"
@ -41,5 +44,6 @@ source "board/renesas/lager/Kconfig"
source "board/kmc/kzm9g/Kconfig"
source "board/renesas/alt/Kconfig"
source "board/renesas/silk/Kconfig"
source "board/renesas/porter/Kconfig"
endif

1001
arch/arm/cpu/armv7/rmobile/pfc-r8a7790.c
View File

File diff suppressed because it is too large Load Diff

148
arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c
View File

@ -151,8 +151,18 @@ enum {
FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
/* IPSR0 */
FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
/*
* From IPSR0 to IPSR5 have been removed because they does not use.
* From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@ -285,8 +295,20 @@ enum {
SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
SD1_DATA2_MARK, SD1_DATA3_MARK,
/* IPSR0 */
SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
/*
* From IPSR0 to IPSR5 have been removed because they does not use.
* From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@ -399,8 +421,55 @@ static pinmux_enum_t pinmux_data[] = {
PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2),
PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3),
/* IPSR0 */
PINMUX_IPSR_DATA(IP0_0, SD1_CD),
PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0),
PINMUX_IPSR_DATA(IP0_9_8, SD1_WP),
PINMUX_IPSR_DATA(IP0_9_8, IRQ7),
PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0),
PINMUX_IPSR_DATA(IP0_10, MMC_CLK),
PINMUX_IPSR_DATA(IP0_10, SD2_CLK),
PINMUX_IPSR_DATA(IP0_11, MMC_CMD),
PINMUX_IPSR_DATA(IP0_11, SD2_CMD),
PINMUX_IPSR_DATA(IP0_12, MMC_D0),
PINMUX_IPSR_DATA(IP0_12, SD2_DATA0),
PINMUX_IPSR_DATA(IP0_13, MMC_D1),
PINMUX_IPSR_DATA(IP0_13, SD2_DATA1),
PINMUX_IPSR_DATA(IP0_14, MMC_D2),
PINMUX_IPSR_DATA(IP0_14, SD2_DATA2),
PINMUX_IPSR_DATA(IP0_15, MMC_D3),
PINMUX_IPSR_DATA(IP0_15, SD2_DATA3),
PINMUX_IPSR_DATA(IP0_16, MMC_D4),
PINMUX_IPSR_DATA(IP0_16, SD2_CD),
PINMUX_IPSR_DATA(IP0_17, MMC_D5),
PINMUX_IPSR_DATA(IP0_17, SD2_WP),
PINMUX_IPSR_DATA(IP0_19_18, MMC_D6),
PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0),
PINMUX_IPSR_DATA(IP0_21_20, MMC_D7),
PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0),
PINMUX_IPSR_DATA(IP0_23_22, D0),
PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
PINMUX_IPSR_DATA(IP0_23_22, IRQ4),
PINMUX_IPSR_DATA(IP0_24, D1),
PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
PINMUX_IPSR_DATA(IP0_25, D2),
PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
PINMUX_IPSR_DATA(IP0_27_26, D3),
PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
PINMUX_IPSR_DATA(IP0_29_28, D4),
PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
PINMUX_IPSR_DATA(IP0_31_30, D5),
PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
/*
* From IPSR0 to IPSR5 have been removed because they does not use.
* From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@ -674,8 +743,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0),
GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3),
/* IPSR0 */
GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7),
GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD),
GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1),
GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2),
GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4),
GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6),
GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX),
GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B),
GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4),
GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B),
GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4),
GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5),
GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D),
/*
* From IPSR0 to IPSR5 have been removed because they does not use
* From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@ -1017,9 +1101,63 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
GP_6_1_FN, FN_SD0_CMD,
GP_6_0_FN, FN_SD0_CLK }
},
{ PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
2, 1, 1, 1, 1, 1, 1, 1, 1) {
/* IP0_31_30 [2] */
FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
/* IP0_29_28 [2] */
FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
/* IP0_27_26 [2] */
FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
/* IP0_25 [1] */
FN_D2, FN_SCIFA3_TXD_B,
/* IP0_24 [1] */
FN_D1, FN_SCIFA3_RXD_B,
/* IP0_23_22 [2] */
FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
/* IP0_21_20 [2] */
FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
/* IP0_19_18 [2] */
FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
/* IP0_17 [1] */
FN_MMC_D5, FN_SD2_WP,
/* IP0_16 [1] */
FN_MMC_D4, FN_SD2_CD,
/* IP0_15 [1] */
FN_MMC_D3, FN_SD2_DATA3,
/* IP0_14 [1] */
FN_MMC_D2, FN_SD2_DATA2,
/* IP0_13 [1] */
FN_MMC_D1, FN_SD2_DATA1,
/* IP0_12 [1] */
FN_MMC_D0, FN_SD2_DATA0,
/* IP0_11 [1] */
FN_MMC_CMD, FN_SD2_CMD,
/* IP0_10 [1] */
FN_MMC_CLK, FN_SD2_CLK,
/* IP0_9_8 [2] */
FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
/* IP0_7 [1] */
0, 0,
/* IP0_6 [1] */
0, 0,
/* IP0_5 [1] */
0, 0,
/* IP0_4 [1] */
0, 0,
/* IP0_3 [1] */
0, 0,
/* IP0_2 [1] */
0, 0,
/* IP0_1 [1] */
0, 0,
/* IP0_0 [1] */
FN_SD1_CD, FN_CAN0_RX, }
},
/*
* From IPSR0 to IPSR5 have been removed because they does not use.
* From IPSR1 to IPSR5 have been removed because they does not use.
*/
{ PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,

29
arch/arm/cpu/armv7/uniphier/ph1-ld4/clkrst_init.c
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

28
arch/arm/cpu/armv7/uniphier/ph1-ld4/sg_init.c
View File

@ -1,28 +0,0 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

29
arch/arm/cpu/armv7/uniphier/ph1-pro4/clkrst_init.c
View File

@ -1,29 +0,0 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

75
arch/arm/cpu/armv7/uniphier/ph1-pro4/sbc_init.c
View File

@ -1,75 +0,0 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
void sbc_init(void)
{
#if defined(CONFIG_PFC_MICRO_SUPPORT_CARD)
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x3effffff: memory bank (31MB)
* 0x03f00000-0x3fffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
#elif defined(CONFIG_DCC_MICRO_SUPPORT_CARD)
#if !defined(CONFIG_SPL_BUILD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS1: sub/boot memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL32);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL34);
writel(0x0000bc01, SBBASE0); /* boot memory */
writel(0x0400bc01, SBBASE1); /* sub memory */
writel(0x0800bf01, SBBASE3); /* peripherals */
#if !defined(CONFIG_SPL_BUILD)
sg_set_pinsel(318, 5); /* PORT22 -> XECS0 */
#endif
sg_set_pinsel(313, 5); /* PORT15 -> XECS3 */
writel(0x00000001, SG_LOADPINCTRL);
#endif /* CONFIG_XXX_MICRO_SUPPORT_CARD */
}

28
arch/arm/cpu/armv7/uniphier/ph1-pro4/sg_init.c
View File

@ -1,28 +0,0 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 1 << 6;
writel(tmp, SG_IECTRL);
}

1
arch/arm/cpu/armv8/Makefile
View File

@ -16,3 +16,4 @@ obj-y += tlb.o
obj-y += transition.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/

9
arch/arm/cpu/armv8/zynqmp/Makefile Normal file
View File

@ -0,0 +1,9 @@
#
# (C) Copyright 2014 - 2015 Xilinx, Inc.
# Michal Simek <michal.simek@xilinx.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += clk.o
obj-y += cpu.o

49
arch/arm/cpu/armv8/zynqmp/clk.c Normal file
View File

@ -0,0 +1,49 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long get_uart_clk(int dev_id)
{
u32 ver = zynqmp_get_silicon_version();
switch (ver) {
case ZYNQMP_CSU_VERSION_EP108:
return 25000000;
}
return 133000000;
}
#ifdef CONFIG_CLOCKS
/**
* set_cpu_clk_info() - Initialize clock framework
* Always returns zero.
*
* This function is called from common code after relocation and sets up the
* clock framework. The framework must not be used before this function had been
* called.
*/
int set_cpu_clk_info(void)
{
gd->cpu_clk = get_tbclk();
/* Support Veloce to show at least 1MHz via bdi */
if (gd->cpu_clk > 1000000)
gd->bd->bi_arm_freq = gd->cpu_clk / 1000000;
else
gd->bd->bi_arm_freq = 1;
gd->bd->bi_dsp_freq = 0;
return 0;
}
#endif

28
arch/arm/cpu/armv8/zynqmp/cpu.c Normal file
View File

@ -0,0 +1,28 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#define ZYNQ_SILICON_VER_MASK 0xF000
#define ZYNQ_SILICON_VER_SHIFT 12
DECLARE_GLOBAL_DATA_PTR;
unsigned int zynqmp_get_silicon_version(void)
{
gd->cpu_clk = get_tbclk();
switch (gd->cpu_clk) {
case 50000000:
return ZYNQMP_CSU_VERSION_QEMU;
}
return ZYNQMP_CSU_VERSION_EP108;
}

8
arch/arm/dts/uniphier-ph1-ld4.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-LD4 SoC
*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -94,19 +94,19 @@
};
usb0: usb@5a800100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};

5
arch/arm/dts/uniphier-ph1-pro4-ref.dts
View File

@ -36,6 +36,7 @@
i2c3 = &i2c3;
i2c5 = &i2c5;
i2c6 = &i2c6;
usb0 = &usb0;
};
};
@ -54,7 +55,3 @@
&usb0 {
status = "okay";
};
&usb1 {
status = "okay";
};

22
arch/arm/dts/uniphier-ph1-pro4.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-Pro4 SoC
*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -119,18 +119,30 @@
status = "ok";
};
usb0: usb@5a800100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
usb2: usb@5a800100 {
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
usb3: usb@5a810100 {
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb0: usb@65a00000 {
compatible = "panasonic,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65a00000 0x100>;
};
usb1: usb@65c00000 {
compatible = "panasonic,uniphier-xhci", "generic-xhci";
status = "disabled";
reg = <0x65c00000 0x100>;
};
nand: nand@68000000 {
compatible = "denali,denali-nand-dt";
reg = <0x68000000 0x20>, <0x68100000 0x1000>;

10
arch/arm/dts/uniphier-ph1-sld3.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-sLD3 SoC
*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -93,25 +93,25 @@
};
usb0: usb@5a800100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};
usb3: usb@5a830100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a830100 0x100>;
};

8
arch/arm/dts/uniphier-ph1-sld8.dtsi
View File

@ -1,7 +1,7 @@
/*
* Device Tree Source for UniPhier PH1-sLD8 SoC
*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -94,19 +94,19 @@
};
usb0: usb@5a800100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
};
usb1: usb@5a810100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
};
usb2: usb@5a820100 {
compatible = "panasonic,uniphier-ehci", "usb-ehci";
compatible = "panasonic,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
};

5
arch/arm/include/asm/arch-exynos/cpu.h
View File

@ -153,6 +153,10 @@
#define EXYNOS5420_CLOCK_BASE 0x10010000
#define EXYNOS5420_POWER_BASE 0x10040000
#define EXYNOS5420_SWRESET 0x10040400
#define EXYNOS5420_INFORM_BASE 0x10040800
#define EXYNOS5420_SPARE_BASE 0x10040900
#define EXYNOS5420_CPU_CONFIG_BASE 0x10042000
#define EXYNOS5420_CPU_STATUS_BASE 0x10042004
#define EXYNOS5420_SYSREG_BASE 0x10050000
#define EXYNOS5420_TZPC_BASE 0x100E0000
#define EXYNOS5420_WATCHDOG_BASE 0x101D0000
@ -186,6 +190,7 @@
#define EXYNOS5420_USB3PHY_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5420_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
#ifndef __ASSEMBLY__
#include <asm/io.h>
/* CPU detection macros */

88
arch/arm/include/asm/arch-exynos/system.h
View File

@ -37,6 +37,94 @@ struct exynos5_sysreg {
#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
/*
* Data Synchronization Barrier acts as a special kind of memory barrier.
* No instruction in program order after this instruction executes until
* this instruction completes. This instruction completes when:
* - All explicit memory accesses before this instruction complete.
* - All Cache, Branch predictor and TLB maintenance operations before
* this instruction complete.
*/
#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
/*
* This instruction causes an event to be signaled to all cores
* within a multiprocessor system. If SEV is implemented,
* WFE must also be implemented.
*/
#define sev() __asm__ __volatile__ ("sev\n\t" : : );
/*
* If the Event Register is not set, WFE suspends execution until
* one of the following events occurs:
* - an IRQ interrupt, unless masked by the CPSR I-bit
* - an FIQ interrupt, unless masked by the CPSR F-bit
* - an Imprecise Data abort, unless masked by the CPSR A-bit
* - a Debug Entry request, if Debug is enabled
* - an Event signaled by another processor using the SEV instruction.
* If the Event Register is set, WFE clears it and returns immediately.
* If WFE is implemented, SEV must also be implemented.
*/
#define wfe() __asm__ __volatile__ ("wfe\n\t" : : );
/* Move 0xd3 value to CPSR register to enable SVC mode */
#define svc32_mode_en() __asm__ __volatile__ \
("@ I&F disable, Mode: 0x13 - SVC\n\t" \
"msr cpsr_c, #0x13|0xC0\n\t" : : )
/* Set program counter with the given value */
#define set_pc(x) __asm__ __volatile__ ("mov pc, %0\n\t" : : "r"(x))
/* Branch to the given location */
#define branch_bx(x) __asm__ __volatile__ ("bx %0\n\t" : : "r"(x))
/* Read Main Id register */
#define mrc_midr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c0, c0, 0\n\t" : "=r"(x) : )
/* Read Multiprocessor Affinity Register */
#define mrc_mpafr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c0, c0, 5\n\t" : "=r"(x) : )
/* Read System Control Register */
#define mrc_sctlr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c1, c0, 0\n\t" : "=r"(x) : )
/* Read Auxiliary Control Register */
#define mrc_auxr(x) __asm__ __volatile__ \
("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(x) : )
/* Read L2 Control register */
#define mrc_l2_ctlr(x) __asm__ __volatile__ \
("mrc p15, 1, %0, c9, c0, 2\n\t" : "=r"(x) : )
/* Read L2 Auxilliary Control register */
#define mrc_l2_aux_ctlr(x) __asm__ __volatile__ \
("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(x) : )
/* Write System Control Register */
#define mcr_sctlr(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c1, c0, 0\n\t" : : "r"(x))
/* Write Auxiliary Control Register */
#define mcr_auxr(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(x))
/* Invalidate all instruction caches to PoU */
#define mcr_icache(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c7, c5, 0\n\t" : : "r"(x))
/* Invalidate unified TLB */
#define mcr_tlb(x) __asm__ __volatile__ \
("mcr p15, 0, %0, c8, c7, 0\n\t" : : "r"(x))
/* Write L2 Control register */
#define mcr_l2_ctlr(x) __asm__ __volatile__ \
("mcr p15, 1, %0, c9, c0, 2\n\t" : : "r"(x))
/* Write L2 Auxilliary Control register */
#define mcr_l2_aux_ctlr(x) __asm__ __volatile__ \
("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(x))
void set_usbhost_mode(unsigned int mode);
void set_system_display_ctrl(void);
int exynos_lcd_early_init(const void *blob);

114
arch/arm/include/asm/arch-rmobile/r8a7794-gpio.h
View File

@ -74,8 +74,23 @@ enum {
GPIO_FN_SD1_CLK, GPIO_FN_SD1_CMD, GPIO_FN_SD1_DATA0,
GPIO_FN_SD1_DATA1, GPIO_FN_SD1_DATA2, GPIO_FN_SD1_DATA3,
/* IPSR0 */
GPIO_FN_SD1_CD, GPIO_FN_CAN0_RX, GPIO_FN_SD1_WP, GPIO_FN_IRQ7,
GPIO_FN_CAN0_TX, GPIO_FN_MMC_CLK, GPIO_FN_SD2_CLK, GPIO_FN_MMC_CMD,
GPIO_FN_SD2_CMD, GPIO_FN_MMC_D0, GPIO_FN_SD2_DATA0, GPIO_FN_MMC_D1,
GPIO_FN_SD2_DATA1, GPIO_FN_MMC_D2, GPIO_FN_SD2_DATA2,
GPIO_FN_MMC_D3, GPIO_FN_SD2_DATA3, GPIO_FN_MMC_D4,
GPIO_FN_SD2_CD, GPIO_FN_MMC_D5, GPIO_FN_SD2_WP, GPIO_FN_MMC_D6,
GPIO_FN_SCIF0_RXD, GPIO_FN_I2C2_SCL_B, GPIO_FN_CAN1_RX, GPIO_FN_MMC_D7,
GPIO_FN_SCIF0_TXD, GPIO_FN_I2C2_SDA_B, GPIO_FN_CAN1_TX, GPIO_FN_D0,
GPIO_FN_SCIFA3_SCK_B, GPIO_FN_IRQ4, GPIO_FN_D1, GPIO_FN_SCIFA3_RXD_B,
GPIO_FN_D2, GPIO_FN_SCIFA3_TXD_B, GPIO_FN_D3, GPIO_FN_I2C3_SCL_B,
GPIO_FN_SCIF5_RXD_B, GPIO_FN_D4, GPIO_FN_I2C3_SDA_B,
GPIO_FN_SCIF5_TXD_B, GPIO_FN_D5, GPIO_FN_SCIF4_RXD_B,
GPIO_FN_I2C0_SCL_D,
/*
* From IPSR0 to IPSR5 have been removed because they does not use.
* From IPSR1 to IPSR5 have been removed because they does not use.
*/
/* IPSR6 */
@ -144,9 +159,54 @@ enum {
GPIO_FN_SCIF5_RXD, GPIO_FN_I2C2_SCL_C, GPIO_FN_DU1_DR2,
GPIO_FN_RIF1_D0_B, GPIO_FN_TS_SDEN_D, GPIO_FN_FMCLK_C, GPIO_FN_RDS_CLK,
/*
* From IPSR9 to IPSR10 have been removed because they does not use.
*/
/* IPSR9 */
GPIO_FN_MSIOF0_TXD, GPIO_FN_SCIF5_TXD, GPIO_FN_I2C2_SDA_C,
GPIO_FN_DU1_DR3, GPIO_FN_RIF1_D1_B, GPIO_FN_TS_SPSYNC_D, GPIO_FN_FMIN_C,
GPIO_FN_RDS_DATA, GPIO_FN_MSIOF0_SCK, GPIO_FN_IRQ0, GPIO_FN_TS_SDATA,
GPIO_FN_DU1_DR4, GPIO_FN_RIF1_SYNC, GPIO_FN_TPUTO1_C,
GPIO_FN_MSIOF0_SYNC, GPIO_FN_PWM1, GPIO_FN_TS_SCK, GPIO_FN_DU1_DR5,
GPIO_FN_RIF1_CLK, GPIO_FN_BPFCLK_B, GPIO_FN_MSIOF0_SS1,
GPIO_FN_SCIFA0_RXD, GPIO_FN_TS_SDEN, GPIO_FN_DU1_DR6, GPIO_FN_RIF1_D0,
GPIO_FN_FMCLK_B, GPIO_FN_RDS_CLK_B, GPIO_FN_MSIOF0_SS2,
GPIO_FN_SCIFA0_TXD, GPIO_FN_TS_SPSYNC, GPIO_FN_DU1_DR7, GPIO_FN_RIF1_D1,
GPIO_FN_FMIN_B, GPIO_FN_RDS_DATA_B, GPIO_FN_HSCIF1_HRX,
GPIO_FN_I2C4_SCL, GPIO_FN_PWM6, GPIO_FN_DU1_DG0, GPIO_FN_HSCIF1_HTX,
GPIO_FN_I2C4_SDA, GPIO_FN_TPUTO1, GPIO_FN_DU1_DG1, GPIO_FN_HSCIF1_HSCK,
GPIO_FN_PWM2, GPIO_FN_IETX, GPIO_FN_DU1_DG2, GPIO_FN_REMOCON_B,
GPIO_FN_SPEEDIN_B, GPIO_FN_VSP_B, GPIO_FN_HSCIF1_HCTS_N,
GPIO_FN_SCIFA4_RXD, GPIO_FN_IECLK, GPIO_FN_DU1_DG3, GPIO_FN_SSI_SCK1_B,
GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_CC50_STATE32,
GPIO_FN_HSCIF1_HRTS_N, GPIO_FN_SCIFA4_TXD, GPIO_FN_IERX,
GPIO_FN_DU1_DG4, GPIO_FN_SSI_WS1_B, GPIO_FN_CAN_STEP0,
GPIO_FN_CC50_STATE33, GPIO_FN_SCIF1_SCK, GPIO_FN_PWM3, GPIO_FN_TCLK2,
GPIO_FN_DU1_DG5, GPIO_FN_SSI_SDATA1_B, GPIO_FN_CAN_TXCLK,
GPIO_FN_CC50_STATE34,
/* IPSR10 */
GPIO_FN_SCIF1_RXD, GPIO_FN_IIC0_SCL, GPIO_FN_DU1_DG6,
GPIO_FN_SSI_SCK2_B, GPIO_FN_CAN_DEBUGOUT0, GPIO_FN_CC50_STATE35,
GPIO_FN_SCIF1_TXD, GPIO_FN_IIC0_SDA, GPIO_FN_DU1_DG7, GPIO_FN_SSI_WS2_B,
GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_CC50_STATE36, GPIO_FN_SCIF2_RXD,
GPIO_FN_IIC1_SCL, GPIO_FN_DU1_DB0, GPIO_FN_SSI_SDATA2_B,
GPIO_FN_USB0_EXTLP, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_CC50_STATE37,
GPIO_FN_SCIF2_TXD, GPIO_FN_IIC1_SDA, GPIO_FN_DU1_DB1,
GPIO_FN_SSI_SCK9_B, GPIO_FN_USB0_OVC1, GPIO_FN_CAN_DEBUGOUT3,
GPIO_FN_CC50_STATE38, GPIO_FN_SCIF2_SCK, GPIO_FN_IRQ1, GPIO_FN_DU1_DB2,
GPIO_FN_SSI_WS9_B, GPIO_FN_USB0_IDIN, GPIO_FN_CAN_DEBUGOUT4,
GPIO_FN_CC50_STATE39, GPIO_FN_SCIF3_SCK, GPIO_FN_IRQ2, GPIO_FN_BPFCLK_D,
GPIO_FN_DU1_DB3, GPIO_FN_SSI_SDATA9_B, GPIO_FN_TANS2,
GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_CC50_OSCOUT, GPIO_FN_SCIF3_RXD,
GPIO_FN_I2C1_SCL_E, GPIO_FN_FMCLK_D, GPIO_FN_DU1_DB4,
GPIO_FN_AUDIO_CLKA_C, GPIO_FN_SSI_SCK4_B, GPIO_FN_CAN_DEBUGOUT6,
GPIO_FN_RDS_CLK_C, GPIO_FN_SCIF3_TXD, GPIO_FN_I2C1_SDA_E,
GPIO_FN_FMIN_D, GPIO_FN_DU1_DB5, GPIO_FN_AUDIO_CLKB_C,
GPIO_FN_SSI_WS4_B, GPIO_FN_CAN_DEBUGOUT7, GPIO_FN_RDS_DATA_C,
GPIO_FN_I2C2_SCL, GPIO_FN_SCIFA5_RXD, GPIO_FN_DU1_DB6,
GPIO_FN_AUDIO_CLKC_C, GPIO_FN_SSI_SDATA4_B, GPIO_FN_CAN_DEBUGOUT8,
GPIO_FN_I2C2_SDA, GPIO_FN_SCIFA5_TXD, GPIO_FN_DU1_DB7,
GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SCK5,
GPIO_FN_SCIFA3_SCK, GPIO_FN_CAN_DEBUGOUT10,
GPIO_FN_DU1_DOTCLKIN,
/* IPSR11 */
GPIO_FN_SSI_WS5, GPIO_FN_SCIFA3_RXD, GPIO_FN_I2C3_SCL_C,
@ -168,9 +228,49 @@ enum {
GPIO_FN_AD_DO_B, GPIO_FN_SSI_SDATA0, GPIO_FN_MSIOF1_SCK_B,
GPIO_FN_PWM0_B, GPIO_FN_ADICLK_B, GPIO_FN_AD_CLK_B,
/*
* From IPSR12 to IPSR13 have been removed because they does not use.
*/
/* IPSR12 */
GPIO_FN_SSI_SCK34, GPIO_FN_MSIOF1_SYNC_B, GPIO_FN_SCIFA1_SCK_C,
GPIO_FN_ADICHS0_B, GPIO_FN_AD_NCS_N_B, GPIO_FN_DREQ1_N_B,
GPIO_FN_SSI_WS34, GPIO_FN_MSIOF1_SS1_B, GPIO_FN_SCIFA1_RXD_C,
GPIO_FN_ADICHS1_B, GPIO_FN_CAN1_RX_C, GPIO_FN_DACK1_B,
GPIO_FN_SSI_SDATA3, GPIO_FN_MSIOF1_SS2_B, GPIO_FN_SCIFA1_TXD_C,
GPIO_FN_ADICHS2_B, GPIO_FN_CAN1_TX_C, GPIO_FN_DREQ2_N, GPIO_FN_SSI_SCK4,
GPIO_FN_MLB_CK, GPIO_FN_IETX_B, GPIO_FN_IRD_TX, GPIO_FN_SSI_WS4,
GPIO_FN_MLB_SIG, GPIO_FN_IECLK_B, GPIO_FN_IRD_RX, GPIO_FN_SSI_SDATA4,
GPIO_FN_MLB_DAT, GPIO_FN_IERX_B, GPIO_FN_IRD_SCK, GPIO_FN_SSI_SDATA8,
GPIO_FN_SCIF1_SCK_B, GPIO_FN_PWM1_B, GPIO_FN_IRQ9, GPIO_FN_REMOCON,
GPIO_FN_DACK2, GPIO_FN_ETH_MDIO_B, GPIO_FN_SSI_SCK1,
GPIO_FN_SCIF1_RXD_B, GPIO_FN_IIC1_SCL_C, GPIO_FN_VI1_CLK,
GPIO_FN_CAN0_RX_D, GPIO_FN_AVB_AVTP_CAPTURE, GPIO_FN_ETH_CRS_DV_B,
GPIO_FN_SSI_WS1, GPIO_FN_SCIF1_TXD_B, GPIO_FN_IIC1_SDA_C,
GPIO_FN_VI1_DATA0, GPIO_FN_CAN0_TX_D, GPIO_FN_AVB_AVTP_MATCH,
GPIO_FN_ETH_RX_ER_B, GPIO_FN_SSI_SDATA1, GPIO_FN_HSCIF1_HRX_B,
GPIO_FN_VI1_DATA1, GPIO_FN_SDATA, GPIO_FN_ATAG0_N, GPIO_FN_ETH_RXD0_B,
GPIO_FN_SSI_SCK2, GPIO_FN_HSCIF1_HTX_B, GPIO_FN_VI1_DATA2,
GPIO_FN_MDATA, GPIO_FN_ATAWR0_N, GPIO_FN_ETH_RXD1_B,
/* IPSR13 */
GPIO_FN_SSI_WS2, GPIO_FN_HSCIF1_HCTS_N_B, GPIO_FN_SCIFA0_RXD_D,
GPIO_FN_VI1_DATA3, GPIO_FN_SCKZ, GPIO_FN_ATACS00_N, GPIO_FN_ETH_LINK_B,
GPIO_FN_SSI_SDATA2, GPIO_FN_HSCIF1_HRTS_N_B, GPIO_FN_SCIFA0_TXD_D,
GPIO_FN_VI1_DATA4, GPIO_FN_STM_N, GPIO_FN_ATACS10_N,
GPIO_FN_ETH_REFCLK_B, GPIO_FN_SSI_SCK9, GPIO_FN_SCIF2_SCK_B,
GPIO_FN_PWM2_B, GPIO_FN_VI1_DATA5, GPIO_FN_MTS_N, GPIO_FN_EX_WAIT1,
GPIO_FN_ETH_TXD1_B, GPIO_FN_SSI_WS9, GPIO_FN_SCIF2_RXD_B,
GPIO_FN_I2C3_SCL_E, GPIO_FN_VI1_DATA6, GPIO_FN_ATARD0_N,
GPIO_FN_ETH_TX_EN_B, GPIO_FN_SSI_SDATA9, GPIO_FN_SCIF2_TXD_B,
GPIO_FN_I2C3_SDA_E, GPIO_FN_VI1_DATA7, GPIO_FN_ATADIR0_N,
GPIO_FN_ETH_MAGIC_B, GPIO_FN_AUDIO_CLKA, GPIO_FN_I2C0_SCL_B,
GPIO_FN_SCIFA4_RXD_D, GPIO_FN_VI1_CLKENB, GPIO_FN_TS_SDATA_C,
GPIO_FN_RIF0_SYNC_B, GPIO_FN_ETH_TXD0_B, GPIO_FN_AUDIO_CLKB,
GPIO_FN_I2C0_SDA_B, GPIO_FN_SCIFA4_TXD_D, GPIO_FN_VI1_FIELD,
GPIO_FN_TS_SCK_C, GPIO_FN_RIF0_CLK_B, GPIO_FN_BPFCLK_E,
GPIO_FN_ETH_MDC_B, GPIO_FN_AUDIO_CLKC, GPIO_FN_I2C4_SCL_B,
GPIO_FN_SCIFA5_RXD_D, GPIO_FN_VI1_HSYNC_N, GPIO_FN_TS_SDEN_C,
GPIO_FN_RIF0_D0_B, GPIO_FN_FMCLK_E, GPIO_FN_RDS_CLK_D,
GPIO_FN_AUDIO_CLKOUT, GPIO_FN_I2C4_SDA_B, GPIO_FN_SCIFA5_TXD_D,
GPIO_FN_VI1_VSYNC_N, GPIO_FN_TS_SPSYNC_C, GPIO_FN_RIF0_D1_B,
GPIO_FN_FMIN_E, GPIO_FN_RDS_DATA_D,
};
#endif /* __ASM_R8A7794_H__ */

33
arch/arm/include/asm/arch-uniphier/ehci-uniphier.h
View File

@ -1,33 +0,0 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __PLAT_UNIPHIER_EHCI_H
#define __PLAT_UNIPHIER_EHCI_H
#include <linux/types.h>
#include <asm/io.h>
#include "mio-regs.h"
struct uniphier_ehci_platform_data {
unsigned long base;
};
extern struct uniphier_ehci_platform_data uniphier_ehci_platdata[];
static inline void uniphier_ehci_reset(int index, int on)
{
u32 tmp;
tmp = readl(MIO_USB_RSTCTRL(index));
if (on)
tmp &= ~MIO_USB_RSTCTRL_XRST;
else
tmp |= MIO_USB_RSTCTRL_XRST;
writel(tmp, MIO_USB_RSTCTRL(index));
}
#endif /* __PLAT_UNIPHIER_EHCI_H */

13
arch/arm/include/asm/arch-zynqmp/clk.h Normal file
View File

@ -0,0 +1,13 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_CLK_H_
#define _ASM_ARCH_CLK_H_
unsigned long get_uart_clk(int dev_id);
#endif /* _ASM_ARCH_CLK_H_ */

52
arch/arm/include/asm/arch-zynqmp/hardware.h Normal file
View File

@ -0,0 +1,52 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_HARDWARE_H
#define _ASM_ARCH_HARDWARE_H
#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
struct crlapb_regs {
u32 reserved0[74];
u32 timestamp_ref_ctrl; /* 0x128 */
u32 reserved0_1[53];
u32 boot_mode; /* 0x200 */
u32 reserved1[26];
};
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
#define ZYNQMP_IOU_SCNTR 0xFF250000
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
struct iou_scntr {
u32 counter_control_register;
u32 reserved0[7];
u32 base_frequency_id_register;
};
#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
/* Bootmode setting values */
#define BOOT_MODES_MASK 0x0000000F
#define SD_MODE 0x00000005
#define JTAG_MODE 0x00000000
/* Board version value */
#define ZYNQMP_CSU_VERSION_SILICON 0x0
#define ZYNQMP_CSU_VERSION_EP108 0x1
#define ZYNQMP_CSU_VERSION_QEMU 0x3
#endif /* _ASM_ARCH_HARDWARE_H */

15
arch/arm/include/asm/arch-zynqmp/sys_proto.h Normal file
View File

@ -0,0 +1,15 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
int zynq_sdhci_init(unsigned long regbase);
unsigned int zynqmp_get_silicon_version(void);
#endif /* _ASM_ARCH_SYS_PROTO_H */

45
arch/arm/include/asm/armv7.h
View File

@ -58,6 +58,7 @@
#ifndef __ASSEMBLY__
#include <linux/types.h>
#include <asm/io.h>
/*
* CP15 Barrier instructions
@ -69,6 +70,50 @@
#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
/*
* Workaround for ARM errata # 798870
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
* stalled for 1024 cycles to verify that its hazard condition still exists.
*/
static inline void v7_enable_l2_hazard_detect(void)
{
uint32_t val;
/* L2ACTLR[7]: Enable hazard detect timeout */
asm volatile ("mrc p15, 1, %0, c15, c0, 0\n\t" : "=r"(val));
val |= (1 << 7);
asm volatile ("mcr p15, 1, %0, c15, c0, 0\n\t" : : "r"(val));
}
/*
* Workaround for ARM errata # 799270
* Ensure that the L2 logic has been used within the previous 256 cycles
* before modifying the ACTLR.SMP bit. This is required during boot before
* MMU has been enabled, or during a specified reset or power down sequence.
*/
static inline void v7_enable_smp(uint32_t address)
{
uint32_t temp, val;
/* Read auxiliary control register */
asm volatile ("mrc p15, 0, %0, c1, c0, 1\n\t" : "=r"(val));
/* Enable SMP */
val |= (1 << 6);
/* Dummy read to assure L2 access */
temp = readl(address);
temp &= 0;
val |= temp;
/* Write auxiliary control register */
asm volatile ("mcr p15, 0, %0, c1, c0, 1\n\t" : : "r"(val));
CP15DSB;
CP15ISB;
}
void v7_en_l2_hazard_detect(void);
void v7_outer_cache_enable(void);
void v7_outer_cache_disable(void);
void v7_outer_cache_flush_all(void);

2
arch/arm/include/asm/spl.h
View File

@ -37,6 +37,8 @@ void spl_board_load_image(void);
/* Linker symbols. */
extern char __bss_start[], __bss_end[];
#ifndef CONFIG_DM
extern gd_t gdata;
#endif
#endif

13
arch/arm/lib/crt0.S
View File

@ -113,7 +113,14 @@ here:
/* Set up final (full) environment */
bl c_runtime_cpu_setup /* we still call old routine here */
#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
# ifdef CONFIG_SPL_BUILD
/* Use a DRAM stack for the rest of SPL, if requested */
bl spl_relocate_stack_gd
cmp r0, #0
movne sp, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
ldr r1, =__bss_end /* this is auto-relocated! */
@ -124,9 +131,10 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */
addlo r0, r0, #4 /* move to next */
blo clbss_l
#if ! defined(CONFIG_SPL_BUILD)
bl coloured_LED_init
bl red_led_on
#endif
/* call board_init_r(gd_t *id, ulong dest_addr) */
mov r0, r9 /* gd_t */
ldr r1, [r9, #GD_RELOCADDR] /* dest_addr */
@ -134,7 +142,6 @@ clbss_l:cmp r0, r1 /* while not at end of BSS */
ldr pc, =board_init_r /* this is auto-relocated! */
/* we should not return here. */
#endif
ENDPROC(_main)

4
arch/arm/lib/spl.c
View File

@ -13,6 +13,7 @@
#include <image.h>
#include <linux/compiler.h>
#ifndef CONFIG_DM
/* Pointer to as well as the global data structure for SPL */
DECLARE_GLOBAL_DATA_PTR;
@ -21,6 +22,7 @@ DECLARE_GLOBAL_DATA_PTR;
* pafches that rely on it. The global_data area is set up in crt0.S.
*/
gd_t gdata __attribute__ ((section(".data")));
#endif
/*
* In the context of SPL, board_init_f must ensure that any clocks/etc for
@ -33,8 +35,10 @@ void __weak board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
#ifndef CONFIG_DM
/* TODO: Remove settings of the global data pointer here */
gd = &gdata;
#endif
board_init_r(NULL, 0);
}

3
arch/arm/mach-tegra/Kconfig
View File

@ -29,6 +29,9 @@ config USE_PRIVATE_LIBGCC
config DM
default y
config SPL_DM
default y
config DM_SERIAL
default y

0
arch/arm/cpu/armv7/uniphier/Kconfig → arch/arm/mach-uniphier/Kconfig
View File

1
arch/arm/cpu/armv7/uniphier/Makefile → arch/arm/mach-uniphier/Makefile
View File

@ -7,6 +7,7 @@ ifdef CONFIG_SPL_BUILD
obj-y += lowlevel_init.o
obj-y += init_page_table.o
obj-y += spl.o
obj-y += memconf.o
obj-y += ddrphy_training.o
else

2
arch/arm/cpu/armv7/uniphier/board_common.c → arch/arm/mach-uniphier/board_common.c
View File

@ -6,7 +6,7 @@
*/
#include <common.h>
#include <asm/arch/led.h>
#include <mach/led.h>
/*
* Routine: board_init

9
arch/arm/cpu/armv7/uniphier/board_early_init_f.c → arch/arm/mach-uniphier/board_early_init_f.c
View File

@ -5,10 +5,11 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/led.h>
#include <asm/arch/board.h>
#include <mach/led.h>
#include <mach/board.h>
void pin_init(void);
void clkrst_init(void);
int board_early_init_f(void)
{
@ -18,5 +19,9 @@ int board_early_init_f(void)
led_write(U, 1, , );
clkrst_init();
led_write(U, 2, , );
return 0;
}

2
arch/arm/cpu/armv7/uniphier/board_early_init_r.c → arch/arm/mach-uniphier/board_early_init_r.c
View File

@ -6,7 +6,7 @@
*/
#include <common.h>
#include <asm/arch/board.h>
#include <mach/board.h>
int board_early_init_r(void)
{

0
arch/arm/cpu/armv7/uniphier/board_late_init.c → arch/arm/mach-uniphier/board_late_init.c
View File

2
arch/arm/cpu/armv7/uniphier/cache_uniphier.c → arch/arm/mach-uniphier/cache_uniphier.c
View File

@ -8,7 +8,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/armv7.h>
#include <asm/arch/ssc-regs.h>
#include <mach/ssc-regs.h>
#ifdef CONFIG_UNIPHIER_L2CACHE_ON
static void uniphier_cache_maint_all(u32 operation)

2
arch/arm/cpu/armv7/uniphier/cmd_ddrphy.c → arch/arm/mach-uniphier/cmd_ddrphy.c
View File

@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/ddrphy-regs.h>
#include <mach/ddrphy-regs.h>
/* Select either decimal or hexadecimal */
#if 1

4
arch/arm/cpu/armv7/uniphier/cmd_pinmon.c → arch/arm/mach-uniphier/cmd_pinmon.c
View File

@ -6,8 +6,8 @@
*/
#include <common.h>
#include <asm/arch/boot-device.h>
#include <asm/arch/sbc-regs.h>
#include <mach/boot-device.h>
#include <mach/sbc-regs.h>
static int do_pinmon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{

2
arch/arm/cpu/armv7/uniphier/cpu_info.c → arch/arm/mach-uniphier/cpu_info.c
View File

@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
#include <mach/sg-regs.h>
int print_cpuinfo(void)
{

2
arch/arm/cpu/armv7/uniphier/ddrphy_training.c → arch/arm/mach-uniphier/ddrphy_training.c
View File

@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/ddrphy-regs.h>
#include <mach/ddrphy-regs.h>
void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank)
{

0
arch/arm/cpu/armv7/uniphier/dram_init.c → arch/arm/mach-uniphier/dram_init.c
View File

0
arch/arm/include/asm/arch-uniphier/arm-mpcore.h → arch/arm/mach-uniphier/include/mach/arm-mpcore.h
View File

0
arch/arm/include/asm/arch-uniphier/bcu-regs.h → arch/arm/mach-uniphier/include/mach/bcu-regs.h
View File

0
arch/arm/include/asm/arch-uniphier/board.h → arch/arm/mach-uniphier/include/mach/board.h
View File

0
arch/arm/include/asm/arch-uniphier/boot-device.h → arch/arm/mach-uniphier/include/mach/boot-device.h
View File

0
arch/arm/include/asm/arch-uniphier/ddrphy-regs.h → arch/arm/mach-uniphier/include/mach/ddrphy-regs.h
View File

0
arch/arm/include/asm/arch-uniphier/debug-uart.S → arch/arm/mach-uniphier/include/mach/debug-uart.S
View File

0
arch/arm/include/asm/arch-uniphier/led.h → arch/arm/mach-uniphier/include/mach/led.h
View File

0
arch/arm/include/asm/arch-uniphier/mio-regs.h → arch/arm/mach-uniphier/include/mach/mio-regs.h
View File

2
arch/arm/include/asm/arch-uniphier/platdevice.h → arch/arm/mach-uniphier/include/mach/platdevice.h
View File

@ -21,6 +21,4 @@ U_BOOT_DEVICE(serial##n) = { \
.platdata = &serial_device##n \
};
#include <asm/arch/ehci-uniphier.h>
#endif /* ARCH_PLATDEVICE_H */

0
arch/arm/include/asm/arch-uniphier/sbc-regs.h → arch/arm/mach-uniphier/include/mach/sbc-regs.h
View File

29
arch/arm/include/asm/arch-uniphier/sc-regs.h → arch/arm/mach-uniphier/include/mach/sc-regs.h
View File

@ -1,7 +1,7 @@
/*
* UniPhier SC (System Control) block registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -11,10 +11,6 @@
#define SC_BASE_ADDR 0x61840000
#define SC_MPLLOSCCTL (SC_BASE_ADDR | 0x1184)
#define SC_MPLLOSCCTL_MPLLEN (0x1 << 0)
#define SC_MPLLOSCCTL_MPLLST (0x1 << 1)
#define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200)
#define SC_DPLLCTRL_SSC_EN (0x1 << 31)
#define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16)
@ -38,21 +34,32 @@
#define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298)
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
#define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */
#define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */
#define SC_RSTCTRL_NRST_ETHER (0x1 << 12)
#define SC_RSTCTRL_NRST_STDMAC (0x1 << 10)
#define SC_RSTCTRL_NRST_GIO (0x1 << 6)
#define SC_RSTCTRL_NRST_UMC1 (0x1 << 5)
#define SC_RSTCTRL_NRST_UMC0 (0x1 << 4)
#define SC_RSTCTRL_NRST_NAND (0x1 << 2)
#define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004)
#define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */
#define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2104)
#define SC_CLKCTRL_CLK_ETHER (0x1 << 12)
#define SC_CLKCTRL_CLK_MIO (0x1 << 11)
#define SC_CLKCTRL_CLK_UMC (0x1 << 4)
#define SC_CLKCTRL_CLK_NAND (0x1 << 2)
#define SC_CLKCTRL_CLK_SBC (0x1 << 1)
#define SC_CLKCTRL_CLK_PERI (0x1 << 0)
#define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */
#define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */
#define SC_CLKCTRL_CEN_ETHER (0x1 << 12)
#define SC_CLKCTRL_CEN_MIO (0x1 << 11)
#define SC_CLKCTRL_CEN_STDMAC (0x1 << 10)
#define SC_CLKCTRL_CEN_GIO (0x1 << 6)
#define SC_CLKCTRL_CEN_UMC (0x1 << 4)
#define SC_CLKCTRL_CEN_NAND (0x1 << 2)
#define SC_CLKCTRL_CEN_SBC (0x1 << 1)
#define SC_CLKCTRL_CEN_PERI (0x1 << 0)
/* System reset control register */
#define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000)

119
arch/arm/include/asm/arch-uniphier/sg-regs.h → arch/arm/mach-uniphier/include/mach/sg-regs.h
View File

@ -1,7 +1,7 @@
/*
* UniPhier SG (SoC Glue) block registers
*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -108,7 +108,6 @@
#else
#include <linux/types.h>
#include <linux/sizes.h>
#include <asm/io.h>
static inline void sg_set_pinsel(int n, int value)
@ -117,122 +116,6 @@ static inline void sg_set_pinsel(int n, int value)
| SG_PINSEL_MODE(n, value), SG_PINSEL_ADDR(n));
}
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH0_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH0_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH0_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH0_SZ_512M;
break;
case SZ_1G:
ret = SG_MEMCONF_CH0_SZ_1G;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH0_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH0_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH1_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH1_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH1_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH1_SZ_512M;
break;
case SZ_1G:
ret = SG_MEMCONF_CH1_SZ_1G;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH1_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH1_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
static inline u32 sg_memconf_val_ch2(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH2_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH2_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH2_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH2_SZ_512M;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH2_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH2_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
#endif /* __ASSEMBLY__ */
#endif /* ARCH_SG_REGS_H */

2
arch/arm/include/asm/arch-uniphier/ssc-regs.h → arch/arm/mach-uniphier/include/mach/ssc-regs.h
View File

@ -60,8 +60,6 @@
#define SSCOQCE0 0x506c0270
#define SSC_LINE_SIZE 128
#define SSC_NUM_ENTRIES 256
#define SSC_WAY_SIZE ((SSC_LINE_SIZE) * (SSC_NUM_ENTRIES))
#define SSC_RANGE_OP_MAX_SIZE (0x00400000 - (SSC_LINE_SIZE))
#endif /* ARCH_SSC_REGS_H */

0
arch/arm/include/asm/arch-uniphier/umc-regs.h → arch/arm/mach-uniphier/include/mach/umc-regs.h
View File

0
arch/arm/cpu/armv7/uniphier/init_page_table.S → arch/arm/mach-uniphier/init_page_table.S
View File

16
arch/arm/cpu/armv7/uniphier/lowlevel_init.S → arch/arm/mach-uniphier/lowlevel_init.S
View File

@ -7,10 +7,12 @@
#include <config.h>
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>
#include <asm/arch/led.h>
#include <asm/arch/arm-mpcore.h>
#include <asm/arch/sbc-regs.h>
#include <mach/led.h>
#include <mach/arm-mpcore.h>
#include <mach/sbc-regs.h>
#include <mach/ssc-regs.h>
ENTRY(lowlevel_init)
mov r8, lr @ persevere link reg across call
@ -122,9 +124,11 @@ ENTRY(enable_mmu)
mov pc, lr
ENDPROC(enable_mmu)
#include <asm/arch/ssc-regs.h>
#define BOOT_RAM_SIZE (SSC_WAY_SIZE)
/*
* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
* It is large enough for tmp RAM.
*/
#define BOOT_RAM_SIZE (SZ_32K)
#define BOOT_WAY_BITS (0x00000100) /* way 8 */
ENTRY(setup_init_ram)

104
arch/arm/mach-uniphier/memconf.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <linux/sizes.h>
#include <asm/io.h>
#include <mach/sg-regs.h>
static inline u32 sg_memconf_val_ch0(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH0_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH0_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH0_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH0_SZ_512M;
break;
case SZ_1G:
ret = SG_MEMCONF_CH0_SZ_1G;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH0_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH0_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
static inline u32 sg_memconf_val_ch1(unsigned long size, int num)
{
int size_mb = size / num;
u32 ret;
switch (size_mb) {
case SZ_64M:
ret = SG_MEMCONF_CH1_SZ_64M;
break;
case SZ_128M:
ret = SG_MEMCONF_CH1_SZ_128M;
break;
case SZ_256M:
ret = SG_MEMCONF_CH1_SZ_256M;
break;
case SZ_512M:
ret = SG_MEMCONF_CH1_SZ_512M;
break;
case SZ_1G:
ret = SG_MEMCONF_CH1_SZ_1G;
break;
default:
BUG();
break;
}
switch (num) {
case 1:
ret |= SG_MEMCONF_CH1_NUM_1;
break;
case 2:
ret |= SG_MEMCONF_CH1_NUM_2;
break;
default:
BUG();
break;
}
return ret;
}
void memconf_init(void)
{
u32 tmp;
/* Set DDR size */
tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
tmp |= SG_MEMCONF_SPARSEMEM;
#endif
writel(tmp, SG_MEMCONF);
}

6
arch/arm/cpu/armv7/uniphier/ph1-ld4/Makefile → arch/arm/mach-uniphier/ph1-ld4/Makefile
View File

@ -4,10 +4,12 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
obj-y += bcu_init.o sg_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif

2
arch/arm/cpu/armv7/uniphier/ph1-ld4/bcu_init.c → arch/arm/mach-uniphier/ph1-ld4/bcu_init.c
View File

@ -7,7 +7,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/bcu-regs.h>
#include <mach/bcu-regs.h>
#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))

0
arch/arm/cpu/armv7/uniphier/ph1-ld4/boot-mode.c → arch/arm/mach-uniphier/ph1-ld4/boot-mode.c
View File

42
arch/arm/mach-uniphier/ph1-ld4/clkrst_init.c Normal file
View File

@ -0,0 +1,42 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <mach/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
tmp |= SC_RSTCTRL_NRST_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

2
arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c → arch/arm/mach-uniphier/ph1-ld4/ddrphy_init.c
View File

@ -6,7 +6,7 @@
#include <linux/types.h>
#include <asm/io.h>
#include <asm/arch/ddrphy-regs.h>
#include <mach/ddrphy-regs.h>
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{

1
arch/arm/mach-uniphier/ph1-ld4/early_clkrst_init.c Normal file
View File

@ -0,0 +1 @@
#include "../ph1-pro4/early_clkrst_init.c"

4
arch/arm/cpu/armv7/uniphier/ph1-ld4/lowlevel_debug.S → arch/arm/mach-uniphier/ph1-ld4/lowlevel_debug.S
View File

@ -8,10 +8,10 @@
*/
#include <linux/linkage.h>
#include <asm/arch/sg-regs.h>
#include <mach/sg-regs.h>
#define UART_CLK 36864000
#include <asm/arch/debug-uart.S>
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
init_debug_uart r0, r1, r2

2
arch/arm/cpu/armv7/uniphier/ph1-ld4/pinctrl.c → arch/arm/mach-uniphier/ph1-ld4/pinctrl.c
View File

@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
#include <mach/sg-regs.h>
void pin_init(void)
{

16
arch/arm/cpu/armv7/uniphier/ph1-ld4/platdevice.c → arch/arm/mach-uniphier/ph1-ld4/platdevice.c
View File

@ -1,11 +1,11 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/platdevice.h>
#include <mach/platdevice.h>
#define UART_MASTER_CLK 36864000
@ -13,15 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
},
{
.base = 0x5a810100,
},
{
.base = 0x5a820100,
},
};

4
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_init.c → arch/arm/mach-uniphier/ph1-ld4/pll_init.c
View File

@ -6,8 +6,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#undef DPLL_SSC_RATE_1PER

0
arch/arm/cpu/armv7/uniphier/ph1-ld4/pll_spectrum.c → arch/arm/mach-uniphier/ph1-ld4/pll_spectrum.c
View File

50
arch/arm/mach-uniphier/ph1-ld4/sbc_init.c Normal file
View File

@ -0,0 +1,50 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
u32 tmp;
/* system bus output enable */
tmp = readl(PC0CTRL);
tmp &= 0xfffffcff;
writel(tmp, PC0CTRL);
/*
* Only CS1 is connected to support card.
* BKSZ[1:0] should be set to "01".
*/
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL10);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL11);
writel(SBCTRL2_SAVEPIN_PERI_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_PERI_VALUE, SBCTRL14);
if (boot_is_swapped()) {
/*
* Boot Swap On: boot from external NOR/SRAM
* 0x02000000-0x03ffffff is a mirror of 0x00000000-0x01ffffff.
*
* 0x00000000-0x01efffff, 0x02000000-0x03efffff: memory bank
* 0x01f00000-0x01ffffff, 0x03f00000-0x03ffffff: peripherals
*/
writel(0x0000bc01, SBBASE0);
} else {
/*
* Boot Swap Off: boot from mask ROM
* 0x00000000-0x01ffffff: mask ROM
* 0x02000000-0x03efffff: memory bank (31MB)
* 0x03f00000-0x03ffffff: peripherals (1MB)
*/
writel(0x0000be01, SBBASE0); /* dummy */
writel(0x0200be01, SBBASE1);
}
}

15
arch/arm/cpu/armv7/uniphier/ph1-ld4/sbc_init.c → arch/arm/mach-uniphier/ph1-ld4/sbc_init_3cs.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
@ -7,8 +7,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sbc-regs.h>
#include <asm/arch/sg-regs.h>
#include <mach/sbc-regs.h>
#include <mach/sg-regs.h>
void sbc_init(void)
{
@ -25,13 +25,12 @@ void sbc_init(void)
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL12);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL14);
#if !defined(CONFIG_SPL_BUILD)
/* XECS0: boot/sub memory (boot swap = off/on) */
writel(SBCTRL0_SAVEPIN_MEM_VALUE, SBCTRL00);
writel(SBCTRL1_SAVEPIN_MEM_VALUE, SBCTRL01);
writel(SBCTRL2_SAVEPIN_MEM_VALUE, SBCTRL02);
writel(SBCTRL4_SAVEPIN_MEM_VALUE, SBCTRL04);
#endif
/* XECS3: peripherals */
writel(SBCTRL0_SAVEPIN_PERI_VALUE, SBCTRL30);
writel(SBCTRL1_SAVEPIN_PERI_VALUE, SBCTRL31);
@ -43,9 +42,9 @@ void sbc_init(void)
writel(0x0400bc01, SBBASE1);
writel(0x0800bf01, SBBASE3);
#if !defined(CONFIG_SPL_BUILD)
/* enable access to sub memory when boot swap is on */
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
#endif
if (boot_is_swapped())
sg_set_pinsel(155, 1); /* PORT24 -> XECS0 */
sg_set_pinsel(156, 1); /* PORT25 -> XECS3 */
}

19
arch/arm/mach-uniphier/ph1-ld4/sg_init.c Normal file
View File

@ -0,0 +1,19 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <mach/sg-regs.h>
void sg_init(void)
{
u32 tmp;
/* Input ports must be enabled before deasserting reset of cores */
tmp = readl(SG_IECTRL);
tmp |= 0x1;
writel(tmp, SG_IECTRL);
}

4
arch/arm/cpu/armv7/uniphier/ph1-ld4/umc_init.c → arch/arm/mach-uniphier/ph1-ld4/umc_init.c
View File

@ -6,8 +6,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/umc-regs.h>
#include <asm/arch/ddrphy-regs.h>
#include <mach/umc-regs.h>
#include <mach/ddrphy-regs.h>
static void umc_start_ssif(void __iomem *ssif_base)
{

6
arch/arm/cpu/armv7/uniphier/ph1-sld8/Makefile → arch/arm/mach-uniphier/ph1-pro4/Makefile
View File

@ -4,10 +4,12 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_DEBUG_LL) += lowlevel_debug.o
obj-y += bcu_init.o sbc_init.o sg_init.o pll_init.o clkrst_init.o \
obj-y += sg_init.o pll_init.o early_clkrst_init.o \
pll_spectrum.o umc_init.o ddrphy_init.o
obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += sbc_init.o
obj-$(CONFIG_DCC_MICRO_SUPPORT_CARD) += sbc_init_3cs.o
else
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o
obj-$(CONFIG_BOARD_EARLY_INIT_F) += pinctrl.o clkrst_init.o
obj-$(if $(CONFIG_OF_CONTROL),,y) += platdevice.o
endif

6
arch/arm/cpu/armv7/uniphier/ph1-pro4/boot-mode.c → arch/arm/mach-uniphier/ph1-pro4/boot-mode.c
View File

@ -8,9 +8,9 @@
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/boot-device.h>
#include <asm/arch/sg-regs.h>
#include <asm/arch/sbc-regs.h>
#include <mach/boot-device.h>
#include <mach/sg-regs.h>
#include <mach/sbc-regs.h>
struct boot_device_info boot_device_table[] = {
{BOOT_DEVICE_NAND, "NAND (Mirror 8, ECC 8, EraseSize 128KB, Addr 4)"},

57
arch/arm/mach-uniphier/ph1-pro4/clkrst_init.c Normal file
View File

@ -0,0 +1,57 @@
/*
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/io.h>
#include <mach/sc-regs.h>
void clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp |= SC_RSTCTRL_NRST_USB3B0 | SC_RSTCTRL_NRST_USB3C0 |
SC_RSTCTRL_NRST_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_RSTCTRL_NRST_ETHER;
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
tmp |= SC_RSTCTRL_NRST_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_RSTCTRL_NRST_NAND;
#endif
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp = readl(SC_RSTCTRL2);
tmp |= SC_RSTCTRL2_NRST_USB3B1 | SC_RSTCTRL2_NRST_USB3C1;
writel(tmp, SC_RSTCTRL2);
readl(SC_RSTCTRL2); /* dummy read */
#endif
/* privide clocks */
tmp = readl(SC_CLKCTRL);
#ifdef CONFIG_USB_XHCI_UNIPHIER
tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
SC_CLKCTRL_CEN_GIO;
#endif
#ifdef CONFIG_UNIPHIER_ETH
tmp |= SC_CLKCTRL_CEN_ETHER;
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
#endif
#ifdef CONFIG_NAND_DENALI
tmp |= SC_CLKCTRL_CEN_NAND;
#endif
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

2
arch/arm/cpu/armv7/uniphier/ph1-pro4/ddrphy_init.c → arch/arm/mach-uniphier/ph1-pro4/ddrphy_init.c
View File

@ -6,7 +6,7 @@
#include <linux/types.h>
#include <asm/io.h>
#include <asm/arch/ddrphy-regs.h>
#include <mach/ddrphy-regs.h>
void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
{

16
arch/arm/cpu/armv7/uniphier/ph1-sld8/clkrst_init.c → arch/arm/mach-uniphier/ph1-pro4/early_clkrst_init.c
View File

@ -1,29 +1,31 @@
/*
* Copyright (C) 2011-2014 Panasonic Corporation
* Copyright (C) 2011-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <mach/sc-regs.h>
void clkrst_init(void)
void early_clkrst_init(void)
{
u32 tmp;
/* deassert reset */
tmp = readl(SC_RSTCTRL);
tmp |= SC_RSTCTRL_NRST_ETHER | SC_RSTCTRL_NRST_UMC1
| SC_RSTCTRL_NRST_UMC0 | SC_RSTCTRL_NRST_NAND;
tmp |= SC_RSTCTRL_NRST_UMC1 | SC_RSTCTRL_NRST_UMC0;
if (spl_boot_device() != BOOT_DEVICE_NAND)
tmp &= ~SC_RSTCTRL_NRST_NAND;
writel(tmp, SC_RSTCTRL);
readl(SC_RSTCTRL); /* dummy read */
/* privide clocks */
tmp = readl(SC_CLKCTRL);
tmp |= SC_CLKCTRL_CLK_ETHER | SC_CLKCTRL_CLK_MIO | SC_CLKCTRL_CLK_UMC
| SC_CLKCTRL_CLK_NAND | SC_CLKCTRL_CLK_SBC | SC_CLKCTRL_CLK_PERI;
tmp |= SC_CLKCTRL_CEN_UMC | SC_CLKCTRL_CEN_SBC | SC_CLKCTRL_CEN_PERI;
writel(tmp, SC_CLKCTRL);
readl(SC_CLKCTRL); /* dummy read */
}

8
arch/arm/cpu/armv7/uniphier/ph1-pro4/lowlevel_debug.S → arch/arm/mach-uniphier/ph1-pro4/lowlevel_debug.S
View File

@ -8,16 +8,16 @@
*/
#include <linux/linkage.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#define UART_CLK 73728000
#include <asm/arch/debug-uart.S>
#include <mach/debug-uart.S>
ENTRY(setup_lowlevel_debug)
ldr r0, =SC_CLKCTRL
ldr r1, [r0]
orr r1, r1, #SC_CLKCTRL_CLK_PERI
orr r1, r1, #SC_CLKCTRL_CEN_PERI
str r1, [r0]
init_debug_uart r0, r1, r2

9
arch/arm/cpu/armv7/uniphier/ph1-pro4/pinctrl.c → arch/arm/mach-uniphier/ph1-pro4/pinctrl.c
View File

@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sg-regs.h>
#include <mach/sg-regs.h>
void pin_init(void)
{
@ -41,6 +41,13 @@ void pin_init(void)
sg_set_pinsel(54, 0); /* NRYBY0 -> NRYBY0 */
#endif
#ifdef CONFIG_USB_XHCI_UNIPHIER
sg_set_pinsel(180, 0); /* USB0VBUS -> USB0VBUS */
sg_set_pinsel(181, 0); /* USB0OD -> USB0OD */
sg_set_pinsel(182, 0); /* USB1VBUS -> USB1VBUS */
sg_set_pinsel(183, 0); /* USB1OD -> USB1OD */
#endif
#ifdef CONFIG_USB_EHCI_UNIPHIER
sg_set_pinsel(184, 0); /* USB2VBUS -> USB2VBUS */
sg_set_pinsel(185, 0); /* USB2OD -> USB2OD */

13
arch/arm/cpu/armv7/uniphier/ph1-pro4/platdevice.c → arch/arm/mach-uniphier/ph1-pro4/platdevice.c
View File

@ -1,11 +1,11 @@
/*
* Copyright (C) 2014 Panasonic Corporation
* Copyright (C) 2014-2015 Panasonic Corporation
* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/platdevice.h>
#include <mach/platdevice.h>
#define UART_MASTER_CLK 73728000
@ -13,12 +13,3 @@ SERIAL_DEVICE(0, 0x54006800, UART_MASTER_CLK)
SERIAL_DEVICE(1, 0x54006900, UART_MASTER_CLK)
SERIAL_DEVICE(2, 0x54006a00, UART_MASTER_CLK)
SERIAL_DEVICE(3, 0x54006b00, UART_MASTER_CLK)
struct uniphier_ehci_platform_data uniphier_ehci_platdata[] = {
{
.base = 0x5a800100,
},
{
.base = 0x5a810100,
},
};

21
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_init.c → arch/arm/mach-uniphier/ph1-pro4/pll_init.c
View File

@ -6,8 +6,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <asm/arch/sg-regs.h>
#include <mach/sc-regs.h>
#include <mach/sg-regs.h>
#undef DPLL_SSC_RATE_1PER
@ -46,22 +46,6 @@ static void dpll_init(void)
writel(tmp, SC_DPLLCTRL2);
}
static void stop_mpll(void)
{
u32 tmp;
tmp = readl(SC_MPLLOSCCTL);
if (!(tmp & SC_MPLLOSCCTL_MPLLST))
return; /* already stopped */
tmp &= ~SC_MPLLOSCCTL_MPLLEN;
writel(tmp, SC_MPLLOSCCTL);
while (readl(SC_MPLLOSCCTL) & SC_MPLLOSCCTL_MPLLST)
;
}
static void vpll_init(void)
{
u32 tmp, clk_mode_axosel;
@ -157,7 +141,6 @@ static void vpll_init(void)
void pll_init(void)
{
dpll_init();
stop_mpll();
vpll_init();
/*

2
arch/arm/cpu/armv7/uniphier/ph1-pro4/pll_spectrum.c → arch/arm/mach-uniphier/ph1-pro4/pll_spectrum.c
View File

@ -6,7 +6,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sc-regs.h>
#include <mach/sc-regs.h>
void enable_dpll_ssc(void)
{

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