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https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
Deassert the reset signal and provide the clock for STDMAC core. This is necessary for the USB 2.0 host controllers. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
43 lines
878 B
C
43 lines
878 B
C
/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <mach/sc-regs.h>
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void clkrst_init(void)
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{
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u32 tmp;
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/* deassert reset */
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tmp = readl(SC_RSTCTRL);
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#ifdef CONFIG_UNIPHIER_ETH
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tmp |= SC_RSTCTRL_NRST_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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tmp |= SC_RSTCTRL_NRST_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_RSTCTRL_NRST_NAND;
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#endif
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writel(tmp, SC_RSTCTRL);
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readl(SC_RSTCTRL); /* dummy read */
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/* privide clocks */
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tmp = readl(SC_CLKCTRL);
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#ifdef CONFIG_UNIPHIER_ETH
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tmp |= SC_CLKCTRL_CEN_ETHER;
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#endif
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#ifdef CONFIG_USB_EHCI_UNIPHIER
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tmp |= SC_CLKCTRL_CEN_MIO | SC_CLKCTRL_CEN_STDMAC;
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#endif
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#ifdef CONFIG_NAND_DENALI
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tmp |= SC_CLKCTRL_CEN_NAND;
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#endif
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writel(tmp, SC_CLKCTRL);
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readl(SC_CLKCTRL); /* dummy read */
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}
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