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arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 

Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
This commit is contained in:
Siew Chin Lim 2021-03-01 20:04:10 +08:00 committed by Ley Foon Tan
parent e4dba4ba6f
commit 9a5bbdfd1a
7 changed files with 15 additions and 12 deletions
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6
arch/arm/Kconfig
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@ -970,7 +970,7 @@ config ARCH_SOCFPGA
bool "Altera SOCFPGA family" bool "Altera SOCFPGA family"
select ARCH_EARLY_INIT_R select ARCH_EARLY_INIT_R
select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select ARM64 if TARGET_SOCFPGA_SOC64
select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select DM select DM
select DM_SERIAL select DM_SERIAL
@ -982,7 +982,7 @@ config ARCH_SOCFPGA
select SPL_LIBGENERIC_SUPPORT select SPL_LIBGENERIC_SUPPORT
select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_NAND_SUPPORT if SPL_NAND_DENALI
select SPL_OF_CONTROL select SPL_OF_CONTROL
select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
select SPL_SERIAL_SUPPORT select SPL_SERIAL_SUPPORT
select SPL_SYSRESET select SPL_SYSRESET
select SPL_WATCHDOG_SUPPORT select SPL_WATCHDOG_SUPPORT
@ -991,7 +991,7 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
imply CMD_DM imply CMD_DM
imply CMD_MTDPARTS imply CMD_MTDPARTS
imply CRC32_VERIFY imply CRC32_VERIFY

5
arch/arm/mach-socfpga/Kconfig
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@ -38,6 +38,7 @@ config TARGET_SOCFPGA_AGILEX
select FPGA_INTEL_SDM_MAILBOX select FPGA_INTEL_SDM_MAILBOX
select NCORE_CACHE select NCORE_CACHE
select SPL_CLK if SPL select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64
config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA5
bool bool
@ -75,12 +76,16 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF imply SPL_USE_TINY_PRINTF
config TARGET_SOCFPGA_SOC64
bool
config TARGET_SOCFPGA_STRATIX10 config TARGET_SOCFPGA_STRATIX10
bool bool
select ARMV8_MULTIENTRY select ARMV8_MULTIENTRY
select ARMV8_SET_SMPEN select ARMV8_SET_SMPEN
select BINMAN if SPL_ATF select BINMAN if SPL_ATF
select FPGA_INTEL_SDM_MAILBOX select FPGA_INTEL_SDM_MAILBOX
select TARGET_SOCFPGA_SOC64
choice choice
prompt "Altera SOCFPGA board select" prompt "Altera SOCFPGA board select"

3
arch/arm/mach-socfpga/include/mach/reset_manager.h
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@ -43,8 +43,7 @@ void socfpga_per_reset_all(void);
#include <asm/arch/reset_manager_gen5.h> #include <asm/arch/reset_manager_gen5.h>
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#include <asm/arch/reset_manager_arria10.h> #include <asm/arch/reset_manager_arria10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ #elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include <asm/arch/reset_manager_soc64.h> #include <asm/arch/reset_manager_soc64.h>
#endif #endif

3
arch/arm/mach-socfpga/include/mach/system_manager.h
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@ -8,8 +8,7 @@
phys_addr_t socfpga_get_sysmgr_addr(void); phys_addr_t socfpga_get_sysmgr_addr(void);
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ #if defined(CONFIG_TARGET_SOCFPGA_SOC64)
defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include <asm/arch/system_manager_soc64.h> #include <asm/arch/system_manager_soc64.h>
#else #else
#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)

6
drivers/ddr/altera/Kconfig
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@ -1,8 +1,8 @@
config SPL_ALTERA_SDRAM config SPL_ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver in SPL" bool "SoCFPGA DDR SDRAM driver in SPL"
depends on SPL depends on SPL
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64
select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
help help
Enable DDR SDRAM controller for the SoCFPGA devices. Enable DDR SDRAM controller for the SoCFPGA devices.

2
drivers/fpga/Kconfig
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@ -33,7 +33,7 @@ config FPGA_CYCLON2
config FPGA_INTEL_SDM_MAILBOX config FPGA_INTEL_SDM_MAILBOX
bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX depends on TARGET_SOCFPGA_SOC64
select FPGA_ALTERA select FPGA_ALTERA
help help
Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver

2
drivers/sysreset/Kconfig
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@ -94,7 +94,7 @@ config SYSRESET_SOCFPGA
config SYSRESET_SOCFPGA_SOC64 config SYSRESET_SOCFPGA_SOC64
bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX) depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64
help help
This enables the system reset driver support for Intel SOCFPGA This enables the system reset driver support for Intel SOCFPGA
SoC64 SoCs. SoC64 SoCs.