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arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
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@ -970,7 +970,7 @@ config ARCH_SOCFPGA
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bool "Altera SOCFPGA family"
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bool "Altera SOCFPGA family"
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select ARCH_EARLY_INIT_R
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select ARCH_EARLY_INIT_R
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select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
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select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
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select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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select ARM64 if TARGET_SOCFPGA_SOC64
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select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select DM
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select DM
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select DM_SERIAL
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select DM_SERIAL
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@ -982,7 +982,7 @@ config ARCH_SOCFPGA
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select SPL_LIBGENERIC_SUPPORT
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select SPL_LIBGENERIC_SUPPORT
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select SPL_NAND_SUPPORT if SPL_NAND_DENALI
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select SPL_NAND_SUPPORT if SPL_NAND_DENALI
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select SPL_OF_CONTROL
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select SPL_OF_CONTROL
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select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
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select SPL_SERIAL_SUPPORT
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select SPL_SERIAL_SUPPORT
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select SPL_SYSRESET
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select SPL_SYSRESET
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select SPL_WATCHDOG_SUPPORT
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select SPL_WATCHDOG_SUPPORT
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@ -991,7 +991,7 @@ config ARCH_SOCFPGA
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select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select SYSRESET
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select SYSRESET
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select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
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select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
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imply CMD_DM
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imply CMD_DM
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imply CMD_MTDPARTS
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imply CMD_MTDPARTS
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imply CRC32_VERIFY
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imply CRC32_VERIFY
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@ -38,6 +38,7 @@ config TARGET_SOCFPGA_AGILEX
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select FPGA_INTEL_SDM_MAILBOX
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select FPGA_INTEL_SDM_MAILBOX
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select NCORE_CACHE
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select NCORE_CACHE
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select SPL_CLK if SPL
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select SPL_CLK if SPL
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select TARGET_SOCFPGA_SOC64
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config TARGET_SOCFPGA_ARRIA5
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config TARGET_SOCFPGA_ARRIA5
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bool
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bool
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@ -75,12 +76,16 @@ config TARGET_SOCFPGA_GEN5
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imply SPL_SYS_MALLOC_SIMPLE
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imply SPL_SYS_MALLOC_SIMPLE
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imply SPL_USE_TINY_PRINTF
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imply SPL_USE_TINY_PRINTF
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config TARGET_SOCFPGA_SOC64
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bool
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config TARGET_SOCFPGA_STRATIX10
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config TARGET_SOCFPGA_STRATIX10
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bool
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bool
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select ARMV8_MULTIENTRY
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select ARMV8_MULTIENTRY
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select ARMV8_SET_SMPEN
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select ARMV8_SET_SMPEN
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select BINMAN if SPL_ATF
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select BINMAN if SPL_ATF
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select FPGA_INTEL_SDM_MAILBOX
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select FPGA_INTEL_SDM_MAILBOX
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select TARGET_SOCFPGA_SOC64
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choice
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choice
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prompt "Altera SOCFPGA board select"
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prompt "Altera SOCFPGA board select"
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@ -43,8 +43,7 @@ void socfpga_per_reset_all(void);
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#include <asm/arch/reset_manager_gen5.h>
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#include <asm/arch/reset_manager_gen5.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
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#include <asm/arch/reset_manager_arria10.h>
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#include <asm/arch/reset_manager_arria10.h>
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#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
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#elif defined(CONFIG_TARGET_SOCFPGA_SOC64)
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defined(CONFIG_TARGET_SOCFPGA_AGILEX)
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#include <asm/arch/reset_manager_soc64.h>
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#include <asm/arch/reset_manager_soc64.h>
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#endif
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#endif
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@ -8,8 +8,7 @@
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phys_addr_t socfpga_get_sysmgr_addr(void);
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phys_addr_t socfpga_get_sysmgr_addr(void);
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#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
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#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
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defined(CONFIG_TARGET_SOCFPGA_AGILEX)
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#include <asm/arch/system_manager_soc64.h>
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#include <asm/arch/system_manager_soc64.h>
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#else
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#else
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
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@ -1,8 +1,8 @@
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config SPL_ALTERA_SDRAM
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config SPL_ALTERA_SDRAM
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bool "SoCFPGA DDR SDRAM driver in SPL"
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bool "SoCFPGA DDR SDRAM driver in SPL"
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depends on SPL
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depends on SPL
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depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64
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select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
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select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64
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help
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help
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Enable DDR SDRAM controller for the SoCFPGA devices.
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Enable DDR SDRAM controller for the SoCFPGA devices.
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@ -33,7 +33,7 @@ config FPGA_CYCLON2
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config FPGA_INTEL_SDM_MAILBOX
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config FPGA_INTEL_SDM_MAILBOX
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bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
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bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver"
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depends on TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
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depends on TARGET_SOCFPGA_SOC64
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select FPGA_ALTERA
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select FPGA_ALTERA
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help
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help
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Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
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Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver
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@ -94,7 +94,7 @@ config SYSRESET_SOCFPGA
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config SYSRESET_SOCFPGA_SOC64
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config SYSRESET_SOCFPGA_SOC64
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bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
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bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)"
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depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX)
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depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64
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help
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help
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This enables the system reset driver support for Intel SOCFPGA
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This enables the system reset driver support for Intel SOCFPGA
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SoC64 SoCs.
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SoC64 SoCs.
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