ARC: nSIM: switch from ARC UART to DW UART

Since v2019.06 DesingWare nSIM supports DesignWare UART simulation
and so we may switch from pretty unusual ARC UART to much more standard
DesignWare UART (which in case of U-Boot is just an ordinary 16650 UART).

This among other things makes built dinaries compatible with our other
platforms to name a few: FPGA-based HAPS boards, QEMU and even ZeBU.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin 2019-12-26 13:46:27 +03:00
parent 26d4d77035
commit 9515e41d38
5 changed files with 23 additions and 21 deletions

View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
* Copyright (C) 2015-2016, 2020 Synopsys, Inc. (www.synopsys.com)
*/
/dts-v1/;
@ -10,7 +10,7 @@
model = "snps,nsim";
aliases {
console = &arcuart0;
console = &uart0;
};
cpu_card {
@ -22,9 +22,11 @@
};
};
arcuart0: serial@0xc0fc1000 {
compatible = "snps,arc-uart";
reg = <0xc0fc1000 0x100>;
uart0: serial@f0000000 {
compatible = "snps,dw-apb-uart";
reg = <0xf0000000 0x1000>;
reg-shift = <2>;
reg-io-width = <4>;
clock-frequency = <70000000>;
};

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@ -1,13 +1,13 @@
CONFIG_ARC=y
CONFIG_TARGET_NSIM=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEBUG_UART_BASE=0xc0fc1000
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
@ -16,6 +16,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_ARC_SERIAL=y
CONFIG_ARC_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y

View File

@ -2,13 +2,13 @@ CONFIG_ARC=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_TARGET_NSIM=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEBUG_UART_BASE=0xc0fc1000
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
@ -17,6 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_ARC_SERIAL=y
CONFIG_ARC_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y

View File

@ -2,13 +2,13 @@ CONFIG_ARC=y
CONFIG_ISA_ARCV2=y
CONFIG_TARGET_NSIM=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEBUG_UART_BASE=0xc0fc1000
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
@ -17,6 +17,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_ARC_SERIAL=y
CONFIG_ARC_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y

View File

@ -3,13 +3,13 @@ CONFIG_ISA_ARCV2=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_TARGET_NSIM=y
CONFIG_SYS_TEXT_BASE=0x81000000
CONFIG_DEBUG_UART_BASE=0xc0fc1000
CONFIG_DEBUG_UART_BASE=0xf0000000
CONFIG_DEBUG_UART_CLOCK=70000000
CONFIG_SYS_CLK_FREQ=70000000
CONFIG_DEBUG_UART=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyARC0,115200n8"
CONFIG_BOOTARGS="console=ttyS0,115200n8"
CONFIG_SYS_PROMPT="nsim# "
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
@ -18,6 +18,6 @@ CONFIG_DEFAULT_DEVICE_TREE="nsim"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DM_SERIAL=y
CONFIG_DEBUG_ARC_SERIAL=y
CONFIG_ARC_SERIAL=y
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550=y
CONFIG_USE_PRIVATE_LIBGCC=y