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https://github.com/brain-hackers/u-boot-brain
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arm: dart6ul: enable DM_ETH for the dart6ul
This patch converts the dart6ul ethernet support to DM_ETH and cleans up the legacy ethernet code. The clean up, more specifically: * moves the fec2 node and pin definition to the carrier board DTS since the phy associated with it is on the carrier board and not on the SoM; * add the reset pin associated to each phy; * separate the ethernet, mdio and reset pins of each fec so that they are easier to reference; * add clock properties to the phy nodes since they are connected to the 50Mhz ENET[12]_TX_CLK clock of the SoC; * remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
This commit is contained in:
parent
4736871dc2
commit
9452d58e10
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
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*/
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/dts-v1/;
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@ -13,6 +14,28 @@
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compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
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};
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&mdio1 {
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/* KSZ8081RNB (carrier-board) */
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ethphy1: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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clocks = <&clks IMX6UL_CLK_ENET2_REF>;
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clock-names = "rmii-ref";
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micrel,led-mode = <1>;
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max-speed = <100>;
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reg = <3>;
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_rst>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <100>;
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status = "okay";
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};
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&usdhc2 {
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status = "okay";
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};
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@ -36,4 +59,29 @@
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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>;
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};
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pinctrl_enet2_mdio: mdio_enet2_grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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>;
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};
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pinctrl_enet2_rst: enet2-rst-grp {
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fsl,pins = <
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MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0
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>;
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};
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};
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@ -1,6 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
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*/
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/ {
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@ -22,36 +23,25 @@
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_rst &pinctrl_enet1_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <100>;
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status = "okay";
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mdio1: mdio1 {
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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/* KSZ8081RNB (SoM) */
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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micrel,led-mode = <1>;
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max-speed = <100>;
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reg = <1>;
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micrel,led-mode = <1>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio2: mdio2 {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@2 {
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reg = <2>;
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micrel,led-mode = <1>;
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};
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};
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};
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@ -149,10 +139,9 @@
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&iomuxc {
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pinctrl-names = "default";
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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@ -164,18 +153,10 @@
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>;
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};
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pinctrl_enet2: enet2grp {
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pinctrl_enet1_mdio: enet1-mdio-grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0X1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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>;
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};
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@ -272,3 +253,11 @@
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>;
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};
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};
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&iomuxc_snvs {
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pinctrl_enet1_rst: enet1-rst-grp {
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fsl,pins = <
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MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0
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>;
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};
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};
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@ -2,6 +2,7 @@
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/*
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* Copyright (C) 2015-2019 Variscite Ltd.
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* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
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* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
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*/
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#include <init.h>
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#include <linux/bitops.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <usb.h>
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#include <usb/ehci-ci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#endif
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#ifdef CONFIG_FEC_MXC
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
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PAD_CTL_SRE_FAST)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
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PAD_CTL_ODE)
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/*
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* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
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* be used for ENET1 or ENET2, cannot be used for both.
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*/
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static iomux_v3_cfg_t const fec1_pads[] = {
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MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static iomux_v3_cfg_t const fec2_pads[] = {
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MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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};
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static void setup_iomux_fec(int fec_id)
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{
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if (fec_id == 0)
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imx_iomux_v3_setup_multiple_pads(fec1_pads,
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ARRAY_SIZE(fec1_pads));
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else
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imx_iomux_v3_setup_multiple_pads(fec2_pads,
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ARRAY_SIZE(fec2_pads));
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}
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int board_eth_init(struct bd_info *bis)
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{
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int ret = 0;
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ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
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CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
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#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
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/* USB Ethernet Gadget */
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usb_eth_initialize(bis);
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#endif
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return ret;
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}
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static int setup_fec(int fec_id)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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}
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#endif /* CONFIG_FEC_MXC */
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int board_early_init_f(void)
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{
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setup_iomux_fec(CONFIG_FEC_ENET_DEV);
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return 0;
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}
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int board_init(void)
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{
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/* Address of boot parameters */
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setup_iomux_uart();
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/* iomux and setup of i2c */
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board_early_init_f();
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/* UART clocks enabled and gd valid - init serial console */
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preloader_console_init();
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
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CONFIG_BOOTDELAY=3
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# CONFIG_USE_BOOTCOMMAND is not set
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SPL_USB_HOST_SUPPORT=y
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CONFIG_SPL_WATCHDOG_SUPPORT=y
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CONFIG_CMD_DM=y
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CONFIG_MTD=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_MICREL=y
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CONFIG_DM_ETH_PHY=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_ENET_DEV 0
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#if (CONFIG_FEC_ENET_DEV == 0)
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "eth0"
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#elif (CONFIG_FEC_ENET_DEV == 1)
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x3
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_ETHPRIME "eth1"
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#endif
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#endif
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