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9452d58e10
u-boot-brain/arch/arm/dts/imx6ull-dart-6ul.dtsi
Marc Ferland 9452d58e10 arm: dart6ul: enable DM_ETH for the dart6ul 
This patch converts the dart6ul ethernet support to DM_ETH and cleans
up the legacy ethernet code. The clean up, more specifically:

* moves the fec2 node and pin definition to the carrier board DTS
  since the phy associated with it is on the carrier board and not on
  the SoM;
* add the reset pin associated to each phy;
* separate the ethernet, mdio and reset pins of each fec so that they
  are easier to reference;
* add clock properties to the phy nodes since they are connected to the
  50Mhz ENET[12]_TX_CLK clock of the SoC;
* remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty.

Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
2021-01-23 11:30:31 +01:00

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
*/
/ {
model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
memory {
reg = <0x80000000 0x20000000>;
};
chosen {
stdout-path = &uart1;
};
aliases {
eeprom0 = &eeprom_som;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_rst &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
phy-reset-duration = <100>;
status = "okay";
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
/* KSZ8081RNB (SoM) */
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
micrel,led-mode = <1>;
max-speed = <100>;
reg = <1>;
};
};
};
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "uboot";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "uboot-env";
reg = <0x400000 0x100000>;
};
partition@500000 {
label = "root";
reg = <0x500000 0x0>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
status = "okay";
u-boot,dm-pre-reloc;
eeprom_som: eeprom@50 {
u-boot,dm-pre-reloc;
compatible = "atmel,24c04";
reg = <0x50>;
status = "okay";
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
#pwm-cells = <3>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
bus-width = <0x4>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet1_mdio: enet1-mdio-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_i2c1: i2cgrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
>;
};
pinctrl_i2c2: i2cgrp {
u-boot,dm-pre-reloc;
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_i2c2_gpio: i2c2grp_gpio {
u-boot,dm-pre-reloc;
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};
&iomuxc_snvs {
pinctrl_enet1_rst: enet1-rst-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0
>;
};
};
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