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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-21 12:10:24 +09:00
Merge git://git.denx.de/u-boot-mmc
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commit
8b4a610af9
@ -93,6 +93,9 @@ int exynos_power_init(void)
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struct udevice *dev;
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struct udevice *dev;
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int ret;
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int ret;
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#ifdef CONFIG_PMIC_S2MPS11
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ret = pmic_get("s2mps11_pmic", &dev);
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#else
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ret = pmic_get("max77686", &dev);
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ret = pmic_get("max77686", &dev);
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if (!ret) {
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if (!ret) {
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/* TODO(sjg@chromium.org): Move into the clock/pmic API */
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/* TODO(sjg@chromium.org): Move into the clock/pmic API */
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@ -112,6 +115,7 @@ int exynos_power_init(void)
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s5m8767_enable_32khz_cp(dev);
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s5m8767_enable_32khz_cp(dev);
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#endif
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#endif
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}
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}
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#endif /* CONFIG_PMIC_S2MPS11 */
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if (ret == -ENODEV)
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if (ret == -ENODEV)
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return 0;
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return 0;
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@ -1689,7 +1689,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
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#if CONFIG_IS_ENABLED(MMC_WRITE)
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#if CONFIG_IS_ENABLED(MMC_WRITE)
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err = sd_read_ssr(mmc);
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err = sd_read_ssr(mmc);
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if (!err)
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if (err)
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pr_warn("unable to read ssr\n");
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pr_warn("unable to read ssr\n");
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#endif
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#endif
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if (!err)
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if (!err)
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@ -462,7 +462,8 @@ static int sdhci_set_ios(struct mmc *mmc)
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else
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else
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ctrl &= ~SDHCI_CTRL_HISPD;
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ctrl &= ~SDHCI_CTRL_HISPD;
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if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)
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if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
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(host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
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ctrl &= ~SDHCI_CTRL_HISPD;
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ctrl &= ~SDHCI_CTRL_HISPD;
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
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@ -602,6 +603,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
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cfg->host_caps &= ~MMC_MODE_8BIT;
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cfg->host_caps &= ~MMC_MODE_8BIT;
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}
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}
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if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
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cfg->host_caps &= ~MMC_MODE_HS;
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cfg->host_caps &= ~MMC_MODE_HS_52MHz;
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}
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if (host->host_caps)
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if (host->host_caps)
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cfg->host_caps |= host->host_caps;
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cfg->host_caps |= host->host_caps;
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@ -54,7 +54,7 @@ static int arasan_sdhci_probe(struct udevice *dev)
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SDHCI_QUIRK_BROKEN_R1B;
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SDHCI_QUIRK_BROKEN_R1B;
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#ifdef CONFIG_ZYNQ_HISPD_BROKEN
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#ifdef CONFIG_ZYNQ_HISPD_BROKEN
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host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT;
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host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
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#endif
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#endif
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host->max_clk = clock;
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host->max_clk = clock;
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@ -60,8 +60,6 @@ static int power_update_battery(struct pmic *p, struct pmic *bat)
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return ret;
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return ret;
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max77693_get_vcell(&pb->bat->voltage_uV);
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max77693_get_vcell(&pb->bat->voltage_uV);
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if (ret)
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return ret;
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return 0;
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return 0;
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}
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}
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@ -213,6 +213,12 @@
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#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
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#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
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#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
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#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
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#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
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#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
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/*
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* SDHCI_QUIRK_BROKEN_HISPD_MODE
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* the hardware cannot operate correctly in high-speed mode,
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* this quirk forces the sdhci host-controller to non high-speed mode
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*/
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#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5)
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#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
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#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
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#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
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#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
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