From 4f0a8bf669f24771d1e4ca89a1f2b1ca39e50e47 Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Mon, 29 Jan 2018 13:53:19 +0900 Subject: [PATCH 1/5] samsung: board: init the s2mps11 pmic during booting time Exynos5422 board has s2mps11 pmic. If CONFIG_PMIC_S2MPS11 is enabled, it can initialize PMIC and Regulators during booting time. Signed-off-by: Jaehoon Chung Tested-by: Anand Moon --- board/samsung/common/exynos5-dt.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index a4eb351405..862644b00e 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -93,6 +93,9 @@ int exynos_power_init(void) struct udevice *dev; int ret; +#ifdef CONFIG_PMIC_S2MPS11 + ret = pmic_get("s2mps11_pmic", &dev); +#else ret = pmic_get("max77686", &dev); if (!ret) { /* TODO(sjg@chromium.org): Move into the clock/pmic API */ @@ -112,6 +115,7 @@ int exynos_power_init(void) s5m8767_enable_32khz_cp(dev); #endif } +#endif /* CONFIG_PMIC_S2MPS11 */ if (ret == -ENODEV) return 0; From 0a4c2b099ed44a18c7768001cb974e80bff0f46b Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 5 Mar 2018 16:20:40 +0800 Subject: [PATCH 2/5] mmc: fix return value check condition sd_read_ssr returns 0, means no error. Fixes: 5b2e72f32721484("mmc: read ssr only if MMC write support is enabled") Signed-off-by: Peng Fan Cc: Jaehoon Chung Cc: Jean-Jacques Hiblot --- drivers/mmc/mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f72b80c704..fe7c0b39ac 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -1689,7 +1689,7 @@ static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps) #if CONFIG_IS_ENABLED(MMC_WRITE) err = sd_read_ssr(mmc); - if (!err) + if (err) pr_warn("unable to read ssr\n"); #endif if (!err) From 88a57125fa689f3207c5409ef6eeb6a47ff051cd Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Wed, 7 Mar 2018 08:00:56 +0100 Subject: [PATCH 3/5] mmc: sdhci: add SDHCI_QUIRK_BROKEN_HISPD_MODE Some IP-core implementations of the SDHCI have different troubles on the silicon where they are placed. On ZYNQ platform for example Xilinx doesn't accept the hold timing of an eMMC chip which operates in High-Speed mode and must be forced to operate in non high-speed mode. To get rid of this "SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced. For more details about this refer to the Xilinx answer-recor #59999 https://www.xilinx.com/support/answers/59999.html This commit: - doesn't set HISPD bit on the host-conroller - reflects this fact within the host-controller capabilities Upon this the layer above (mmc-driver) can setup the card correctly. Otherwise the MMC card will be switched into high-speed mode and causes possible timing violation on the host-controller side. Signed-off-by: Hannes Schmelzer Signed-off-by: Hannes Schmelzer --- drivers/mmc/sdhci.c | 8 +++++++- include/sdhci.h | 6 ++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c index d31793a7b7..1e5e8a6159 100644 --- a/drivers/mmc/sdhci.c +++ b/drivers/mmc/sdhci.c @@ -462,7 +462,8 @@ static int sdhci_set_ios(struct mmc *mmc) else ctrl &= ~SDHCI_CTRL_HISPD; - if (host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) + if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) || + (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE)) ctrl &= ~SDHCI_CTRL_HISPD; sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); @@ -602,6 +603,11 @@ int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host, cfg->host_caps &= ~MMC_MODE_8BIT; } + if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) { + cfg->host_caps &= ~MMC_MODE_HS; + cfg->host_caps &= ~MMC_MODE_HS_52MHz; + } + if (host->host_caps) cfg->host_caps |= host->host_caps; diff --git a/include/sdhci.h b/include/sdhci.h index 7e84012f60..ed35f0434a 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -213,6 +213,12 @@ #define SDHCI_QUIRK_BROKEN_R1B (1 << 2) #define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3) #define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4) +/* + * SDHCI_QUIRK_BROKEN_HISPD_MODE + * the hardware cannot operate correctly in high-speed mode, + * this quirk forces the sdhci host-controller to non high-speed mode + */ +#define SDHCI_QUIRK_BROKEN_HISPD_MODE BIT(5) #define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6) #define SDHCI_QUIRK_USE_WIDE8 (1 << 8) From 4781921630f9f2dd1165cc1e79494893e8e9bd3c Mon Sep 17 00:00:00 2001 From: Hannes Schmelzer Date: Wed, 7 Mar 2018 08:00:57 +0100 Subject: [PATCH 4/5] mmc: zynq_sdhci: use correct quirk if CONFIG_ZYNQ_HISPD_BROKEN is defined The 'SDHCI_QUIRK_NO_HISPD_BIT' is used wrong here. The purpose of this quirk is to tell the sdhci-driver that the IP-core doesn't have a "high- speed-enable" bit in its registers. With this commit we change this to the correct quirk: SDHCI_QUIRK_BROKEN_HISPD_MODE Signed-off-by: Hannes Schmelzer --- drivers/mmc/zynq_sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 9463a06ebc..76fe97f6ef 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -54,7 +54,7 @@ static int arasan_sdhci_probe(struct udevice *dev) SDHCI_QUIRK_BROKEN_R1B; #ifdef CONFIG_ZYNQ_HISPD_BROKEN - host->quirks |= SDHCI_QUIRK_NO_HISPD_BIT; + host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE; #endif host->max_clk = clock; From 4bf225aa87a11f5d22b22d469e77d005ad441fd8 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Sun, 18 Mar 2018 11:52:45 +0100 Subject: [PATCH 5/5] drivers:power:max77693: remove redundant logical constraint As ret is not set when calling max77693_get_vcell() there is no need to check ret again. Signed-off-by: Heinrich Schuchardt --- drivers/power/mfd/fg_max77693.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/power/mfd/fg_max77693.c b/drivers/power/mfd/fg_max77693.c index df1550816e..a1407318ef 100644 --- a/drivers/power/mfd/fg_max77693.c +++ b/drivers/power/mfd/fg_max77693.c @@ -60,8 +60,6 @@ static int power_update_battery(struct pmic *p, struct pmic *bat) return ret; max77693_get_vcell(&pb->bat->voltage_uV); - if (ret) - return ret; return 0; }