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sharp: format

This commit is contained in:
Takumi Sueda 2020-10-26 02:31:46 +09:00 committed by Suguru Saito
parent 662e02ec58
commit 87abacbd9c
4 changed files with 305 additions and 290 deletions
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115
board/sharp/common/lcd.c
View File

@ -14,76 +14,17 @@ DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_VIDEO_MXS
static lcd_regs_t regs_early[] = {
{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
{ 0xfd, 0, 0 }, /* PFM Type C */
{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
{ 0xf8, 0, 0 }, /* PFM Type C */
{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
{ 0x72, 1, 0 },
{ 0xf1, 0, 0 }, /* Gate Modulation */
{ 0x00, 1, 0 },
{ 0xf2, 0, 0 }, /* CR/EQ/PC */
{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
{ 0xeb, 0, 0 }, /* ? */
{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
{ 0xe0, 0, 0 }, /* Positive Gamma Control */
{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
{ 0xe1, 0, 0 }, /* Negative Gamma Control */
{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
{ 0xc1, 0, 0 }, /* Power Control 1 */
{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
{ 0xc7, 0, 0 }, /* VCOM Control */
{ 0x90, 1, 0 },
{ 0xb1, 0, 0 }, /* Frame Rate Control */
{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
{ 0xb4, 0, 0 }, /* Display Inversion Control */
{ 0x02, 1, 0 },
{ 0xbb, 0, 0 }, /* ? */
{ 0x14, 1, 0 }, { 0x55, 1, 0 },
{ 0x3a, 0, 0 }, /* Interface Pixel Format */
{ 0x55, 1, 0 },
{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
{ 0x00, 1, 0 }, { 0x00, 1, 0 },
{ 0x35, 0, 0 }, /* Tearing Effect Line On */
{ 0x00, 1, 0 },
};
static lcd_regs_t regs_late[] = {
{ 0x11, 0, 120 }, /* Sleep Out */
{ 0x29, 0, 20 }, /* Display On */
{ 0x2a, 0, 0 }, /* Column Address Set */
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
{ 0x2b, 0, 0 }, /* Page Address Set */
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
{ 0x2c, 0, 0 }, /* Memory Write*/
};
static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
const unsigned int timeout = 0x10000;
if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, timeout))
if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
timeout))
return -ETIMEDOUT;
writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
&regs->hw_lcdif_transfer_count);
writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
@ -94,8 +35,7 @@ static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
timeout))
if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29, timeout))
return -ETIMEDOUT;
writel(payload, &regs->hw_lcdif_data);
@ -106,7 +46,8 @@ static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
void mxsfb_system_setup(void)
{
struct mxs_lcdif_regs *lcdif = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
struct mxs_clkctrl_regs *xtal = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_clkctrl_regs *xtal =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_pwm_regs *pwm = (struct mxs_pwm_regs *)MXS_PWM_BASE;
int i, j;
uint32_t valid_data;
@ -114,20 +55,22 @@ void mxsfb_system_setup(void)
uint8_t ili9805_mac = 0;
lcd_config_t config = get_lcd_config();
valid_data = readl(&lcdif->hw_lcdif_ctrl1) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
valid_data = readl(&lcdif->hw_lcdif_ctrl1) &
LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
&lcdif->hw_lcdif_ctrl1);
&lcdif->hw_lcdif_ctrl1);
/* Switch the LCDIF into System-Mode */
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
LCDIF_CTRL_BYPASS_COUNT, &lcdif->hw_lcdif_ctrl_clr);
LCDIF_CTRL_BYPASS_COUNT,
&lcdif->hw_lcdif_ctrl_clr);
writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
writel((0x01 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
&lcdif->hw_lcdif_timing);
/* Enable LCD Controller */
@ -158,11 +101,11 @@ void mxsfb_system_setup(void)
ili9805_mac |= 1 << ILI9805_MAC_BGR_OFFSET;
}
mxsfb_write_byte(0x36, 0); /* Memory Access Control */
mxsfb_write_byte(0x36, 0); /* Memory Access Control */
mxsfb_write_byte(ili9805_mac, 1);
if (config.inversion) {
mxsfb_write_byte(0x21, 0); /* Display Inversion On */
mxsfb_write_byte(0x21, 0); /* Display Inversion On */
}
for (i = 0; i < ARRAY_SIZE(regs_late); i++) {
@ -189,24 +132,30 @@ void mxsfb_system_setup(void)
writel(PWM_CTRL_SFTRST, &pwm->hw_pwm_ctrl_clr);
writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_clr);
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE,
&pwm->hw_pwm_ctrl_clr);
writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET), &pwm->hw_pwm_active0_set);
(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET),
&pwm->hw_pwm_active0_set);
writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET), &pwm->hw_pwm_active1_set);
(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET),
&pwm->hw_pwm_active1_set);
writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET), &pwm->hw_pwm_period0_set);
(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET),
&pwm->hw_pwm_period0_set);
writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
(0x07cf << PWM_PERIOD1_PERIOD_OFFSET), &pwm->hw_pwm_period1_set);
(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
(0x07cf << PWM_PERIOD1_PERIOD_OFFSET),
&pwm->hw_pwm_period1_set);
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_set);
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE,
&pwm->hw_pwm_ctrl_set);
}
#endif

96
board/sharp/common/lcd.h
View File

@ -3,18 +3,12 @@
#ifndef __BRAIN_LCD_H__
#define __BRAIN_LCD_H__
typedef struct {
uint32_t payload;
unsigned int data;
uint32_t delay;
} lcd_regs_t;
typedef struct {
int flip_x;
int flip_y;
int transpose;
int inversion;
int bgr;
int inversion;
int bgr;
} lcd_config_t;
lcd_config_t get_lcd_config(void);
@ -22,13 +16,83 @@ lcd_config_t get_lcd_config(void);
#define ILI9805_ENABLE 1
#define ILI9805_DISABLE 0
#define ILI9805_MAC_GS_OFFSET 0 /* Flip Vertical */
#define ILI9805_MAC_SS_OFFSET 1 /* Flip Horizontal */
#define ILI9805_MAC_MH_OFFSET 2 /* Horizontal Refresh Order (h direction) */
#define ILI9805_MAC_BGR_OFFSET 3 /* RGB-BGR Order */
#define ILI9805_MAC_ML_OFFSET 4 /* Vertical Refresh Order (v direction) */
#define ILI9805_MAC_MV_OFFSET 5 /* Row/Column Exchange */
#define ILI9805_MAC_MX_OFFSET 6 /* Column Address Order */
#define ILI9805_MAC_MY_OFFSET 7 /* Row Address Order */
#define ILI9805_MAC_GS_OFFSET 0 /* Flip Vertical */
#define ILI9805_MAC_SS_OFFSET 1 /* Flip Horizontal */
#define ILI9805_MAC_MH_OFFSET 2 /* Horizontal Refresh Order (h direction) */
#define ILI9805_MAC_BGR_OFFSET 3 /* RGB-BGR Order */
#define ILI9805_MAC_ML_OFFSET 4 /* Vertical Refresh Order (v direction) */
#define ILI9805_MAC_MV_OFFSET 5 /* Row/Column Exchange */
#define ILI9805_MAC_MX_OFFSET 6 /* Column Address Order */
#define ILI9805_MAC_MY_OFFSET 7 /* Row Address Order */
typedef struct {
uint32_t payload;
unsigned int data;
uint32_t delay;
} lcd_regs_t;
/* clang-format off */
const static lcd_regs_t regs_early[] = {
{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
{ 0xfd, 0, 0 }, /* PFM Type C */
{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
{ 0xf8, 0, 0 }, /* PFM Type C */
{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
{ 0x72, 1, 0 },
{ 0xf1, 0, 0 }, /* Gate Modulation */
{ 0x00, 1, 0 },
{ 0xf2, 0, 0 }, /* CR/EQ/PC */
{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
{ 0xeb, 0, 0 }, /* ? */
{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
{ 0xe0, 0, 0 }, /* Positive Gamma Control */
{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
{ 0xe1, 0, 0 }, /* Negative Gamma Control */
{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
{ 0xc1, 0, 0 }, /* Power Control 1 */
{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
{ 0xc7, 0, 0 }, /* VCOM Control */
{ 0x90, 1, 0 },
{ 0xb1, 0, 0 }, /* Frame Rate Control */
{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
{ 0xb4, 0, 0 }, /* Display Inversion Control */
{ 0x02, 1, 0 },
{ 0xbb, 0, 0 }, /* ? */
{ 0x14, 1, 0 }, { 0x55, 1, 0 },
{ 0x3a, 0, 0 }, /* Interface Pixel Format */
{ 0x55, 1, 0 },
{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
{ 0x00, 1, 0 }, { 0x00, 1, 0 },
{ 0x35, 0, 0 }, /* Tearing Effect Line On */
{ 0x00, 1, 0 },
};
const static lcd_regs_t regs_late[] = {
{ 0x11, 0, 120 }, /* Sleep Out */
{ 0x29, 0, 20 }, /* Display On */
{ 0x2a, 0, 0 }, /* Column Address Set */
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
{ 0x2b, 0, 0 }, /* Page Address Set */
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
{ 0x2c, 0, 0 }, /* Memory Write*/
};
/* clang-format on */
#endif

372
board/sharp/pwsh1/iomux.c
View File

@ -14,208 +14,210 @@
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_LCD (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_LCD (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
///* MMC0 */
MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SSP0_SCK__SSP0_SCK |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* write protect */
//MX28_PAD_SSP1_SCK__GPIO_2_12,
/* eMMC power enable */
MX28_PAD_PWM3__GPIO_3_28 |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
///* MMC0 */
MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SSP0_SCK__SSP0_SCK |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* write protect */
//MX28_PAD_SSP1_SCK__GPIO_2_12,
/* eMMC power enable */
MX28_PAD_PWM3__GPIO_3_28 |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
/* MMC1 */
MX28_PAD_GPMI_D00__SSP1_D0 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D01__SSP1_D1 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D02__SSP1_D2 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D03__SSP1_D3 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_RDY1__SSP1_CMD | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_GPMI_WRN__SSP1_SCK |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* SD slot power enable */
MX28_PAD_SSP2_SS2__GPIO_2_21 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* MMC1 */
MX28_PAD_GPMI_D00__SSP1_D0 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D01__SSP1_D1 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D02__SSP1_D2 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_D03__SSP1_D3 | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_RDY1__SSP1_CMD | MUX_CONFIG_SSP1,
MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_GPMI_WRN__SSP1_SCK |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* SD slot power enable */
MX28_PAD_SSP2_SS2__GPIO_2_21 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* USB */
//MX28_PAD_GPMI_RDY0__USB0_ID,
/* USB */
//MX28_PAD_GPMI_RDY0__USB0_ID,
MX28_PAD_ENET0_COL__GPIO_4_14 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD1__GPIO_4_8 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD0__GPIO_4_7 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TX_EN__GPIO_4_6 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RX_EN__GPIO_4_2| MUX_CONFIG_GPIO,
MX28_PAD_ENET0_MDIO__GPIO_4_1 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_MDC__GPIO_4_0 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_COL__GPIO_4_14 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MX28_PAD_ENET0_TXD3__GPIO_4_12 |
MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD1__GPIO_4_8 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TXD0__GPIO_4_7 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TX_EN__GPIO_4_6 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MX28_PAD_ENET0_RXD1__GPIO_4_4 |
MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_MDIO__GPIO_4_1 | MUX_CONFIG_GPIO,
MX28_PAD_ENET0_MDC__GPIO_4_0 | MUX_CONFIG_GPIO,
/* EMI */
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
/* EMI */
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
/* SPI2 (for SPI flash) */
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
/* I2C */
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
MX28_PAD_PWM1__I2C1_SDA,
MX28_PAD_PWM0__I2C1_SCL,
/* SPI2 (for SPI flash) */
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
/* I2C */
MX28_PAD_I2C0_SCL__I2C0_SCL,
MX28_PAD_I2C0_SDA__I2C0_SDA,
MX28_PAD_PWM1__I2C1_SDA,
MX28_PAD_PWM0__I2C1_SCL,
MX28_PAD_AUART0_RTS__DUART_TX, // TP302
MX28_PAD_AUART0_CTS__DUART_RX, // TP301
MX28_PAD_AUART0_RTS__DUART_TX, // TP302
MX28_PAD_AUART0_CTS__DUART_RX, // TP301
/* LCD */
MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
MX28_PAD_LCD_RD_E__LCD_RD_E | MUX_CONFIG_LCD,
MX28_PAD_LCD_WR_RWN__LCD_WR_RWN | MUX_CONFIG_LCD,
MX28_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
MX28_PAD_LCD_RESET__LCD_VSYNC | MUX_CONFIG_LCD,
/* LCD */
MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
MX28_PAD_LCD_RD_E__LCD_RD_E | MUX_CONFIG_LCD,
MX28_PAD_LCD_WR_RWN__LCD_WR_RWN | MUX_CONFIG_LCD,
MX28_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
MX28_PAD_LCD_RESET__LCD_VSYNC | MUX_CONFIG_LCD,
/* Regulator EN? */
MX28_PAD_GPMI_ALE__GPIO_0_26 | (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL),
MX28_PAD_GPMI_CLE__GPIO_0_27 | (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
/* Regulator EN? */
MX28_PAD_GPMI_ALE__GPIO_0_26 |
(MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL),
MX28_PAD_GPMI_CLE__GPIO_0_27 |
(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
/* ILI9805 Reset? */
MX28_PAD_ENET_CLK__GPIO_4_16 | MUX_CONFIG_LCD,
/* ILI9805 Reset? */
MX28_PAD_ENET_CLK__GPIO_4_16 | MUX_CONFIG_LCD,
/* GPIO */
MX28_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D18__GPIO_1_18 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D19__GPIO_1_19 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D20__GPIO_1_20 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D21__GPIO_1_21 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D22__GPIO_1_22 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D23__GPIO_1_23 | MUX_CONFIG_GPIO,
MX28_PAD_SSP2_MISO__GPIO_2_18 | MUX_CONFIG_GPIO,
MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
MX28_PAD_SPDIF__GPIO_3_27 | MUX_CONFIG_GPIO,
MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_GPIO,
MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_GPIO,
/* GPIO */
MX28_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D18__GPIO_1_18 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D19__GPIO_1_19 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D20__GPIO_1_20 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D21__GPIO_1_21 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D22__GPIO_1_22 | MUX_CONFIG_GPIO,
MX28_PAD_LCD_D23__GPIO_1_23 | MUX_CONFIG_GPIO,
MX28_PAD_SSP2_MISO__GPIO_2_18 | MUX_CONFIG_GPIO,
MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
MX28_PAD_SPDIF__GPIO_3_27 | MUX_CONFIG_GPIO,
MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_GPIO,
MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_GPIO,
/* PWM */
MX28_PAD_AUART1_RX__PWM_0 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_AUART1_TX__PWM_1 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* PWM */
MX28_PAD_AUART1_RX__PWM_0 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_AUART1_TX__PWM_1 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* SAIF */
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
/* SAIF */
MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
#define HW_DRAM_CTL29 (0x74 >> 2)
#define CS_MAP 0x1
#define COLUMN_SIZE 0x2
#define ADDR_PINS 0x1
#define APREBIT 0xa
#define HW_DRAM_CTL29 (0x74 >> 2)
#define CS_MAP 0x1
#define COLUMN_SIZE 0x2
#define ADDR_PINS 0x1
#define APREBIT 0xa
#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
ADDR_PINS << 8 | APREBIT)
#define HW_DRAM_CTL29_CONFIG \
(CS_MAP << 24 | COLUMN_SIZE << 16 | ADDR_PINS << 8 | APREBIT)
void mxs_adjust_memory_params(uint32_t *dram_vals)
{

12
board/sharp/pwsh1/pwsh1.c
View File

@ -44,10 +44,10 @@ int board_early_init_f(void)
/* SSP1 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK1, 96000, 0);
#ifdef CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 | MXS_PAD_4MA |
MXS_PAD_3V3 | MXS_PAD_NOPULL);
gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
#endif
@ -68,7 +68,7 @@ int board_init(void)
return 0;
}
#ifdef CONFIG_CMD_MMC
#ifdef CONFIG_CMD_MMC
static int brain_mmc_wp(int id)
{
return 0;
@ -95,8 +95,8 @@ static const lcd_config_t lcd_config = {
.flip_x = ILI9805_DISABLE,
.flip_y = ILI9805_DISABLE,
.transpose = ILI9805_ENABLE,
.inversion = ILI9805_ENABLE,
.bgr = ILI9805_ENABLE,
.inversion = ILI9805_ENABLE,
.bgr = ILI9805_ENABLE,
};
lcd_config_t get_lcd_config()