sharp: split LCD init code into board-specific part and common part
This commit is contained in:
Takumi Sueda
Suguru Saito
parent
0b23ec198c
commit
662e02ec58
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@ -0,0 +1,5 @@
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ifdef CONFIG_VIDEO_MXS
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obj-$(CONFIG_VIDEO_MXS) += lcd.o
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else
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obj- = __dummy__.o
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endif
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@ -0,0 +1,212 @@
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
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#include <errno.h>
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#include "lcd.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_VIDEO_MXS
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static lcd_regs_t regs_early[] = {
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{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
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{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
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{ 0xfd, 0, 0 }, /* PFM Type C */
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{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
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{ 0xf8, 0, 0 }, /* PFM Type C */
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{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
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{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
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{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
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{ 0x72, 1, 0 },
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{ 0xf1, 0, 0 }, /* Gate Modulation */
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{ 0x00, 1, 0 },
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{ 0xf2, 0, 0 }, /* CR/EQ/PC */
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{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
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{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
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{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
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{ 0xeb, 0, 0 }, /* ? */
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{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
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{ 0xe0, 0, 0 }, /* Positive Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
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{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
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{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xe1, 0, 0 }, /* Negative Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
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{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xc1, 0, 0 }, /* Power Control 1 */
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{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
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{ 0xc7, 0, 0 }, /* VCOM Control */
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{ 0x90, 1, 0 },
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{ 0xb1, 0, 0 }, /* Frame Rate Control */
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{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
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{ 0xb4, 0, 0 }, /* Display Inversion Control */
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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};
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static lcd_regs_t regs_late[] = {
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
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{ 0x2a, 0, 0 }, /* Column Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
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{ 0x2b, 0, 0 }, /* Page Address Set */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
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{ 0x2c, 0, 0 }, /* Memory Write*/
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};
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static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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const unsigned int timeout = 0x10000;
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, timeout))
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return -ETIMEDOUT;
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writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
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(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
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®s->hw_lcdif_transfer_count);
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writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
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®s->hw_lcdif_ctrl_clr);
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if (data)
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writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
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timeout))
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return -ETIMEDOUT;
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writel(payload, ®s->hw_lcdif_data);
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return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout);
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}
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void mxsfb_system_setup(void)
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{
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struct mxs_lcdif_regs *lcdif = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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struct mxs_clkctrl_regs *xtal = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct mxs_pwm_regs *pwm = (struct mxs_pwm_regs *)MXS_PWM_BASE;
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int i, j;
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uint32_t valid_data;
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uint8_t ili9805_mac = 0;
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lcd_config_t config = get_lcd_config();
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valid_data = readl(&lcdif->hw_lcdif_ctrl1) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
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writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
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&lcdif->hw_lcdif_ctrl1);
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/* Switch the LCDIF into System-Mode */
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
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LCDIF_CTRL_BYPASS_COUNT, &lcdif->hw_lcdif_ctrl_clr);
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writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
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writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
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writel((0x01 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
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&lcdif->hw_lcdif_timing);
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/* Enable LCD Controller */
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gpio_direction_output(MX28_PAD_GPMI_ALE__GPIO_0_26, 1);
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gpio_direction_output(MX28_PAD_GPMI_CLE__GPIO_0_27, 1);
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gpio_direction_output(MX28_PAD_ENET_CLK__GPIO_4_16, 1);
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mdelay(20);
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for (i = 0; i < ARRAY_SIZE(regs_early); i++) {
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mxsfb_write_byte(regs_early[i].payload, regs_early[i].data);
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if (regs_early[i].delay)
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mdelay(regs_early[i].delay);
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}
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if (config.flip_x) {
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ili9805_mac |= 1 << ILI9805_MAC_MX_OFFSET;
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}
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if (config.flip_y) {
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ili9805_mac |= 1 << ILI9805_MAC_MY_OFFSET;
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}
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if (config.transpose) {
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ili9805_mac |= 1 << ILI9805_MAC_MV_OFFSET;
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}
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if (config.bgr) {
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ili9805_mac |= 1 << ILI9805_MAC_BGR_OFFSET;
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}
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mxsfb_write_byte(0x36, 0); /* Memory Access Control */
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mxsfb_write_byte(ili9805_mac, 1);
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if (config.inversion) {
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mxsfb_write_byte(0x21, 0); /* Display Inversion On */
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}
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for (i = 0; i < ARRAY_SIZE(regs_late); i++) {
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mxsfb_write_byte(regs_late[i].payload, regs_late[i].data);
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if (regs_late[i].delay)
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mdelay(regs_late[i].delay);
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}
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/* Fill black */
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for (i = 0; i < 480; i++) {
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for (j = 0; j < 800; j++) {
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mxsfb_write_byte(0, 1);
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}
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}
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writel(valid_data, &lcdif->hw_lcdif_ctrl1);
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
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&lcdif->hw_lcdif_ctrl_set);
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/* Turn on backlight */
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writel(CLKCTRL_XTAL_PWM_CLK24M_GATE, &xtal->hw_clkctrl_xtal_clr);
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mdelay(1);
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writel(PWM_CTRL_SFTRST, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_clr);
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writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET), &pwm->hw_pwm_active0_set);
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writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET), &pwm->hw_pwm_active1_set);
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writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
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(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
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(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET), &pwm->hw_pwm_period0_set);
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writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
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(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
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(0x07cf << PWM_PERIOD1_PERIOD_OFFSET), &pwm->hw_pwm_period1_set);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_set);
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}
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#endif
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@ -0,0 +1,34 @@
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#include <common.h>
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#ifndef __BRAIN_LCD_H__
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#define __BRAIN_LCD_H__
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typedef struct {
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uint32_t payload;
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unsigned int data;
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uint32_t delay;
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} lcd_regs_t;
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typedef struct {
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int flip_x;
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int flip_y;
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int transpose;
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int inversion;
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int bgr;
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} lcd_config_t;
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lcd_config_t get_lcd_config(void);
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#define ILI9805_ENABLE 1
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#define ILI9805_DISABLE 0
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#define ILI9805_MAC_GS_OFFSET 0 /* Flip Vertical */
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#define ILI9805_MAC_SS_OFFSET 1 /* Flip Horizontal */
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#define ILI9805_MAC_MH_OFFSET 2 /* Horizontal Refresh Order (h direction) */
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#define ILI9805_MAC_BGR_OFFSET 3 /* RGB-BGR Order */
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#define ILI9805_MAC_ML_OFFSET 4 /* Vertical Refresh Order (v direction) */
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#define ILI9805_MAC_MV_OFFSET 5 /* Row/Column Exchange */
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#define ILI9805_MAC_MX_OFFSET 6 /* Column Address Order */
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#define ILI9805_MAC_MY_OFFSET 7 /* Row Address Order */
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#endif
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@ -25,6 +25,8 @@
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#include <netdev.h>
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#include <errno.h>
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#include "../common/lcd.h"
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DECLARE_GLOBAL_DATA_PTR;
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/*
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@ -89,173 +91,16 @@ int board_mmc_init(bd_t *bis)
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#endif
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#ifdef CONFIG_VIDEO_MXS
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static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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{
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struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
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const unsigned int timeout = 0x10000;
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, timeout))
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return -ETIMEDOUT;
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writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
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(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
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®s->hw_lcdif_transfer_count);
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writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
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®s->hw_lcdif_ctrl_clr);
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if (data)
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writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
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writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
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if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
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timeout))
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return -ETIMEDOUT;
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writel(payload, ®s->hw_lcdif_data);
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return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout);
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}
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/* https://github.com/muojie/spec_mtk/blob/master/MTK_driver/spec/LCM/ILI9805/ILI9805_AN_V0.4_20120330.pdf */
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static const struct {
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uint32_t payload;
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unsigned int data;
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uint32_t delay;
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} lcd_regs[] = {
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{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
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{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
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{ 0xfd, 0, 0 }, /* PFM Type C */
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{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
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{ 0xf8, 0, 0 }, /* PFM Type C */
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{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
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{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
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{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
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{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
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{ 0x72, 1, 0 },
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{ 0xf1, 0, 0 }, /* Gate Modulation */
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{ 0x00, 1, 0 },
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{ 0xf2, 0, 0 }, /* CR/EQ/PC */
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{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
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{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
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{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
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{ 0xeb, 0, 0 }, /* ? */
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{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
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{ 0xe0, 0, 0 }, /* Positive Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
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{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
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{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xe1, 0, 0 }, /* Negative Gamma Control */
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{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
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{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
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{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
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{ 0xc1, 0, 0 }, /* Power Control 1 */
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{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
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{ 0xc7, 0, 0 }, /* VCOM Control */
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{ 0x90, 1, 0 },
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{ 0xb1, 0, 0 }, /* Frame Rate Control */
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{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
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{ 0xb4, 0, 0 }, /* Display Inversion Control */
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{ 0x02, 1, 0 },
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{ 0xbb, 0, 0 }, /* ? */
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{ 0x14, 1, 0 }, { 0x55, 1, 0 },
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{ 0x36, 0, 0 }, /* Memory Access Control */
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{ 0x28, 1, 0 },
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{ 0x3a, 0, 0 }, /* Interface Pixel Format */
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{ 0x55, 1, 0 },
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{ 0x21, 0, 0 }, /* Display Inversion On */
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{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
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{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
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{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
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{ 0x00, 1, 0 }, { 0x00, 1, 0 },
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{ 0x35, 0, 0 }, /* Tearing Effect Line On */
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{ 0x00, 1, 0 },
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{ 0x11, 0, 120 }, /* Sleep Out */
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{ 0x29, 0, 20 }, /* Display On */
|
||||
{ 0x2a, 0, 0 }, /* Column Address Set */
|
||||
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
|
||||
{ 0x2b, 0, 0 }, /* Page Address Set */
|
||||
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
|
||||
{ 0x2c, 0, 0 }, /* Memory Write*/
|
||||
static const lcd_config_t lcd_config = {
|
||||
.flip_x = ILI9805_DISABLE,
|
||||
.flip_y = ILI9805_DISABLE,
|
||||
.transpose = ILI9805_ENABLE,
|
||||
.inversion = ILI9805_ENABLE,
|
||||
.bgr = ILI9805_ENABLE,
|
||||
};
|
||||
|
||||
void mxsfb_system_setup(void)
|
||||
lcd_config_t get_lcd_config()
|
||||
{
|
||||
struct mxs_lcdif_regs *lcdif = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
|
||||
struct mxs_clkctrl_regs *xtal = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
struct mxs_pwm_regs *pwm = (struct mxs_pwm_regs *)MXS_PWM_BASE;
|
||||
int i, j;
|
||||
uint32_t valid_data;
|
||||
|
||||
valid_data = readl(&lcdif->hw_lcdif_ctrl1) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
|
||||
writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
|
||||
&lcdif->hw_lcdif_ctrl1);
|
||||
|
||||
/* Switch the LCDIF into System-Mode */
|
||||
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
|
||||
LCDIF_CTRL_BYPASS_COUNT, &lcdif->hw_lcdif_ctrl_clr);
|
||||
writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
|
||||
writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
|
||||
|
||||
writel((0x01 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
|
||||
(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
|
||||
(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
|
||||
(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
|
||||
&lcdif->hw_lcdif_timing);
|
||||
|
||||
/* Enable LCD Controller */
|
||||
gpio_direction_output(MX28_PAD_GPMI_ALE__GPIO_0_26, 1);
|
||||
gpio_direction_output(MX28_PAD_GPMI_CLE__GPIO_0_27, 1);
|
||||
gpio_direction_output(MX28_PAD_ENET_CLK__GPIO_4_16, 1);
|
||||
mdelay(20);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
|
||||
mxsfb_write_byte(lcd_regs[i].payload, lcd_regs[i].data);
|
||||
if (lcd_regs[i].delay)
|
||||
mdelay(lcd_regs[i].delay);
|
||||
}
|
||||
|
||||
/* Fill black */
|
||||
for (i = 0; i < 480; i++) {
|
||||
for (j = 0; j < 800; j++) {
|
||||
mxsfb_write_byte(0, 1);
|
||||
}
|
||||
}
|
||||
|
||||
writel(valid_data, &lcdif->hw_lcdif_ctrl1);
|
||||
|
||||
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
|
||||
&lcdif->hw_lcdif_ctrl_set);
|
||||
|
||||
/* Turn on backlight */
|
||||
writel(CLKCTRL_XTAL_PWM_CLK24M_GATE, &xtal->hw_clkctrl_xtal_clr);
|
||||
mdelay(1);
|
||||
writel(PWM_CTRL_SFTRST, &pwm->hw_pwm_ctrl_clr);
|
||||
writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
|
||||
|
||||
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_clr);
|
||||
|
||||
writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
|
||||
(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET), &pwm->hw_pwm_active0_set);
|
||||
|
||||
writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
|
||||
(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET), &pwm->hw_pwm_active1_set);
|
||||
|
||||
writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
|
||||
(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
|
||||
(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
|
||||
(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET), &pwm->hw_pwm_period0_set);
|
||||
|
||||
writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
|
||||
(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
|
||||
(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
|
||||
(0x07cf << PWM_PERIOD1_PERIOD_OFFSET), &pwm->hw_pwm_period1_set);
|
||||
|
||||
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_set);
|
||||
return lcd_config;
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue