mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
Merge git://git.denx.de/u-boot-fsl-qoriq
- DPAA2 fixes and DDR errata workaround for LS1021A
This commit is contained in:
commit
8303467e80
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@ -4,6 +4,7 @@ config ARCH_LS1021A
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008850
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_ERRATUM_A009007
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select SYS_FSL_ERRATUM_A009008
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select SYS_FSL_ERRATUM_A009008
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@ -63,6 +64,11 @@ config SYS_CCI400_OFFSET
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Offset for CCI400 base.
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Offset for CCI400 base.
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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config SYS_FSL_ERRATUM_A008850
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bool
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help
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Workaround for DDR erratum A008850
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config SYS_FSL_ERRATUM_A008997
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config SYS_FSL_ERRATUM_A008997
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bool
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bool
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help
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help
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@ -11,6 +11,7 @@
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <fsl_csu.h>
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#include <fsl_csu.h>
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#include <fsl_ddr_sdram.h>
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struct liodn_id_table sec_liodn_tbl[] = {
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
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SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
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@ -103,6 +104,41 @@ static void erratum_a009007(void)
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
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}
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}
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static void erratum_a008850_early(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
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/* part 1 of 2 */
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struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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/* disables propagation of barrier transactions to DDRC from CCI400 */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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/* disable the re-ordering in DDRC */
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out_be32(&ddr->eor, DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
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#endif
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}
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void erratum_a008850_post(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008850
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/* part 2 of 2 */
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struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
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u32 tmp;
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/* enable propagation of barrier transactions to DDRC from CCI400 */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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/* enable the re-ordering in DDRC */
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tmp = in_be32(&ddr->eor);
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tmp &= ~(DDR_EOR_RD_REOD_DIS | DDR_EOR_WD_REOD_DIS);
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out_be32(&ddr->eor, tmp);
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#endif
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}
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void s_init(void)
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void s_init(void)
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{
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{
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}
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}
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@ -163,13 +199,6 @@ int arch_soc_init(void)
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*/
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*/
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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/* Workaround for the issue that DDR could not respond to
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* barrier transaction which is generated by executing DSB/ISB
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* instruction. Set CCI-400 control override register to
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* terminate the barrier transaction. After DDR is initialized,
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* allow barrier transaction to DDR again */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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}
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}
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/* Enable all the snoop signal for various masters */
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/* Enable all the snoop signal for various masters */
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@ -191,6 +220,7 @@ int arch_soc_init(void)
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out_be32(&scfg->eddrtqcfg, 0x63b20042);
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out_be32(&scfg->eddrtqcfg, 0x63b20042);
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/* Erratum */
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/* Erratum */
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erratum_a008850_early();
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erratum_a009008();
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erratum_a009008();
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erratum_a009798();
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erratum_a009798();
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erratum_a008997();
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erratum_a008997();
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@ -10,6 +10,8 @@ unsigned int get_soc_major_rev(void);
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int arch_soc_init(void);
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int arch_soc_init(void);
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int ls102xa_smmu_stream_id_init(void);
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int ls102xa_smmu_stream_id_init(void);
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void erratum_a008850_post(void);
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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void erratum_a010315(void);
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void erratum_a010315(void);
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#endif
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#endif
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@ -97,6 +97,8 @@ int dram_init(void)
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ddrmc_init();
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ddrmc_init();
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#endif
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#endif
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erratum_a008850_post();
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gd->ram_size = DDR_SIZE;
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gd->ram_size = DDR_SIZE;
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return 0;
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return 0;
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}
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}
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@ -179,6 +179,8 @@ int fsl_initdram(void)
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fsl_dp_resume();
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fsl_dp_resume();
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#endif
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#endif
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erratum_a008850_post();
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gd->ram_size = dram_size;
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gd->ram_size = dram_size;
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return 0;
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return 0;
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@ -5,6 +5,9 @@
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#ifndef __DDR_H__
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#ifndef __DDR_H__
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#define __DDR_H__
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#define __DDR_H__
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void erratum_a008850_post(void);
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struct board_specific_parameters {
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struct board_specific_parameters {
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u32 n_ranks;
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 datarate_mhz_high;
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@ -200,10 +200,6 @@ int board_early_init_f(void)
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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void board_init_f(ulong dummy)
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{
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
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#ifdef CONFIG_NAND_BOOT
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#ifdef CONFIG_NAND_BOOT
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 porsr1, pinctl;
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u32 porsr1, pinctl;
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@ -240,10 +236,6 @@ void board_init_f(ulong dummy)
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i2c_init_all();
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i2c_init_all();
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#endif
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#endif
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0)
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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timer_init();
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timer_init();
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dram_init();
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dram_init();
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@ -420,22 +412,12 @@ int misc_init_r(void)
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int board_init(void)
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int board_init(void)
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{
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{
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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erratum_a010315();
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erratum_a010315();
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#endif
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
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erratum_a009942_check_cpo();
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erratum_a009942_check_cpo();
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#endif
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#endif
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/* Set CCI-400 control override register to
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* enable barrier transaction */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
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}
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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@ -456,18 +438,6 @@ int board_init(void)
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#if defined(CONFIG_DEEP_SLEEP)
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#if defined(CONFIG_DEEP_SLEEP)
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void board_sleep_prepare(void)
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void board_sleep_prepare(void)
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{
|
{
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struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
|
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/* Set CCI-400 control override register to
|
|
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* enable barrier transaction */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
|
|
||||||
}
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||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
|
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
|
||||||
enable_layerscape_ns_access();
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enable_layerscape_ns_access();
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -222,6 +222,8 @@ int dram_init(void)
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||||||
ddrmc_init();
|
ddrmc_init();
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
erratum_a008850_post();
|
||||||
|
|
||||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||||
|
|
||||||
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
|
#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
|
||||||
|
|
|
@ -628,8 +628,9 @@ int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
|
||||||
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
||||||
{
|
{
|
||||||
char mdio_ioslot_str[] = "mdio@00";
|
char mdio_ioslot_str[] = "mdio@00";
|
||||||
char mdio_mux_str[] = "mdio-mux-0";
|
|
||||||
struct lx2160a_qds_mdio *priv;
|
struct lx2160a_qds_mdio *priv;
|
||||||
|
u64 reg;
|
||||||
|
u32 phandle;
|
||||||
int offset, mux_val;
|
int offset, mux_val;
|
||||||
|
|
||||||
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
|
/*Test if the MDIO bus is real mdio bus or muxing front end ?*/
|
||||||
|
@ -643,15 +644,32 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
|
||||||
debug("real_bus_num = %d, ioslot = %d\n",
|
debug("real_bus_num = %d, ioslot = %d\n",
|
||||||
priv->realbusnum, priv->ioslot);
|
priv->realbusnum, priv->ioslot);
|
||||||
|
|
||||||
sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
|
if (priv->realbusnum == EMI1)
|
||||||
offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
|
reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
|
||||||
|
else
|
||||||
|
reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
|
||||||
|
|
||||||
|
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
|
||||||
if (offset < 0) {
|
if (offset < 0) {
|
||||||
printf("%s node not found under node %s in device tree\n",
|
printf("mdio@%llx node not found in device tree\n", reg);
|
||||||
mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
|
return offset;
|
||||||
|
}
|
||||||
|
|
||||||
|
phandle = fdt_get_phandle(fdt, offset);
|
||||||
|
phandle = cpu_to_fdt32(phandle);
|
||||||
|
offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
|
||||||
|
&phandle, 4);
|
||||||
|
if (offset < 0) {
|
||||||
|
printf("mdio-mux-%d node not found in device tree\n",
|
||||||
|
priv->realbusnum == EMI1 ? 1 : 2);
|
||||||
return offset;
|
return offset;
|
||||||
}
|
}
|
||||||
|
|
||||||
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
|
||||||
|
if (priv->realbusnum == EMI1)
|
||||||
|
mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
|
||||||
|
else
|
||||||
|
mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
|
||||||
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
|
sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
|
||||||
|
|
||||||
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
|
offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
|
||||||
|
@ -675,7 +693,9 @@ int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
|
||||||
|
|
||||||
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
|
*subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
|
||||||
if (*subnodeoffset <= 0) {
|
if (*subnodeoffset <= 0) {
|
||||||
printf("Could not add subnode %s\n", phy_node_name);
|
printf("Could not add subnode %s inside node %s err = %s\n",
|
||||||
|
phy_node_name, fdt_get_name(fdt, offset, NULL),
|
||||||
|
fdt_strerror(*subnodeoffset));
|
||||||
return *subnodeoffset;
|
return *subnodeoffset;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -779,7 +799,6 @@ int fdt_fixup_board_phy(void *fdt)
|
||||||
}
|
}
|
||||||
if (dpmac_id == NUM_WRIOP_PORTS)
|
if (dpmac_id == NUM_WRIOP_PORTS)
|
||||||
continue;
|
continue;
|
||||||
|
|
||||||
ret = fdt_create_phy_node(fdt, offset, i,
|
ret = fdt_create_phy_node(fdt, offset, i,
|
||||||
&subnodeoffset,
|
&subnodeoffset,
|
||||||
phy_dev, phandle);
|
phy_dev, phandle);
|
||||||
|
@ -792,6 +811,11 @@ int fdt_fixup_board_phy(void *fdt)
|
||||||
fdt_del_node(fdt, subnodeoffset);
|
fdt_del_node(fdt, subnodeoffset);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
/* calculate offset again as new node addition may have
|
||||||
|
* changed offset;
|
||||||
|
*/
|
||||||
|
offset = fdt_get_ioslot_offset(fdt, mii_dev,
|
||||||
|
fpga_offset);
|
||||||
phandle++;
|
phandle++;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -28,6 +28,7 @@
|
||||||
#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
|
#define MC_MEM_SIZE_ENV_VAR "mcmemsize"
|
||||||
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
|
#define MC_BOOT_TIMEOUT_ENV_VAR "mcboottimeout"
|
||||||
#define MC_BOOT_ENV_VAR "mcinitcmd"
|
#define MC_BOOT_ENV_VAR "mcinitcmd"
|
||||||
|
#define MC_DRAM_BLOCK_DEFAULT_SIZE (512UL * 1024 * 1024)
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
static int mc_memset_resv_ram;
|
static int mc_memset_resv_ram;
|
||||||
|
@ -421,9 +422,11 @@ static int mc_fixup_dpc(u64 dpc_addr)
|
||||||
/* fixup MAC addresses for dpmac ports */
|
/* fixup MAC addresses for dpmac ports */
|
||||||
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
|
nodeoffset = fdt_path_offset(blob, "/board_info/ports");
|
||||||
if (nodeoffset < 0)
|
if (nodeoffset < 0)
|
||||||
return 0;
|
goto out;
|
||||||
|
|
||||||
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
|
err = mc_fixup_mac_addrs(blob, MC_FIXUP_DPC);
|
||||||
|
|
||||||
|
out:
|
||||||
flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
|
flush_dcache_range(dpc_addr, dpc_addr + fdt_totalsize(blob));
|
||||||
|
|
||||||
return err;
|
return err;
|
||||||
|
@ -680,13 +683,20 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
|
||||||
size_t mc_ram_size = mc_get_dram_block_size();
|
size_t mc_ram_size = mc_get_dram_block_size();
|
||||||
|
|
||||||
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
|
mc_ram_num_256mb_blocks = mc_ram_size / MC_RAM_SIZE_ALIGNMENT;
|
||||||
if (mc_ram_num_256mb_blocks < 1 || mc_ram_num_256mb_blocks > 0xff) {
|
|
||||||
|
if (mc_ram_num_256mb_blocks >= 0xff) {
|
||||||
error = -EINVAL;
|
error = -EINVAL;
|
||||||
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
|
printf("fsl-mc: ERROR: invalid MC private RAM size (%lu)\n",
|
||||||
mc_ram_size);
|
mc_ram_size);
|
||||||
goto out;
|
goto out;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* To support 128 MB DDR Size for MC
|
||||||
|
*/
|
||||||
|
if (mc_ram_num_256mb_blocks == 0)
|
||||||
|
mc_ram_num_256mb_blocks = 0xFF;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Management Complex cores should be held at reset out of POR.
|
* Management Complex cores should be held at reset out of POR.
|
||||||
* U-Boot should be the first software to touch MC. To be safe,
|
* U-Boot should be the first software to touch MC. To be safe,
|
||||||
|
@ -727,8 +737,14 @@ int mc_init(u64 mc_fw_addr, u64 mc_dpc_addr)
|
||||||
/*
|
/*
|
||||||
* Tell MC what is the address range of the DRAM block assigned to it:
|
* Tell MC what is the address range of the DRAM block assigned to it:
|
||||||
*/
|
*/
|
||||||
reg_mcfbalr = (u32)mc_ram_addr |
|
if (mc_ram_num_256mb_blocks < 0xFF) {
|
||||||
(mc_ram_num_256mb_blocks - 1);
|
reg_mcfbalr = (u32)mc_ram_addr |
|
||||||
|
(mc_ram_num_256mb_blocks - 1);
|
||||||
|
} else {
|
||||||
|
reg_mcfbalr = (u32)mc_ram_addr |
|
||||||
|
(mc_ram_num_256mb_blocks);
|
||||||
|
}
|
||||||
|
|
||||||
out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
|
out_le32(&mc_ccsr_regs->reg_mcfbalr, reg_mcfbalr);
|
||||||
out_le32(&mc_ccsr_regs->reg_mcfbahr,
|
out_le32(&mc_ccsr_regs->reg_mcfbahr,
|
||||||
(u32)(mc_ram_addr >> 32));
|
(u32)(mc_ram_addr >> 32));
|
||||||
|
@ -878,7 +894,7 @@ unsigned long mc_get_dram_block_size(void)
|
||||||
"\' environment variable: %lu\n",
|
"\' environment variable: %lu\n",
|
||||||
dram_block_size);
|
dram_block_size);
|
||||||
|
|
||||||
dram_block_size = CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE;
|
dram_block_size = MC_DRAM_BLOCK_DEFAULT_SIZE;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -93,7 +93,7 @@ void fsl_rgmii_init(void)
|
||||||
u32 ec;
|
u32 ec;
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FSL_EC1
|
#ifdef CONFIG_SYS_FSL_EC1
|
||||||
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1])
|
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR])
|
||||||
& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
|
& FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK;
|
||||||
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
|
ec >>= FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT;
|
||||||
|
|
||||||
|
@ -102,7 +102,7 @@ void fsl_rgmii_init(void)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_FSL_EC2
|
#ifdef CONFIG_SYS_FSL_EC2
|
||||||
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1])
|
ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR])
|
||||||
& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
|
& FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK;
|
||||||
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
|
ec >>= FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT;
|
||||||
|
|
||||||
|
|
|
@ -91,7 +91,7 @@ void fsl_rgmii_init(void)
|
||||||
& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
|
& FSL_CHASSIS3_EC1_REGSR_PRTCL_MASK;
|
||||||
ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
|
ec >>= FSL_CHASSIS3_EC1_REGSR_PRTCL_SHIFT;
|
||||||
|
|
||||||
if (!ec)
|
if (!ec && (wriop_is_enabled_dpmac(17) == -ENODEV))
|
||||||
wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
|
wriop_init_dpmac_enet_if(17, PHY_INTERFACE_MODE_RGMII_ID);
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -100,7 +100,7 @@ void fsl_rgmii_init(void)
|
||||||
& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
|
& FSL_CHASSIS3_EC2_REGSR_PRTCL_MASK;
|
||||||
ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
|
ec >>= FSL_CHASSIS3_EC2_REGSR_PRTCL_SHIFT;
|
||||||
|
|
||||||
if (!ec)
|
if (!ec && (wriop_is_enabled_dpmac(18) == -ENODEV))
|
||||||
wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
|
wriop_init_dpmac_enet_if(18, PHY_INTERFACE_MODE_RGMII_ID);
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
|
@ -85,6 +85,8 @@
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||||
|
|
||||||
|
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Serial Port
|
* Serial Port
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -104,6 +104,8 @@
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||||
|
|
||||||
|
#define CONFIG_CHIP_SELECTS_PER_CTRL 4
|
||||||
|
|
||||||
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
|
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
|
||||||
!defined(CONFIG_QSPI_BOOT)
|
!defined(CONFIG_QSPI_BOOT)
|
||||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
|
||||||
|
|
|
@ -147,7 +147,7 @@ unsigned long long get_qixis_addr(void);
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#if defined(CONFIG_FSL_MC_ENET)
|
#if defined(CONFIG_FSL_MC_ENET)
|
||||||
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
|
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
|
||||||
#endif
|
#endif
|
||||||
/* Command line configuration */
|
/* Command line configuration */
|
||||||
#define CONFIG_CMD_CACHE
|
#define CONFIG_CMD_CACHE
|
||||||
|
|
|
@ -152,7 +152,7 @@ unsigned long long get_qixis_addr(void);
|
||||||
* 512MB aligned, so the min size to hide is 512MB.
|
* 512MB aligned, so the min size to hide is 512MB.
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_FSL_MC_ENET
|
#ifdef CONFIG_FSL_MC_ENET
|
||||||
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
|
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* Command line configuration */
|
/* Command line configuration */
|
||||||
|
|
|
@ -100,7 +100,7 @@
|
||||||
* 512MB aligned, so the min size to hide is 512MB.
|
* 512MB aligned, so the min size to hide is 512MB.
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_FSL_MC_ENET
|
#ifdef CONFIG_FSL_MC_ENET
|
||||||
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
|
#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* I2C bus multiplexer */
|
/* I2C bus multiplexer */
|
||||||
|
|
Loading…
Reference in New Issue
Block a user