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Changed MarelV38B board make target to lowercase. Config file cleanup.

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This commit is contained in:
Bartlomiej Sieka 2006-11-01 01:34:29 +01:00
parent d9831893ab
commit 82d9c9ec29
2 changed files with 84 additions and 109 deletions
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2
Makefile
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@ -412,7 +412,7 @@ icecube_5100_config: unconfig
@$(MKCONFIG) -a IceCube ppc mpc5xxx icecube @$(MKCONFIG) -a IceCube ppc mpc5xxx icecube
v38b_config: unconfig v38b_config: unconfig
@./mkconfig -a V38B ppc mpc5xxx v38b @./mkconfig -a v38b ppc mpc5xxx v38b
inka4x0_config: unconfig inka4x0_config: unconfig
@$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0 @$(MKCONFIG) inka4x0 ppc mpc5xxx inka4x0

191
include/configs/V38B.h → include/configs/v38b.h
View File

@ -1,5 +1,5 @@
/* /*
* (C) Copyright 2003-2004 Wolfgang Denk, DENX Software Engineering, * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
* wd@denx.de. * wd@denx.de.
* *
* See file CREDITS for list of people who contributed to this project. * See file CREDITS for list of people who contributed to this project.
@ -11,7 +11,7 @@
* *
* This program is distributed in the hope that it will be useful, but WITHOUT * This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details. * for more details.
* *
* You should have received a copy of the GNU General Public License along * You should have received a copy of the GNU General Public License along
@ -22,51 +22,41 @@
#ifndef __CONFIG_H #ifndef __CONFIG_H
#define __CONFIG_H #define __CONFIG_H
#if 0
#define DEBUG 0xFFF
#endif
#if 0
#define DEBUG 0x01
#endif
/* /*
* High Level Configuration Options * High Level Configuration Options
* (easy to change) * (easy to change)
*/ */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
#define CONFIG_V38B 1 /* ...on V38B board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
#define CONFIG_V38B 1 /* ... on V38B board */
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ #define CONFIG_HW_WATCHDOG 1 /* has watchdog */
#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
#define CONFIG_HW_WATCHDOG 1 /* has watchdog */
#define CONFIG_NETCONSOLE 1 #define CONFIG_NETCONSOLE 1
#define CONFIG_BOARD_EARLY_INIT_R 1 /* make flash read/write */ #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
#define CFG_XLB_PIPELINING 1 /* gives better performance */ #define CFG_XLB_PIPELINING 1 /* gives better performance */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif #endif
/* /*
* Serial console configuration * Serial console configuration
*/ */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* /*
* DDR * DDR
*/ */
@ -79,7 +69,6 @@
#define SDRAM_CONFIG2 0x47770000 #define SDRAM_CONFIG2 0x47770000
#define SDRAM_TAPDELAY 0x10000000 #define SDRAM_TAPDELAY 0x10000000
/* /*
* PCI - no suport * PCI - no suport
*/ */
@ -96,13 +85,13 @@
*/ */
#define CONFIG_USB_OHCI #define CONFIG_USB_OHCI
#define CONFIG_USB_STORAGE #define CONFIG_USB_STORAGE
#define CONFIG_USB_CLOCK 0x0001BBBB
#define CONFIG_TIMESTAMP /* Print image info with timestamp */ #define CONFIG_USB_CONFIG 0x00001000
/* /*
* Supported commands * Supported commands
*/ */
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
CFG_CMD_FAT | \ CFG_CMD_FAT | \
CFG_CMD_I2C | \ CFG_CMD_I2C | \
CFG_CMD_IDE | \ CFG_CMD_IDE | \
@ -112,53 +101,63 @@
CFG_CMD_IRQ | \ CFG_CMD_IRQ | \
CFG_CMD_JFFS2 | \ CFG_CMD_JFFS2 | \
CFG_CMD_MII | \ CFG_CMD_MII | \
CFG_CMD_SDRAMi | \ CFG_CMD_SDRAMi | \
CFG_CMD_DATE | \ CFG_CMD_DATE | \
CFG_CMD_USB | \ CFG_CMD_USB | \
CFG_CMD_FAT) CFG_CMD_FAT)
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
/* /*
* Boot low with 16 MB Flash * Boot low with 16 MB Flash
*/ */
# define CFG_LOWBOOT 1 #define CFG_LOWBOOT 1
# define CFG_LOWBOOT16 1 #define CFG_LOWBOOT16 1
/* /*
* Autobooting * Autobooting
*/ */
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_PREBOOT "echo;" \ #define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
"echo" "echo"
#undef CONFIG_BOOTARGS #undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"devno=5\0" \
"hostname=V38B_$(devno)\0" \
"ipaddr=10.100.99.$(devno)\0" \
"netmask=255.255.0.0\0" \
"serverip=10.100.10.90\0" \
"gatewayip=10.100.254.254\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=mpc5200/uImage\0" \
"bootcmd=run net_nfs\0" \ "bootcmd=run net_nfs\0" \
"bootdelay=3\0" \
"baudrate=115200\0" \
"preboot=echo;echo Type \"run flash_nfs\" to mount root " \
"filesystem over NFS; echo\0" \
"netdev=eth0\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs $(bootargs) " \ "addip=setenv bootargs $(bootargs) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):" \ "ip=$(ipaddr):$(serverip):$(gatewayip):" \
"$(netmask):$(hostname):$(netdev):off panic=1\0" \ "$(netmask):$(hostname):$(netdev):off panic=1\0" \
"flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
"flash_self=run ramargs addip;bootm $(kernel_addr) " \ "flash_self=run ramargs addip;bootm $(kernel_addr) " \
"$(ramdisk_addr)\0" \ "$(ramdisk_addr)\0" \
"net_nfs=tftp 200000 $(bootfile);run nfsargs " \ "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
"addip;bootm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=$(serverip):$(rootpath)\0" \ "nfsroot=$(serverip):$(rootpath)\0" \
"hostname=v38b\0" \
"ethact=FEC ETHERNET\0" \
"rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
"update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
"cp.b 200000 ff000000 $(filesize);" \
"prot on ff000000 ff03ffff\0" \
"load=tftp 200000 $(u-boot)\0" \
"netmask=255.255.0.0\0" \
"ipaddr=192.168.160.18\0" \
"serverip=192.168.1.1\0" \
"ethaddr=00:e0:ee:00:05:2e\0" \
"bootfile=/tftpboot/v38b/uImage\0" \
"u-boot=/tftpboot/v38b/u-boot.bin\0" \
"" ""
#define CONFIG_BOOTCOMMAND "run net_nfs" #define CONFIG_BOOTCOMMAND "run net_nfs"
@ -169,13 +168,13 @@
*/ */
#undef CFG_IPBSPEED_133 /* define for 133MHz speed */ #undef CFG_IPBSPEED_133 /* define for 133MHz speed */
#endif #endif
/* /*
* I2C configuration * I2C configuration
*/ */
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SPEED 100000 /* 100 kHz */
#define CFG_I2C_SLAVE 0x7F #define CFG_I2C_SLAVE 0x7F
/* /*
@ -196,7 +195,7 @@
*/ */
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
#define CFG_FLASH_CFI_AMD_RESET 1 #define CFG_FLASH_CFI_AMD_RESET 1
#define CFG_FLASH_BASE 0xFF000000 #define CFG_FLASH_BASE 0xFF000000
#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
@ -224,19 +223,18 @@
#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */ #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_BASE TEXT_BASE #define CFG_MONITOR_BASE TEXT_BASE
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
# define CFG_RAMBOOT 1 # define CFG_RAMBOOT 1
#endif #endif
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ #define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
/* /*
* Ethernet configuration * Ethernet configuration
@ -253,19 +251,19 @@
/* /*
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#define CFG_LONGHELP /* undef to save memory */ #define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */ #define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
#define CFG_LOAD_ADDR 0x100000 /* default load address */ #define CFG_LOAD_ADDR 0x100000 /* default load address */
@ -274,14 +272,8 @@
/* /*
* Various low-level settings * Various low-level settings
*/ */
#if defined(CONFIG_MPC5200)
#define CFG_HID0_INIT HID0_ICE | HID0_ICFI #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
#define CFG_HID0_FINAL HID0_ICE #define CFG_HID0_FINAL HID0_ICE
#else
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL 0
#endif
#define CFG_BOOTCS_START CFG_FLASH_BASE #define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
@ -294,55 +286,39 @@
#define CFG_RESET_ADDRESS 0xff000000 #define CFG_RESET_ADDRESS 0xff000000
/*----------------------------------------------------------------------- /*
* USB stuff * IDE/ATA (supports IDE harddisk)
*-----------------------------------------------------------------------
*/ */
#define CONFIG_USB_CLOCK 0x0001BBBB #undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
#define CONFIG_USB_CONFIG 0x00001000 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
*-----------------------------------------------------------------------
*/
#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#define CONFIG_IDE_RESET /* reset for ide supported */
#define CONFIG_IDE_PREINIT #define CONFIG_IDE_PREINIT
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
#define CFG_ATA_IDE0_OFFSET 0x0000 #define CFG_ATA_IDE0_OFFSET 0x0000
#define CFG_ATA_BASE_ADDR MPC5XXX_ATA #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */ #define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
#define CFG_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */ #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */
#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
/* Offset for alternate registers */ #define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
#define CFG_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */ #define CFG_ATA_STRIDE 4 /* Interval between registers */
#define CFG_ATA_STRIDE 4
/* Status LED */ /*
* Status LED
#define CONFIG_STATUS_LED /* Status LED enabled */ */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ #define CONFIG_STATUS_LED /* Status LED enabled */
#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
#define CFG_LED_BASE (0xf0000600 + 0x70) /* Timer 7 GPIO */
#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* LEDs */
typedef unsigned int led_id_t; typedef unsigned int led_id_t;
#define __led_toggle(_msk) \ #define __led_toggle(_msk) \
@ -359,10 +335,9 @@ typedef unsigned int led_id_t;
} while(0) } while(0)
#define __led_init(_msk, st) \ #define __led_init(_msk, st) \
{ \ do { \
*((volatile long *) (CFG_LED_BASE)) |= 0x34; \ *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
} } while(0)
#endif /* __ASSEMBLY__ */
#endif
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */