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phy: marvell: utmi: update utmi config which fixes usb2.0 instability
- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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@ -288,21 +288,34 @@ static void comphy_utmi_phy_config(u32 utmi_index, void __iomem *utmi_pll_addr,
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reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
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reg_set(utmi_pll_addr + UTMI_PLL_CTRL_REG, data, mask);
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/* Impedance Calibration Threshold Setting */
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/* Impedance Calibration Threshold Setting */
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reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG,
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mask = UTMI_CALIB_CTRL_IMPCAL_VTH_MASK;
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0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET,
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data = 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET;
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UTMI_CALIB_CTRL_IMPCAL_VTH_MASK);
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reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
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/* Start Impedance and PLL Calibration */
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mask = UTMI_CALIB_CTRL_PLLCAL_START_MASK;
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data = (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET);
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mask |= UTMI_CALIB_CTRL_IMPCAL_START_MASK;
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data |= (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET);
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reg_set(utmi_pll_addr + UTMI_CALIB_CTRL_REG, data, mask);
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/* Set LS TX driver strength coarse control */
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/* Set LS TX driver strength coarse control */
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mask = UTMI_TX_CH_CTRL_AMP_MASK;
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mask = UTMI_TX_CH_CTRL_AMP_MASK;
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data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
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data = 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET;
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mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK;
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data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET;
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mask |= UTMI_TX_CH_CTRL_DRV_EN_LS_MASK;
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data |= 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET;
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reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
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reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask);
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/* Enable SQ */
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/* Enable SQ */
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mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
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mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK;
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data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
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data = 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET;
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/* Enable analog squelch detect */
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/* Enable analog squelch detect */
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mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
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mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK;
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data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
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data |= 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET;
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mask |= UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK;
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data |= 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET;
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reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
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reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask);
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/* Set External squelch calibration number */
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/* Set External squelch calibration number */
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@ -38,6 +38,12 @@
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#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
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#define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8
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#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
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#define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK \
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(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
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(0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET)
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#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13
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#define UTMI_CALIB_CTRL_IMPCAL_START_MASK \
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(0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET)
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#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22
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#define UTMI_CALIB_CTRL_PLLCAL_START_MASK \
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(0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET)
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#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
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#define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23
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#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
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#define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK \
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(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
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(0x1 << UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET)
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@ -57,6 +63,9 @@
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(0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
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(0x7 << UTMI_TX_CH_CTRL_AMP_OFFSET)
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#define UTMI_RX_CH_CTRL0_REG 0x8
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#define UTMI_RX_CH_CTRL0_REG 0x8
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#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8
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#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK \
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(0x3 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET)
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#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
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#define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15
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#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
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#define UTMI_RX_CH_CTRL0_SQ_DET_MASK \
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(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
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(0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET)
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