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mips: mscc: serval: Fix reset

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In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
This commit is contained in:
Horatiu Vultur 2019-04-15 11:56:36 +02:00 committed by Daniel Schwierzeck
parent b4ee6daad7
commit 72e224b864
2 changed files with 31 additions and 26 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
arch/mips/mach-mscc/include/mach/ddr.h
View File

@ -401,23 +401,7 @@ static inline void sleep_100ns(u32 val)
;
}
#if defined(CONFIG_SOC_OCELOT)
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* DDR has reset pin on GPIO 19 toggle Low-High to release */
setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
sleep_100ns(10000);
}
static inline void hal_vcoreiii_ddr_reset_release(void)
{
/* DDR has reset pin on GPIO 19 toggle Low-High to release */
setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
sleep_100ns(10000);
}
#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_SERVAL)
/*
* DDR memory sanity checking failed, tally and do hard reset
*
@ -427,9 +411,11 @@ static inline void hal_vcoreiii_ddr_failed(void)
{
register u32 reset;
#if defined(CONFIG_SOC_OCELOT)
writel(readl(BASE_CFG + ICPU_GPR(6)) + 1, BASE_CFG + ICPU_GPR(6));
clrbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
#endif
/* We have to execute the reset function from cache. Indeed,
* the reboot workaround in _machine_restart() will change the
@ -452,6 +438,33 @@ static inline void hal_vcoreiii_ddr_failed(void)
panic("DDR init failed\n");
}
#else /* JR2 || ServalT */
static inline void hal_vcoreiii_ddr_failed(void)
{
writel(0, BASE_CFG + ICPU_RESET);
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
panic("DDR init failed\n");
}
#endif
#if defined(CONFIG_SOC_OCELOT)
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
/* DDR has reset pin on GPIO 19 toggle Low-High to release */
setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_CLR);
sleep_100ns(10000);
}
static inline void hal_vcoreiii_ddr_reset_release(void)
{
/* DDR has reset pin on GPIO 19 toggle Low-High to release */
setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
sleep_100ns(10000);
}
#else /* JR2 || ServalT || Serval */
static inline void hal_vcoreiii_ddr_reset_assert(void)
{
@ -463,14 +476,6 @@ static inline void hal_vcoreiii_ddr_reset_assert(void)
writel(readl(BASE_CFG + ICPU_RESET) |
ICPU_RESET_MEM_RST_FORCE, BASE_CFG + ICPU_RESET);
}
static inline void hal_vcoreiii_ddr_failed(void)
{
writel(0, BASE_CFG + ICPU_RESET);
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_CFG + PERF_SOFT_RST);
panic("DDR init failed\n");
}
#endif /* JR2 || ServalT || Serval */
/*

2
arch/mips/mach-mscc/reset.c
View File

@ -36,7 +36,7 @@ void _machine_restart(void)
/* Do global reset */
writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
for (i = 0; i < 1000; i++)
for (i = 0; i < 2000; i++)
;
/* Power down DDR for clean DDR re-training */