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u-boot-brain
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Porting to DM and i.MX8 

------------------------
 
 - warp7 to DM
 - kp_imx53 to DM
 - Warnings in DT
 - MX8QM support
 - colibri-imx6ull to DM
 - imx7d-pico to DM
 - ocotp for MX8
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Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx

Porting to DM and i.MX8
------------------------

- warp7 to DM
- kp_imx53 to DM
- Warnings in DT
- MX8QM support
- colibri-imx6ull to DM
- imx7d-pico to DM
- ocotp for MX8
This commit is contained in:
Tom Rini 2019-04-30 23:21:27 -04:00
parent a69120a0d7 0d3912fcd4
commit b4ee6daad7
111 changed files with 6451 additions and 836 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -1639,6 +1639,7 @@ source "board/tcl/sl50/Kconfig"
source "board/ucRobotics/bubblegum_96/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/woodburn/Kconfig"
source "board/xilinx/Kconfig"

10
arch/arm/dts/Makefile
View File

@ -558,6 +558,7 @@ dtb-$(CONFIG_MX6UL) += \
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
imx6ull-dart-6ul.dtb
dtb-$(CONFIG_ARCH_MX6) += \
imx6-colibri.dtb
@ -566,11 +567,16 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-sdb-qspi.dtb \
imx7-colibri-emmc.dtb \
imx7-colibri-rawnand.dtb \
imx7s-warp.dtb
imx7s-warp.dtb \
imx7d-pico-pi.dtb \
imx7d-pico-hobbit.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qxp-mek.dtb \
fsl-imx8qm-mek.dtb \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb

54
arch/arm/dts/fsl-imx8dx.dtsi
View File

@ -236,6 +236,21 @@
power-domains = <&pd_dma>;
wakeup-irq = <225>;
};
pd_dma_lpuart1: PD_DMA_UART1 {
reg = <SC_R_UART_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpuart2: PD_DMA_UART2 {
reg = <SC_R_UART_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpuart3: PD_DMA_UART3 {
reg = <SC_R_UART_3>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
};
};
@ -402,6 +417,45 @@
status = "disabled";
};
lpuart1: serial@5a070000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a070000 0x0 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QXP_UART1_CLK>,
<&clk IMX8QXP_UART1_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_UART1_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart1>;
status = "disabled";
};
lpuart2: serial@5a080000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a080000 0x0 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QXP_UART2_CLK>,
<&clk IMX8QXP_UART2_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_UART2_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart2>;
status = "disabled";
};
lpuart3: serial@5a090000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a090000 0x0 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QXP_UART3_CLK>,
<&clk IMX8QXP_UART3_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QXP_UART3_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart3>;
status = "disabled";
};
usdhc1: usdhc@5b010000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;

112
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi Normal file
View File

@ -0,0 +1,112 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
&mu {
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pd_lsio {
u-boot,dm-spl;
};
&pd_lsio_gpio0 {
u-boot,dm-spl;
};
&pd_lsio_gpio1 {
u-boot,dm-spl;
};
&pd_lsio_gpio2 {
u-boot,dm-spl;
};
&pd_lsio_gpio3 {
u-boot,dm-spl;
};
&pd_lsio_gpio4 {
u-boot,dm-spl;
};
&pd_lsio_gpio5 {
u-boot,dm-spl;
};
&pd_lsio_gpio6 {
u-boot,dm-spl;
};
&pd_lsio_gpio7 {
u-boot,dm-spl;
};
&pd_conn {
u-boot,dm-spl;
};
&pd_conn_sdch0 {
u-boot,dm-spl;
};
&pd_conn_sdch1 {
u-boot,dm-spl;
};
&pd_conn_sdch2 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&gpio6 {
u-boot,dm-spl;
};
&gpio7 {
u-boot,dm-spl;
};
&lpuart0 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};

184
arch/arm/dts/fsl-imx8qm-mek.dts Normal file
View File

@ -0,0 +1,184 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2018 NXP
*/
/dts-v1/;
#include "fsl-imx8qm.dtsi"
#include "fsl-imx8qm-mek-u-boot.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
stdout-path = &lpuart0;
};
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
off-on-delay = <4800>;
enable-active-high;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx8qm-mek {
pinctrl_hog: hoggrp {
fsl,pins = <
SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0
SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060
SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060
SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060
SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060
SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060
SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060
SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060
SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060
SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060
SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060
SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060
SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_DMA_UART0_RX 0x06000020
SC_P_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
};
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-txid";
phy-handle = <&ethphy0>;
fsl,magic-packet;
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
status = "disabled";
};
};
};
&lpuart0 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&gpio1 {
status = "okay";
};

400
arch/arm/dts/fsl-imx8qm.dtsi Normal file
View File

@ -0,0 +1,400 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "fsl-imx8-ca53.dtsi"
#include <dt-bindings/clock/imx8qm-clock.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <dt-bindings/soc/imx8_pd.h>
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "fsl,imx8qm";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &fec1;
ethernet1 = &fec2;
serial0 = &lpuart0;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
/* DRAM space - 1, size : 1 GB DRAM */
};
gic: interrupt-controller@51a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
<0x0 0x51b00000 0 0xC0000>, /* GICR */
<0x0 0x52000000 0 0x2000>, /* GICC */
<0x0 0x52010000 0 0x1000>, /* GICH */
<0x0 0x52020000 0 0x20000>; /* GICV */
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
interrupt-parent = <&gic>;
};
mu: mu@5d1c0000 {
compatible = "fsl,imx8-mu";
reg = <0x0 0x5d1c0000 0x0 0x10000>;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
fsl,scu_ap_mu_id = <0>;
status = "okay";
clk: clk {
compatible = "fsl,imx8qm-clk";
#clock-cells = <1>;
};
iomuxc: iomuxc {
compatible = "fsl,imx8qm-iomuxc";
};
};
imx8qm-pm {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
pd_lsio: PD_LSIO {
compatible = "nxp,imx8-pd";
reg = <SC_R_LAST>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_lsio_gpio0: PD_LSIO_GPIO_0 {
reg = <SC_R_GPIO_0>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio1: PD_LSIO_GPIO_1 {
reg = <SC_R_GPIO_1>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio2: PD_LSIO_GPIO_2 {
reg = <SC_R_GPIO_2>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio3: PD_LSIO_GPIO_3 {
reg = <SC_R_GPIO_3>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio4: PD_LSIO_GPIO_4 {
reg = <SC_R_GPIO_4>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio5: PD_LSIO_GPIO_5{
reg = <SC_R_GPIO_5>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio6:PD_LSIO_GPIO_6 {
reg = <SC_R_GPIO_6>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
pd_lsio_gpio7: PD_LSIO_GPIO_7 {
reg = <SC_R_GPIO_7>;
#power-domain-cells = <0>;
power-domains = <&pd_lsio>;
};
};
pd_conn: PD_CONN {
compatible = "nxp,imx8-pd";
reg = <SC_R_LAST>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_conn_sdch0: PD_CONN_SDHC_0 {
reg = <SC_R_SDHC_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_sdch1: PD_CONN_SDHC_1 {
reg = <SC_R_SDHC_1>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_sdch2: PD_CONN_SDHC_2 {
reg = <SC_R_SDHC_2>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
};
pd_conn_enet0: PD_CONN_ENET_0 {
reg = <SC_R_ENET_0>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
wakeup-irq = <258>;
};
pd_conn_enet1: PD_CONN_ENET_1 {
reg = <SC_R_ENET_1>;
#power-domain-cells = <0>;
power-domains = <&pd_conn>;
fsl,wakeup_irq = <262>;
};
};
pd_dma: PD_DMA {
compatible = "nxp,imx8-pd";
reg = <SC_R_LAST>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_dma_lpi2c0: PD_DMA_I2C_0 {
reg = <SC_R_I2C_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c1: PD_DMA_I2C_1 {
reg = <SC_R_I2C_1>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c2:PD_DMA_I2C_2 {
reg = <SC_R_I2C_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c3: PD_DMA_I2C_3 {
reg = <SC_R_I2C_3>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpi2c4: PD_DMA_I2C_4 {
reg = <SC_R_I2C_4>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
};
pd_dma_lpuart0: PD_DMA_UART0 {
reg = <SC_R_UART_0>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
wakeup-irq = <345>;
};
};
};
gpio0: gpio@5d080000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d080000 0x0 0x10000>;
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio0>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio1: gpio@5d090000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d090000 0x0 0x10000>;
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio1>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@5d0a0000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d0a0000 0x0 0x10000>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@5d0b0000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d0b0000 0x0 0x10000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio3>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@5d0c0000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d0c0000 0x0 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio4>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@5d0d0000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d0d0000 0x0 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio5>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio6: gpio@5d0e0000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d0e0000 0x0 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio6>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio7: gpio@5d0f0000 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d0f0000 0x0 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
power-domains = <&pd_lsio_gpio7>;
interrupt-controller;
#interrupt-cells = <2>;
};
lpuart0: serial@5a060000 {
compatible = "fsl,imx8qm-lpuart";
reg = <0x0 0x5a060000 0x0 0x1000>;
interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_UART0_CLK>,
<&clk IMX8QM_UART0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_UART0_CLK>;
assigned-clock-rates = <80000000>;
power-domains = <&pd_dma_lpuart0>;
status = "disabled";
};
usdhc1: usdhc@5b010000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x5b010000 0x0 0x10000>;
clocks = <&clk IMX8QM_SDHC0_IPG_CLK>,
<&clk IMX8QM_SDHC0_CLK>,
<&clk IMX8QM_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QM_SDHC0_DIV>;
assigned-clock-rates = <400000000>;
power-domains = <&pd_conn_sdch0>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc2: usdhc@5b020000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x5b020000 0x0 0x10000>;
clocks = <&clk IMX8QM_SDHC1_IPG_CLK>,
<&clk IMX8QM_SDHC1_CLK>,
<&clk IMX8QM_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QM_SDHC1_DIV>;
assigned-clock-rates = <200000000>;
power-domains = <&pd_conn_sdch1>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
usdhc3: usdhc@5b030000 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x5b030000 0x0 0x10000>;
clocks = <&clk IMX8QM_SDHC2_IPG_CLK>,
<&clk IMX8QM_SDHC2_CLK>,
<&clk IMX8QM_CLK_DUMMY>;
clock-names = "ipg", "per", "ahb";
assigned-clocks = <&clk IMX8QM_SDHC2_DIV>;
assigned-clock-rates = <200000000>;
power-domains = <&pd_conn_sdch2>;
status = "disabled";
};
fec1: ethernet@5b040000 {
compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
reg = <0x0 0x5b040000 0x0 0x10000>;
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_ENET0_IPG_CLK>,
<&clk IMX8QM_ENET0_AHB_CLK>,
<&clk IMX8QM_ENET0_RGMII_TX_CLK>,
<&clk IMX8QM_ENET0_PTP_CLK>,
<&clk IMX8QM_ENET0_TX_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
"enet_2x_txclk";
assigned-clocks = <&clk IMX8QM_ENET0_ROOT_DIV>,
<&clk IMX8QM_ENET0_REF_DIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,wakeup_irq = <0>;
power-domains = <&pd_conn_enet0>;
status = "disabled";
};
fec2: ethernet@5b050000 {
compatible = "fsl,imx8qm-fec", "fsl,imx7d-fec";
reg = <0x0 0x5b050000 0x0 0x10000>;
interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8QM_ENET1_IPG_CLK>,
<&clk IMX8QM_ENET1_AHB_CLK>,
<&clk IMX8QM_ENET1_RGMII_TX_CLK>,
<&clk IMX8QM_ENET1_PTP_CLK>,
<&clk IMX8QM_ENET1_TX_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp",
"enet_2x_txclk";
assigned-clocks = <&clk IMX8QM_ENET1_ROOT_DIV>,
<&clk IMX8QM_ENET1_REF_DIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
fsl,wakeup_irq = <0>;
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
};
&A53_0 {
clocks = <&clk IMX8QM_A53_DIV>;
};

5
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
View File

@ -3,6 +3,11 @@
* Copyright 2018 NXP
*/
&{/imx8qx-pm} {
u-boot,dm-spl;
};
&mu {
u-boot,dm-spl;
};

59
arch/arm/dts/imx53-kp.dts
View File

@ -17,6 +17,34 @@
chosen {
stdout-path = &uart2;
};
aliases {
mmc0 = &esdhc3;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
};
&esdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc3>;
bus-width = <8>;
non-removable;
status = "okay";
};
&fec {
@ -61,6 +89,21 @@
pinctrl-0 = <&pinctrl_hog>;
imx53-kp {
pinctrl_esdhc3: esdhc3grp {
fsl,pins = <
MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d4
MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d4
MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d4
MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d4
MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d4
MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d4
MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d4
MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d4
MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1e4
MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d4
>;
};
pinctrl_eth: ethgrp {
fsl,pins = <
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
@ -82,8 +125,6 @@
fsl,pins = <
/* PHY RESET */
MX53_PAD_PATA_DA_0__GPIO7_6 0x182
/* VBUS_PWR_EN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
/* BOOSTER_OFF */
MX53_PAD_EIM_CS0__GPIO2_23 0x1e4
/* LCD BACKLIGHT */
@ -129,6 +170,13 @@
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
/* VBUS_PWR_EN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x1e4
>;
};
};
};
@ -137,3 +185,10 @@
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbh1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usbh1_vbus>;
status = "okay";
};

10
arch/arm/dts/imx53.dtsi
View File

@ -35,6 +35,7 @@
mmc1 = &esdhc2;
mmc2 = &esdhc3;
mmc3 = &esdhc4;
usb1 = &usbh1;
};
tzic: tz-interrupt-controller@fffc000 {
@ -136,6 +137,15 @@
status = "disabled";
};
usbh1: usb@53f80200 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
dr_mode = "host";
status = "disabled";
};
clks: ccm@53fd4000{
compatible = "fsl,imx53-ccm";
reg = <0x53fd4000 0x4000>;

5
arch/arm/dts/imx6q.dtsi
View File

@ -202,6 +202,7 @@
<&clks IMX6QDL_CLK_GPU2D_CORE>;
clock-names = "bus", "core";
power-domains = <&pd_pu>;
#cooling-cells = <2>;
};
ipu2: ipu@2800000 {
@ -234,6 +235,8 @@
};
ipu2_di0: port@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
ipu2_di0_disp0: endpoint@0 {
@ -262,6 +265,8 @@
};
ipu2_di1: port@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
ipu2_di1_hdmi: endpoint@1 {

170
arch/arm/dts/imx6ull-colibri.dts
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2018 Toradex AG
* Copyright 2018-2019 Toradex AG
*/
/dts-v1/;
@ -9,7 +9,12 @@
/ {
model = "Toradex Colibri iMX6ULL";
compatible = "toradex,imx6ull-colibri", "fsl,imx6ull";
compatible = "toradex,colibri-imx6ull", "fsl,imx6ull";
aliases {
mmc0 = &usdhc1;
usb0 = &usbotg1; /* required for ums */
};
chosen {
stdout-path = &uart1;
@ -31,6 +36,13 @@
regulator-max-microvolt = <3300000>;
};
reg_5v0: regulator-5v0 {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_sd1_vmmc: regulator-sd1-vmmc {
compatible = "regulator-gpio";
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
@ -43,6 +55,17 @@
states = <1800000 0x1 3300000 0x0>;
vin-supply = <&reg_module_3v3>;
};
reg_usbh_vbus: regulator-usbh-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh_reg>;
regulator-name = "VCC_USB[1-4]";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
vin-supply = <&reg_5v0>;
};
};
&adc1 {
@ -57,6 +80,7 @@
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
};
/* Ethernet */
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
@ -76,6 +100,7 @@
};
};
/* NAND */
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
@ -86,21 +111,28 @@
status = "okay";
};
/*
* I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier board)
*/
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
/*
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
* touch screen controller
*/
&i2c2 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
ad7879@2c {
@ -126,24 +158,28 @@
&pinctrl_lcdif_ctrl>;
};
/* PWM <A> */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
#pwm-cells = <3>;
};
/* PWM <B> */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
#pwm-cells = <3>;
};
/* PWM <C> */
&pwm6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm6>;
#pwm-cells = <3>;
};
/* PWM <D> */
&pwm7 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm7>;
@ -158,45 +194,110 @@
status = "disabled";
};
/* Colibri UART_A */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
fsl,uart-has-rtscts;
uart-has-rtscts;
fsl,dte-mode;
status = "okay";
};
/* Colibri UART_B */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
uart-has-rtscts;
fsl,dte-mode;
};
/* Colibri UART_C */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,dte-mode;
};
/* Colibri USBC */
&usbotg1 {
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
/* Colibri USBH */
&usbotg2 {
dr_mode = "host";
vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
/* Colibri MMC */
&usdhc1 {
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl_can_int: canint-grp {
fsl,pins = <
/* SODIMM 73 */
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14
>;
};
pinctrl_enet2: enet2-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
>;
};
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio_bl_on: gpio-bl-on-grp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
>;
};
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
@ -253,54 +354,6 @@
>;
};
pinctrl_can_int: canint-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
>;
};
pinctrl_enet2: enet2-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
>;
};
pinctrl_ecspi1_cs: ecspi1-cs-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
>;
};
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
>;
};
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio_bl_on: gpio-bl-on-grp {
fsl,pins = <
MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
>;
};
pinctrl_gpmi_nand: gpmi-nand-grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
@ -484,6 +537,8 @@
MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14
>;
};
};
@ -511,7 +566,7 @@
>;
};
pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
>;
@ -547,4 +602,3 @@
>;
};
};

39
arch/arm/dts/imx6ull-dart-6ul.dts Normal file
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@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-dart-6ul.dtsi"
/ {
model = "Variscite DART-6UL Evaluation Kit";
compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
};
&usdhc2 {
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
};

261
arch/arm/dts/imx6ull-dart-6ul.dtsi Normal file
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@ -0,0 +1,261 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
/ {
model = "Variscite DART-6UL i.MX6 Ultra Low Lite SOM";
compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
memory {
reg = <0x80000000 0x20000000>;
};
chosen {
stdout-path = &uart1;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio1: mdio1 {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <1>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio2: mdio2 {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <1>;
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
fsl,no-blockmark-swap;
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "uboot";
reg = <0x0 0x400000>;
};
partition@400000 {
label = "uboot-env";
reg = <0x400000 0x100000>;
};
partition@500000 {
label = "root";
reg = <0x500000 0x0>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
status = "okay";
eeprom@50 {
compatible = "cat,24c32";
reg = <0x50>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
#pwm-cells = <3>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
bus-width = <0x4>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
status = "disabled";
};
&iomuxc {
pinctrl-names = "default";
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0X1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0X1b0b0
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x0b0b1
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_i2c1: i2cgrp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c1_gpio: i2c1grp_gpio {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
>;
};
pinctrl_i2c2: i2cgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
>;
};
pinctrl_i2c2_gpio: i2c2grp_gpio {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x1b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};

26
arch/arm/dts/imx6ull-pinfunc.h
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@ -14,6 +14,8 @@
* The pin function ID is a tuple of
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x0068 0x02f4 0x0000 0x3 0x0
#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0
#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0
#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0
@ -41,17 +43,17 @@
#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0
#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0
#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0
#endif /* __DTS_IMX6ULL_PINFUNC_H */

2
arch/arm/dts/imx6ull.dtsi
View File

@ -46,6 +46,8 @@
spi4 = &ecspi4;
usbphy0 = &usbphy1;
usbphy1 = &usbphy2;
usb0 = &usbotg1;
usb1 = &usbotg2;
};
cpus {

105
arch/arm/dts/imx7d-pico-hobbit.dts Normal file
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@ -0,0 +1,105 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright 2017 NXP
#include "imx7d-pico.dtsi"
/ {
model = "TechNexion PICO-IMX7D Board using Hobbit baseboard";
compatible = "technexion,imx7d-pico-hobbit", "fsl,imx7d";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led {
label = "gpio-led";
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
};
};
};
&i2c1 {
sgtl5000: codec@a {
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};
};
&i2c4 {
status = "okay";
adc081c: adc@50 {
compatible = "ti,adc081c";
reg = <0x50>;
vref-supply = <&reg_3p3v>;
};
};
&ecspi3 {
ads7846@0 {
reg = <0>;
compatible = "ti,ads7846";
interrupt-parent = <&gpio2>;
interrupts = <7 0>;
spi-max-frequency = <1000000>;
pendown-gpio = <&gpio2 7 0>;
vcc-supply = <&reg_3p3v>;
ti,x-min = /bits/ 16 <0>;
ti,x-max = /bits/ 16 <4095>;
ti,y-min = /bits/ 16 <0>;
ti,y-max = /bits/ 16 <4095>;
ti,pressure-max = /bits/ 16 <1024>;
ti,x-plate-ohms = /bits/ 16 <90>;
ti,y-plate-ohms = /bits/ 16 <90>;
ti,debounce-max = /bits/ 16 <70>;
ti,debounce-tol = /bits/ 16 <3>;
ti,debounce-rep = /bits/ 16 <2>;
ti,settle-delay-usec = /bits/ 16 <150>;
wakeup-source;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
>;
};
};

93
arch/arm/dts/imx7d-pico-pi.dts Normal file
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@ -0,0 +1,93 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright 2017 NXP
#include "imx7d-pico.dtsi"
/ {
model = "TechNexion PICO-IMX7D Board and PI baseboard";
compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led {
label = "gpio-led";
gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
};
};
};
&i2c1 {
sgtl5000: codec@a {
#sound-dai-cells = <0>;
reg = <0x0a>;
compatible = "fsl,sgtl5000";
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
VDDA-supply = <&reg_2p5v>;
VDDIO-supply = <&reg_vref_1v8>;
};
};
&i2c4 {
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5x06";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
interrupt-parent = <&gpio2>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14
MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x14
MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x14
MX7D_PAD_EPDC_DATA12__GPIO2_IO12 0x14
MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x14
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x14
>;
};
pinctrl_touchscreen: touchscreengrp {
fsl,pins = <
MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
>;
};
};

590
arch/arm/dts/imx7d-pico.dtsi Normal file
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@ -0,0 +1,590 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
//
// Copyright 2017 NXP
/dts-v1/;
#include "imx7d.dtsi"
/ {
aliases {
mmc0 = &usdhc3;
};
/* Will be filled by the bootloader */
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0>;
};
reg_wlreg_on: regulator-wlreg_on {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wlreg_on>;
regulator-name = "wlreg_on";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_2p5v: regulator-2p5v {
compatible = "regulator-fixed";
regulator-name = "2P5V";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_pwr>;
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
};
reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "vref-1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
usdhc2_pwrseq: usdhc2_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
clock-names = "ext_clock";
};
};
&clks {
assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
<&clks IMX7D_CLKO2_ROOT_DIV>;
assigned-clock-parents = <&clks IMX7D_CKIL>;
assigned-clock-rates = <0>, <32768>;
};
&ecspi3 {
cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
assigned-clock-rates = <0>, <100000000>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
phy-reset-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
status = "okay";
};
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
pmic: pfuze3000@8 {
compatible = "fsl,pfuze3000";
reg = <0x08>;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
/* use sw1c_reg to align with pfuze100/pfuze200 */
sw1c_reg: sw1b {
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1475000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1850000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1650000>;
regulator-boot-on;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen2_reg: vldo2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vccsd {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: v33 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vldo3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vldo4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
<&clks IMX7D_SAI1_ROOT_CLK>;
assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
assigned-clock-rates = <0>, <24576000>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&pwm4 { /* Backlight */
status = "okay";
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
status = "okay";
};
&uart6 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6>;
assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
uart-has-rtscts;
status = "okay";
};
&uart7 { /* Bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7>;
assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>;
assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
bus-width = <4>;
tuning-step = <2>;
vmmc-supply = <&reg_3p3v>;
wakeup-source;
no-1-8-v;
keep-power-in-suspend;
status = "okay";
};
&usdhc2 { /* Wifi SDIO */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_wlreg_on>;
mmc-pwrseq = <&usdhc2_pwrseq>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
assigned-clock-rates = <400000000>;
bus-width = <8>;
no-1-8-v;
fsl,tuning-step = <2>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX7D_PAD_I2C1_SCL__ECSPI3_MISO 0x2
MX7D_PAD_I2C1_SDA__ECSPI3_MOSI 0x2
MX7D_PAD_I2C2_SCL__ECSPI3_SCLK 0x2
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX7D_PAD_UART2_TX_DATA__I2C2_SDA 0x4000007f
MX7D_PAD_UART2_RX_DATA__I2C2_SCL 0x4000007f
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
MX7D_PAD_SD2_WP__ENET1_MDC 0x3
MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
MX7D_PAD_SD3_RESET_B__GPIO6_IO11 0x1 /* Ethernet reset */
>;
};
pinctrl_can1: can1frp {
fsl,pins = <
MX7D_PAD_SAI1_RX_DATA__FLEXCAN1_RX 0x59
MX7D_PAD_SAI1_TX_BCLK__FLEXCAN1_TX 0x59
>;
};
pinctrl_can2: can2frp {
fsl,pins = <
MX7D_PAD_SAI1_TX_SYNC__FLEXCAN2_RX 0x59
MX7D_PAD_SAI1_TX_DATA__FLEXCAN2_TX 0x59
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f
>;
};
pinctrl_pwm1: pwm1 {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x7f
>;
};
pinctrl_pwm2: pwm2 {
fsl,pins = <
MX7D_PAD_GPIO1_IO09__PWM2_OUT 0x7f
>;
};
pinctrl_pwm3: pwm3 {
fsl,pins = <
MX7D_PAD_GPIO1_IO10__PWM3_OUT 0x7f
>;
};
pinctrl_reg_wlreg_on: regregongrp {
fsl,pins = <
MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16 0x59
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
>;
};
pinctrl_uart6: uart6grp {
fsl,pins = <
MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x79
MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x79
MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x79
MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x79
>;
};
pinctrl_uart7: uart7grp {
fsl,pins = <
MX7D_PAD_ECSPI2_MOSI__UART7_DCE_TX 0x79
MX7D_PAD_ECSPI2_SCLK__UART7_DCE_RX 0x79
MX7D_PAD_ECSPI2_SS0__UART7_DCE_CTS 0x79
MX7D_PAD_ECSPI2_MISO__UART7_DCE_RTS 0x79
>;
};
pinctrl_usbotg1_pwr: usbotg_pwr {
fsl,pins = <
MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x59
MX7D_PAD_SD1_CLK__SD1_CLK 0x19
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
fsl,pins = <
MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x15
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX7D_PAD_SD2_CMD__SD2_CMD 0x59
MX7D_PAD_SD2_CLK__SD2_CLK 0x19
MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59
MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59
MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59
MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x59
MX7D_PAD_SD3_CLK__SD3_CLK 0x19
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
fsl,pins = <
MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
>;
};
};
&iomuxc_lpsr {
pinctrl_wifi_clk: wificlkgrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2 0x7d
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
>;
};
};

5
arch/arm/dts/imx7s-warp.dts
View File

@ -19,6 +19,11 @@
aliases {
mmc0 = &usdhc3;
usb0 = &usbotg1;
};
chosen {
stdout-path = &uart1;
};
gpio-keys {

13
arch/arm/dts/vf-colibri.dtsi
View File

@ -60,11 +60,24 @@
status = "okay";
};
/* Ethernet */
&fec1 {
phy-mode = "rmii";
phy-handle = <&ethphy1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
max-speed = <100>;
reg = <1>;
};
};
};
&i2c0 {

1
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -26,6 +26,7 @@
#define MXC_CPU_MX7D 0x72
#define MXC_CPU_IMX8MQ 0x82
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */
#define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */
#define MXC_CPU_VF610 0xF6 /* dummy ID */

2
arch/arm/include/asm/arch-imx8/imx8-pins.h
View File

@ -8,6 +8,8 @@
#if defined(CONFIG_IMX8QXP)
#include <dt-bindings/pinctrl/pads-imx8qxp.h>
#elif defined(CONFIG_IMX8QM)
#include <dt-bindings/pinctrl/pads-imx8qm.h>
#else
#error "No pin header"
#endif

4
arch/arm/include/asm/arch-imx8/sci/sci.h
View File

@ -62,10 +62,6 @@ int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_set_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_pm_clock_rate_t *rate);
int sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk,
sc_bool_t enable, sc_bool_t autog);

3
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -134,4 +134,7 @@ int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
unsigned long reg1, unsigned long reg2);
unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
unsigned long *reg1, unsigned long reg2,
unsigned long reg3);
#endif

2
arch/arm/mach-imx/Makefile
View File

@ -204,7 +204,7 @@ endif
targets += $(addprefix ../../../,SPL spl/u-boot-spl.cfgout u-boot-dtb.cfgout u-boot.cfgout u-boot.uim spl/u-boot-nand-spl.imx)
obj-$(CONFIG_ARM64) += sip.o
obj-$(CONFIG_ARM64) += lowlevel.o sip.o
obj-$(CONFIG_MX5) += mx5/
obj-$(CONFIG_MX6) += mx6/

11
arch/arm/mach-imx/imx8/Kconfig
View File

@ -10,6 +10,11 @@ config MU_BASE_SPL
SPL runs in EL3 mode, it use MU0_A to communicate with SCU.
So we could not reuse the one in dts which is for normal U-Boot.
config IMX8QM
select IMX8
select SUPPORT_SPL
bool
config IMX8QXP
select IMX8
select SUPPORT_SPL
@ -27,8 +32,14 @@ config TARGET_IMX8QXP_MEK
select BOARD_LATE_INIT
select IMX8QXP
config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
endchoice
source "board/freescale/imx8qxp_mek/Kconfig"
source "board/freescale/imx8qm_mek/Kconfig"
endif

3
arch/arm/mach-imx/imx8/cpu.c
View File

@ -542,6 +542,8 @@ const char *get_imx8_type(u32 imxtype)
case MXC_CPU_IMX8QXP:
case MXC_CPU_IMX8QXP_A0:
return "QXP";
case MXC_CPU_IMX8QM:
return "QM";
default:
return "??";
}
@ -613,6 +615,7 @@ static const struct cpu_ops cpu_imx8_ops = {
static const struct udevice_id cpu_imx8_ids[] = {
{ .compatible = "arm,cortex-a35" },
{ .compatible = "arm,cortex-a53" },
{ }
};

7
arch/arm/mach-imx/imx8m/soc.c
View File

@ -169,6 +169,7 @@ static void imx_set_wdog_powerdown(bool enable)
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
/*
* Init timer at very early state, because sscg pll setting
* will use it
@ -180,6 +181,12 @@ int arch_cpu_init(void)
imx_set_wdog_powerdown(false);
}
if (is_imx8mq()) {
clock_enable(CCGR_OCOTP, 1);
if (readl(&ocotp->ctrl) & 0x200)
writel(0x200, &ocotp->ctrl_clr);
}
return 0;
}

22
arch/arm/mach-imx/lowlevel.S Normal file
View File

@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2019 NXP
*/
#include <linux/linkage.h>
ENTRY(lowlevel_init)
mrs x0, CurrentEL
cmp x0, #8
b.eq 1f
ret
1:
msr daifclr, #4
/* set HCR_EL2.AMO to catch SERROR */
mrs x0, hcr_el2
orr x0, x0, #0x20
msr hcr_el2, x0
isb
ret
ENDPROC(lowlevel_init)

2
arch/arm/mach-imx/mx2/Kconfig
View File

@ -17,7 +17,7 @@ config TARGET_MX25PDK
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
select CPU_ARM926EJS1
select CPU_ARM926EJS
endchoice

4
arch/arm/mach-imx/mx5/Kconfig
View File

@ -27,6 +27,10 @@ config TARGET_KP_IMX53
select DM_I2C
select DM_PMIC
select DM_SERIAL
select DM_MMC
select BLK
select DM_USB
select DM_REGULATOR
select MX53
imply CMD_DM

12
arch/arm/mach-imx/mx6/Kconfig
View File

@ -161,6 +161,18 @@ config TARGET_COLIBRI_IMX6ULL
select DM_THERMAL
select MX6ULL
config TARGET_DART_6UL
bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
select MX6ULL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_SERIAL
select DM_THERMAL
select SUPPORT_SPL
config TARGET_DHCOMIMX6
bool "dh_imx6"
select BOARD_EARLY_INIT_F

22
arch/arm/mach-imx/sip.c
View File

@ -20,3 +20,25 @@ unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
return regs.regs[0];
}
/*
* Do an SMC call to return 2 registers by having reg1 passed in by reference
*/
unsigned long call_imx_sip_ret2(unsigned long id, unsigned long reg0,
unsigned long *reg1, unsigned long reg2,
unsigned long reg3)
{
struct pt_regs regs;
regs.regs[0] = id;
regs.regs[1] = reg0;
regs.regs[2] = *reg1;
regs.regs[3] = reg2;
regs.regs[4] = reg3;
smc_call(&regs);
*reg1 = regs.regs[1];
return regs.regs[0];
}

56
board/dhelectronics/dh_imx6/dh_imx6_spl.c
View File

@ -161,18 +161,18 @@ static const struct mx6_mmdc_calibration dhcom_mmdc_calib_2x4g_800 = {
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_1066 = {
.p0_mpwldectrl0 = 0x0011000E,
.p0_mpwldectrl1 = 0x000E001B,
.p1_mpwldectrl0 = 0x00190015,
.p1_mpwldectrl1 = 0x00070018,
.p0_mpdgctrl0 = 0x42720306,
.p0_mpdgctrl1 = 0x026F0266,
.p1_mpdgctrl0 = 0x4273030A,
.p1_mpdgctrl1 = 0x02740240,
.p0_mprddlctl = 0x45393B3E,
.p1_mprddlctl = 0x403A3747,
.p0_mpwrdlctl = 0x40434541,
.p1_mpwrdlctl = 0x473E4A3B,
.p0_mpwldectrl0 = 0x001a001a,
.p0_mpwldectrl1 = 0x00260015,
.p0_mpdgctrl0 = 0x030c0320,
.p0_mpdgctrl1 = 0x03100304,
.p0_mprddlctl = 0x432e3538,
.p0_mpwrdlctl = 0x363f423d,
.p1_mpwldectrl0 = 0x0006001e,
.p1_mpwldectrl1 = 0x00050015,
.p1_mpdgctrl0 = 0x031c0324,
.p1_mpdgctrl1 = 0x030c0258,
.p1_mprddlctl = 0x3834313f,
.p1_mpwrdlctl = 0x47374a42,
};
static const struct mx6_mmdc_calibration dhcom_mmdc_calib_4x2g_800 = {
@ -482,6 +482,29 @@ static void setup_iomux_usb(void)
SETUP_IOMUX_PADS(usb_pads);
}
/* Perform DDR DRAM calibration */
static int spl_dram_perform_cal(struct mx6_ddr_sysinfo const *sysinfo)
{
int ret = 0;
#ifdef CONFIG_MX6_DDRCAL
udelay(100);
ret = mmdc_do_write_level_calibration(sysinfo);
if (ret) {
printf("DDR3: Write level calibration error [%d]\n", ret);
return ret;
}
ret = mmdc_do_dqs_calibration(sysinfo);
if (ret) {
printf("DDR3: DQS calibration error [%d]\n", ret);
return ret;
}
#endif /* CONFIG_MX6_DDRCAL */
return ret;
}
/* DRAM */
static void dhcom_spl_dram_init(void)
@ -509,8 +532,7 @@ static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
udelay(100);
mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
spl_dram_perform_cal(&dhcom_ddr_64bit);
} else if (is_cpu_type(MXC_CPU_MX6DL)) {
mx6sdl_dram_iocfg(64, &dhcom6sdl_ddr_ioregs,
@ -528,8 +550,7 @@ static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
udelay(100);
mmdc_do_dqs_calibration(&dhcom_ddr_64bit);
spl_dram_perform_cal(&dhcom_ddr_64bit);
} else if (is_cpu_type(MXC_CPU_MX6SOLO)) {
mx6sdl_dram_iocfg(32, &dhcom6sdl_ddr_ioregs,
@ -552,8 +573,7 @@ static void dhcom_spl_dram_init(void)
}
/* Perform DDR DRAM calibration */
udelay(100);
mmdc_do_dqs_calibration(&dhcom_ddr_32bit);
spl_dram_perform_cal(&dhcom_ddr_32bit);
}
}

14
board/freescale/imx8qm_mek/Kconfig Normal file
View File

@ -0,0 +1,14 @@
if TARGET_IMX8QM_MEK
config SYS_BOARD
default "imx8qm_mek"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "imx8qm_mek"
source "board/freescale/common/Kconfig"
endif

6
board/freescale/imx8qm_mek/MAINTAINERS Normal file
View File

@ -0,0 +1,6 @@
i.MX8QM MEK BOARD
M: Peng Fan <peng.fan@nxp.com>
S: Maintained
F: board/freescale/imx8qm_mek/
F: include/configs/imx8qm_mek.h
F: configs/imx8qm_mek_defconfig

8
board/freescale/imx8qm_mek/Makefile Normal file
View File

@ -0,0 +1,8 @@
#
# Copyright 2018 NXP
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8qm_mek.o
obj-$(CONFIG_SPL_BUILD) += spl.o

57
board/freescale/imx8qm_mek/README Normal file
View File

@ -0,0 +1,57 @@
U-Boot for the NXP i.MX8QM EVK board
Quick Start
===========
- Build the ARM Trusted firmware binary
- Get scfw_tcm.bin and ahab-container.img
- Build U-Boot
- Flash the binary into the SD card
- Boot
Get and Build the ARM Trusted firmware
======================================
$ git clone https://source.codeaurora.org/external/imx/imx-atf
$ cd imx-atf/
$ git checkout origin/imx_4.14.78_1.0.0_ga -b imx_4.14.78_1.0.0_ga
$ make PLAT=imx8qm bl31
Get scfw_tcm.bin and ahab-container.img
==============================
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-1.1.bin
$ chmod +x imx-sc-firmware-1.1.bin
$ ./imx-sc-firmware-1.1.bin
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.0.bin
$ chmod +x firmware-imx-8.0.bin
$ ./firmware-imx-8.0.bin
Copy the following binaries to U-Boot folder:
$ cp imx-atf/build/imx8qm/release/bl31.bin .
$ cp u-boot/u-boot.bin .
Copy the following firmwares U-Boot folder :
$ cp firmware-imx-7.6/firmware/seco/ahab-container.img .
$ cp imx-sc-firmware-0.7/mx8qm-mek-scfw-tcm.bin .
Build U-Boot
============
$ export ATF_LOAD_ADDR=0x80000000
$ export BL33_LOAD_ADDR=0x80020000
$ make imx8qm_mek_defconfig
$ make flash.bin
$ dd if=u-boot.itb of=flash.bin bs=512 seek=1984
Flash the binary into the SD card
=================================
Burn the flash.bin binary to SD card offset 32KB:
$ sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32
Boot
====
Set Boot switch SW2: 1100.

157
board/freescale/imx8qm_mek/imx8qm_mek.c Normal file
View File

@ -0,0 +1,157 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <common.h>
#include <errno.h>
#include <linux/libfdt.h>
#include <environment.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
static iomux_cfg_t uart0_pads[] = {
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
}
int board_early_init_f(void)
{
int ret;
/* Set UART0 clock root to 80 MHz */
sc_pm_clock_rate_t rate = 80000000;
/* Power up UART0 */
ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
if (ret)
return ret;
ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
if (ret)
return ret;
/* Enable UART0 clock root */
ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
if (ret)
return ret;
setup_iomux_uart();
sc_pm_set_resource_power_mode(-1, SC_R_GPIO_5, SC_PM_PW_MODE_ON);
return 0;
}
#if IS_ENABLED(CONFIG_DM_GPIO)
static void board_gpio_init(void)
{
/* TODO */
}
#else
static inline void board_gpio_init(void) {}
#endif
#if IS_ENABLED(CONFIG_FEC_MXC)
#include <miiphy.h>
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif
void build_info(void)
{
u32 sc_build = 0, sc_commit = 0;
/* Get SCFW build and commit id */
sc_misc_build_info(-1, &sc_build, &sc_commit);
if (!sc_build) {
printf("SCFW does not support build info\n");
sc_commit = 0; /* Display 0 when the build info is not supported*/
}
printf("Build: SCFW %x\n", sc_commit);
}
int checkboard(void)
{
puts("Board: iMX8QM MEK\n");
build_info();
print_bootinfo();
return 0;
}
int board_init(void)
{
/* Power up base board */
sc_pm_set_resource_power_mode(-1, SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
board_gpio_init();
return 0;
}
void detail_board_ddr_info(void)
{
puts("\nDDR ");
}
/*
* Board specific reset that is system reset.
*/
void reset_cpu(ulong addr)
{
/* TODO */
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "MEK");
env_set("board_rev", "iMX8QM");
#endif
return 0;
}

19
board/freescale/imx8qm_mek/imximage.cfg Normal file
View File

@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#define __ASSEMBLY__
/* Boot from SD, sector size 0x400 */
BOOT_FROM SD 0x400
/* SoC type IMX8QM */
SOC_TYPE IMX8QM
/* Append seco container image */
APPEND mx8qm-ahab-container.img
/* Create the 2nd container */
CONTAINER
/* Add scfw image with exec attribute */
IMAGE SCU mx8qm-mek-scfw-tcm.bin
/* Add ATF image with exec attribute */
IMAGE A35 spl/u-boot-spl.bin 0x00100000

75
board/freescale/imx8qm_mek/spl.c Normal file
View File

@ -0,0 +1,75 @@
/*
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <spl.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
struct udevice *dev;
int offset;
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
while (offset != -FDT_ERR_NOTFOUND) {
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
NULL, true);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
"nxp,imx8-pd");
}
uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
puts("Normal Boot\n");
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* Just empty function now - can't decide what to choose */
debug("%s: %s\n", __func__, name);
return 0;
}
#endif
void board_init_f(ulong dummy)
{
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
board_init_r(NULL, 0);
}

16
board/freescale/imx8qxp_mek/spl.c
View File

@ -18,7 +18,6 @@ DECLARE_GLOBAL_DATA_PTR;
void spl_board_init(void)
{
struct udevice *dev;
int offset;
uclass_find_first_device(UCLASS_MISC, &dev);
@ -27,21 +26,6 @@ void spl_board_init(void)
continue;
}
offset = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "nxp,imx8-pd");
while (offset != -FDT_ERR_NOTFOUND) {
lists_bind_fdt(gd->dm_root, offset_to_ofnode(offset),
NULL, true);
offset = fdt_node_offset_by_compatible(gd->fdt_blob, offset,
"nxp,imx8-pd");
}
uclass_find_first_device(UCLASS_POWER_DOMAIN, &dev);
for (; dev; uclass_find_next_device(&dev)) {
if (device_probe(dev))
continue;
}
arch_cpu_init();
board_early_init_f();

7
board/k+p/bootscripts/tpcboot.cmd
View File

@ -27,6 +27,12 @@ setenv miscadj "
if test '${boardsoc}' = 'imx53'; then
setenv bootargs '${bootargs} di=${dig_in} key1=${key1}';
fi;"
setenv nfsadj "
if test '${boardsoc}' = 'imx53'; then
if test '${boardtype}' = 'hsc'; then
setenv bootargs '${bootargs} dsa_core.blacklist=yes';
fi;
fi;"
setenv boot_fitImage "
setenv fdt_conf 'conf@${boardsoc}-${boardname}.dtb';
setenv itbcfg "\"#\${fdt_conf}\"";
@ -72,6 +78,7 @@ setenv boot_nfs "
if run download_kernel; then
run nfsargs;
run addip;
run nfsadj;
setenv bootargs '${bootargs}' console=${console};
run boot_fitImage;

70
board/k+p/kp_imx53/kp_imx53.c
View File

@ -13,14 +13,10 @@
#include <asm/arch/iomux-mx53.h>
#include <asm/arch/clock.h>
#include <asm/gpio.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include "kp_id_rev.h"
#define VBUS_PWR_EN IMX_GPIO_NR(7, 8)
#define PHY_nRST IMX_GPIO_NR(7, 6)
#define BOOSTER_OFF IMX_GPIO_NR(2, 23)
#define LCD_BACKLIGHT IMX_GPIO_NR(1, 1)
#define KEY1 IMX_GPIO_NR(2, 26)
@ -45,59 +41,6 @@ int dram_init_banksize(void)
return 0;
}
#ifdef CONFIG_USB_EHCI_MX5
int board_ehci_hcd_init(int port)
{
gpio_request(VBUS_PWR_EN, "VBUS_PWR_EN");
gpio_direction_output(VBUS_PWR_EN, 1);
return 0;
}
#endif
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[] = {
{MMC_SDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1; /* eMMC is always present */
}
#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
PAD_CTL_DSE_HIGH)
int board_mmc_init(bd_t *bis)
{
int ret;
static const iomux_v3_cfg_t sd3_pads[] = {
NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
SD_CMD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
};
esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
imx_iomux_v3_setup_multiple_pads(sd3_pads, ARRAY_SIZE(sd3_pads));
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
if (ret)
return ret;
return 0;
}
#endif
static int power_init(void)
{
struct udevice *dev;
@ -168,17 +111,6 @@ int board_init(void)
return 0;
}
void eth_phy_reset(void)
{
gpio_request(PHY_nRST, "PHY_nRST");
gpio_direction_output(PHY_nRST, 1);
udelay(50);
gpio_set_value(PHY_nRST, 0);
udelay(400);
gpio_set_value(PHY_nRST, 1);
udelay(50);
}
void board_disable_display(void)
{
gpio_request(LCD_BACKLIGHT, "LCD_BACKLIGHT");
@ -210,8 +142,6 @@ int board_late_init(void)
if (ret)
printf("Error %d reading EEPROM content!\n", ret);
eth_phy_reset();
show_eeprom();
read_board_id();

42
board/technexion/pico-imx7d/pico-imx7d.c
View File

@ -13,10 +13,8 @@
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_esdhc.h>
#include <i2c.h>
#include <miiphy.h>
#include <mmc.h>
#include <netdev.h>
#include <usb.h>
#include <power/pmic.h>
@ -28,9 +26,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
@ -126,20 +121,6 @@ static iomux_v3_cfg_t const uart5_pads[] = {
MX7D_PAD_I2C4_SDA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec1_pads[] = {
MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
@ -165,7 +146,7 @@ static iomux_v3_cfg_t const fec1_pads[] = {
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
gpio_request(FEC1_RST_GPIO, "phy_rst");
gpio_direction_output(FEC1_RST_GPIO, 0);
udelay(500);
gpio_set_value(FEC1_RST_GPIO, 1);
@ -224,25 +205,6 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
}
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
/* Assume uSDHC3 emmc is always present */
return 1;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(
usdhc3_emmc_pads, ARRAY_SIZE(usdhc3_emmc_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
int board_early_init_f(void)
{
setup_iomux_uart();
@ -291,6 +253,8 @@ static iomux_v3_cfg_t const lcd_pads[] = {
void setup_lcd(void)
{
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
gpio_request(IMX_GPIO_NR(1, 11), "lcd_brightness");
gpio_request(IMX_GPIO_NR(1, 6), "lcd_enable");
/* Set Brightness to high */
gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
/* Set LCD enable to high */

38
board/technexion/pico-imx7d/spl.c
View File

@ -5,11 +5,15 @@
* Author: Richard Hu <richard.hu@technexion.com>
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch-mx7/mx7-ddr.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/gpio.h>
#include <fsl_esdhc.h>
#include <spl.h>
#if defined(CONFIG_SPL_BUILD)
@ -119,4 +123,38 @@ void board_init_f(ulong dummy)
void reset_cpu(ulong addr)
{
}
#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
static iomux_v3_cfg_t const usdhc3_pads[] = {
MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static struct fsl_esdhc_cfg usdhc_cfg[1] = {
{USDHC3_BASE_ADDR},
};
int board_mmc_getcd(struct mmc *mmc)
{
/* Assume uSDHC3 emmc is always present */
return 1;
}
int board_mmc_init(bd_t *bis)
{
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
}
#endif

225
board/toradex/colibri-imx6ull/colibri-imx6ull.c
View File

@ -1,8 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Toradex AG
* Copyright (C) 2018-2019 Toradex AG
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
@ -14,47 +15,30 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <dm/platform_data/serial_mxc.h>
#include <fdt_support.h>
#include <fsl_esdhc.h>
#include <imx_thermal.h>
#include <jffs2/load_kernel.h>
#include <linux/sizes.h>
#include <mmc.h>
#include <miiphy.h>
#include <mtd_node.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include "../common/tdx-common.h"
#include "../common/tdx-cfg-block.h"
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm)
#define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm)
#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \
PAD_CTL_DSE_48ohm)
#define MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR 0x2290040
#define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP)
#define USB_CDET_GPIO IMX_GPIO_NR(7, 14)
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@ -62,56 +46,13 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
};
#ifdef CONFIG_FSL_ESDHC
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#endif
static iomux_v3_cfg_t const usb_cdet_pads[] = {
MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const gpmi_pads[] = {
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
};
static void setup_gpmi_nand(void)
{
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
}
#endif
#endif /* CONFIG_NAND_MXS */
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
@ -168,100 +109,24 @@ static int setup_lcd(void)
#endif
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
}
#endif
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
#ifdef CONFIG_FSL_ESDHC
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC1_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
}
return ret;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/* USDHC1 is mmc0 */
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
ARRAY_SIZE(usdhc1_pads));
gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers"
"(%d) than supported by the board\n", i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
setup_iomux_fec();
/* provide the PHY clock from the i.MX 6 */
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret)
return ret;
/* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */
/* Use 50M anatop REF_CLK and output it on ENET2_TX_CLK */
clrsetbits_le32(&iomuxc_regs->gpr[1],
IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
/* give new Ethernet PHY power save mode circuitry time to settle */
mdelay(300);
return 0;
}
@ -271,14 +136,7 @@ int board_phy_config(struct phy_device *phydev)
phydev->drv->config(phydev);
return 0;
}
#endif
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
#endif /* CONFIG_FEC_MXC */
int board_init(void)
{
@ -297,11 +155,6 @@ int board_init(void)
setup_lcd();
#endif
#ifdef CONFIG_USB_EHCI_MX6
imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
#endif
return 0;
}
@ -317,10 +170,23 @@ static const struct boot_mode board_boot_modes[] = {
int board_late_init(void)
{
int minc, maxc;
if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL)
#ifdef CONFIG_TDX_CFG_BLOCK
/*
* If we have a valid config block and it says we are a module with
* Wi-Fi/Bluetooth make sure we use the -wifi device tree.
*/
if (tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT_IT ||
tdx_hw_tag.prodid == COLIBRI_IMX6ULL_WIFI_BT)
env_set("variant", "-wifi");
#endif
/*
* Disable output driver of PAD CCM_PMIC_STBY_REQ. This prevents the
* SOC to request for a lower voltage during sleep. This is necessary
* because the voltage is changing too slow for the SOC to wake up
* properly.
*/
__raw_writel(0x8080, MX6_PAD_SNVS_PMIC_STBY_REQ_ADDR);
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
@ -362,41 +228,6 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
static iomux_v3_cfg_t const usb_otg2_pads[] = {
MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_ehci_hcd_init(int port)
{
switch (port) {
case 0:
break;
case 1:
imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
ARRAY_SIZE(usb_otg2_pads));
break;
default:
return -EINVAL;
}
return 0;
}
int board_usb_phy_mode(int port)
{
switch (port) {
case 0:
if (gpio_get_value(USB_CDET_GPIO))
return USB_INIT_DEVICE;
else
return USB_INIT_HOST;
case 1:
default:
return USB_INIT_HOST;
}
}
#endif
static struct mxc_serial_platdata mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = 1,

2
board/toradex/colibri_vf/MAINTAINERS
View File

@ -1,7 +1,7 @@
Colibri VFxx
M: Stefan Agner <stefan.agner@toradex.com>
W: http://developer.toradex.com/software/linux/linux-software
W: https://www.toradex.com/community
W: https://www.toradex.com/community
S: Maintained
F: board/toradex/colibri_vf/
F: include/configs/colibri_vf.h

89
board/toradex/common/tdx-cfg-block.c
View File

@ -1,12 +1,14 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2016 Toradex, Inc.
* Copyright (c) 2016-2019 Toradex, Inc.
*/
#include <common.h>
#include "tdx-cfg-block.h"
#if defined(CONFIG_TARGET_APALIS_IMX6) || defined(CONFIG_TARGET_COLIBRI_IMX6)
#if defined(CONFIG_TARGET_APALIS_IMX6) || \
defined(CONFIG_TARGET_COLIBRI_IMX6) || \
defined(CONFIG_TARGET_COLIBRI_IMX8QXP)
#include <asm/arch/sys_proto.h>
#else
#define is_cpu_type(cpu) (0)
@ -92,12 +94,22 @@ const char * const toradex_modules[] = {
[34] = "Apalis TK1 2GB",
[35] = "Apalis iMX6 Dual 1GB IT",
[36] = "Colibri iMX6ULL 256MB",
[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / Bluetooth",
[38] = "Colibri iMX8X",
[37] = "Apalis iMX8 QuadMax 4GB Wi-Fi / BT IT",
[38] = "Colibri iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
[39] = "Colibri iMX7 Dual 1GB (eMMC)",
[40] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth IT",
[40] = "Colibri iMX6ULL 512MB Wi-Fi / BT IT",
[41] = "Colibri iMX7 Dual 512MB EPDC",
[42] = "Apalis TK1 4GB",
[43] = "Colibri T20 512MB IT SETEK",
[44] = "Colibri iMX6ULL 512MB IT",
[45] = "Colibri iMX6ULL 512MB Wi-Fi / Bluetooth",
[46] = "Apalis iMX8 QuadXPlus 2GB Wi-Fi / BT IT",
[47] = "Apalis iMX8 QuadMax 4GB IT",
[48] = "Apalis iMX8 QuadPlus 2GB Wi-Fi / BT",
[49] = "Apalis iMX8 QuadPlus 2GB",
[50] = "Colibri iMX8 QuadXPlus 2GB IT",
[51] = "Colibri iMX8 DualX 1GB Wi-Fi / Bluetooth",
[52] = "Colibri iMX8 DualX 1GB",
};
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
@ -277,6 +289,9 @@ static int get_cfgblock_interactive(void)
char it = 'n';
int len;
/* Unknown module by default */
tdx_hw_tag.prodid = 0;
if (cpu_is_pxa27x())
sprintf(message, "Is the module the 312 MHz version? [y/N] ");
else
@ -287,34 +302,56 @@ static int get_cfgblock_interactive(void)
soc = env_get("soc");
if (!strcmp("mx6", soc)) {
#ifdef CONFIG_MACH_TYPE
if (it == 'y' || it == 'Y')
#ifdef CONFIG_TARGET_APALIS_IMX6
if (it == 'y' || it == 'Y') {
if (is_cpu_type(MXC_CPU_MX6Q))
tdx_hw_tag.prodid = APALIS_IMX6Q_IT;
else
tdx_hw_tag.prodid = APALIS_IMX6D_IT;
else
} else {
if (is_cpu_type(MXC_CPU_MX6Q))
tdx_hw_tag.prodid = APALIS_IMX6Q;
else
tdx_hw_tag.prodid = APALIS_IMX6D;
#else
if (it == 'y' || it == 'Y')
}
#elif CONFIG_TARGET_COLIBRI_IMX6
if (it == 'y' || it == 'Y') {
if (is_cpu_type(MXC_CPU_MX6DL))
tdx_hw_tag.prodid = COLIBRI_IMX6DL_IT;
else
else if (is_cpu_type(MXC_CPU_MX6SOLO))
tdx_hw_tag.prodid = COLIBRI_IMX6S_IT;
else
} else {
if (is_cpu_type(MXC_CPU_MX6DL))
tdx_hw_tag.prodid = COLIBRI_IMX6DL;
else
else if (is_cpu_type(MXC_CPU_MX6SOLO))
tdx_hw_tag.prodid = COLIBRI_IMX6S;
#endif /* CONFIG_MACH_TYPE */
} else if (!strcmp("imx7d", soc)) {
}
#elif CONFIG_TARGET_COLIBRI_IMX6ULL
char wb = 'n';
sprintf(message, "Does the module have Wi-Fi / Bluetooth? " \
"[y/N] ");
len = cli_readline(message);
wb = console_buffer[0];
if (it == 'y' || it == 'Y') {
if (wb == 'y' || wb == 'Y')
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT_IT;
else
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_IT;
} else {
if (wb == 'y' || wb == 'Y')
tdx_hw_tag.prodid = COLIBRI_IMX6ULL_WIFI_BT;
else
tdx_hw_tag.prodid = COLIBRI_IMX6ULL;
}
#endif
} else if (!strcmp("imx7d", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7D;
} else if (!strcmp("imx7s", soc)) {
else if (!strcmp("imx7s", soc))
tdx_hw_tag.prodid = COLIBRI_IMX7S;
} else if (!strcmp("tegra20", soc)) {
else if (is_cpu_type(MXC_CPU_IMX8QXP))
tdx_hw_tag.prodid = COLIBRI_IMX8QXP_WIFI_BT_IT;
else if (!strcmp("tegra20", soc)) {
if (it == 'y' || it == 'Y')
if (gd->ram_size == 0x10000000)
tdx_hw_tag.prodid = COLIBRI_T20_256MB_IT;
@ -330,8 +367,9 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = COLIBRI_PXA270_312MHZ;
else
tdx_hw_tag.prodid = COLIBRI_PXA270_520MHZ;
}
#ifdef CONFIG_MACH_TYPE
} else if (!strcmp("tegra30", soc)) {
else if (!strcmp("tegra30", soc)) {
if (CONFIG_MACH_TYPE == MACH_TYPE_APALIS_T30) {
if (it == 'y' || it == 'Y')
tdx_hw_tag.prodid = APALIS_T30_IT;
@ -346,8 +384,9 @@ static int get_cfgblock_interactive(void)
else
tdx_hw_tag.prodid = COLIBRI_T30;
}
}
#endif /* CONFIG_MACH_TYPE */
} else if (!strcmp("tegra124", soc)) {
else if (!strcmp("tegra124", soc)) {
tdx_hw_tag.prodid = APALIS_TK1_2GB;
} else if (!strcmp("vf500", soc)) {
if (it == 'y' || it == 'Y')
@ -359,7 +398,9 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.prodid = COLIBRI_VF61_IT;
else
tdx_hw_tag.prodid = COLIBRI_VF61;
} else {
}
if (!tdx_hw_tag.prodid) {
printf("Module type not detectable due to unknown SoC\n");
return -1;
}
@ -373,7 +414,7 @@ static int get_cfgblock_interactive(void)
tdx_hw_tag.ver_minor = console_buffer[2] - '0';
tdx_hw_tag.ver_assembly = console_buffer[3] - 'A';
if (cpu_is_pxa27x() && (tdx_hw_tag.ver_major == 1))
if (cpu_is_pxa27x() && tdx_hw_tag.ver_major == 1)
tdx_hw_tag.prodid -= (COLIBRI_PXA270_312MHZ -
COLIBRI_PXA270_V1_312MHZ);
@ -441,7 +482,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
* On NAND devices, recreation is only allowed if the page is
* empty (config block invalid...)
*/
printf("NAND erase block %d need to be erased before creating a Toradex config block\n",
printf("NAND erase block %d need to be erased before creating" \
" a Toradex config block\n",
CONFIG_TDX_CFG_BLOCK_OFFSET /
get_nand_dev_by_index(0)->erasesize);
goto out;
@ -450,7 +492,8 @@ static int do_cfgblock_create(cmd_tbl_t *cmdtp, int flag, int argc,
* On NOR devices, recreation is only allowed if the sector is
* empty and write protection is off (config block invalid...)
*/
printf("NOR sector at offset 0x%02x need to be erased and unprotected before creating a Toradex config block\n",
printf("NOR sector at offset 0x%02x need to be erased and " \
"unprotected before creating a Toradex config block\n",
CONFIG_TDX_CFG_BLOCK_OFFSET);
goto out;
#else

32
board/toradex/common/tdx-cfg-block.h
View File

@ -25,42 +25,54 @@ enum {
COLIBRI_PXA270_V1_520MHZ,
COLIBRI_PXA320,
COLIBRI_PXA300,
COLIBRI_PXA310,
COLIBRI_PXA310, /* 5 */
COLIBRI_PXA320_IT,
COLIBRI_PXA300_XT,
COLIBRI_PXA270_312MHZ,
COLIBRI_PXA270_520MHZ,
COLIBRI_VF50, /* not currently on sale */
COLIBRI_VF61,
COLIBRI_VF50, /* 10 */
COLIBRI_VF61, /* not currently on sale */
COLIBRI_VF61_IT,
COLIBRI_VF50_IT,
COLIBRI_IMX6S,
COLIBRI_IMX6DL,
COLIBRI_IMX6DL, /* 15 */
COLIBRI_IMX6S_IT,
COLIBRI_IMX6DL_IT,
/* 18 */
/* 19 */
COLIBRI_T20_256MB = 20,
COLIBRI_T20_512MB,
COLIBRI_T20_512MB_IT,
COLIBRI_T30,
COLIBRI_T20_256MB_IT,
APALIS_T30_2GB,
APALIS_T30_2GB, /* 25 */
APALIS_T30_1GB,
APALIS_IMX6Q,
APALIS_IMX6Q_IT,
APALIS_IMX6D,
COLIBRI_T30_IT,
COLIBRI_T30_IT, /* 30 */
APALIS_T30_IT,
COLIBRI_IMX7S,
COLIBRI_IMX7D,
APALIS_TK1_2GB,
APALIS_IMX6D_IT,
APALIS_IMX6D_IT, /* 35 */
COLIBRI_IMX6ULL,
APALIS_IMX8QM, /* 37 */
COLIBRI_IMX8X,
APALIS_IMX8QM_WIFI_BT_IT,
COLIBRI_IMX8QXP_WIFI_BT_IT,
COLIBRI_IMX7D_EMMC,
COLIBRI_IMX6ULL_WIFI_BT_IT, /* 40 */
COLIBRI_IMX7D_EPDC,
APALIS_TK1_4GB,
APALIS_TK1_4GB, /* not currently on sale */
COLIBRI_T20_512MB_IT_SETEK,
COLIBRI_IMX6ULL_IT,
COLIBRI_IMX6ULL_WIFI_BT, /* 45 */
APALIS_IMX8QXP_WIFI_BT_IT,
APALIS_IMX8QM_IT,
APALIS_IMX8QP_WIFI_BT,
APALIS_IMX8QP,
COLIBRI_IMX8QXP_IT, /* 50 */
COLIBRI_IMX8DX_WIFI_BT,
COLIBRI_IMX8DX,
};
extern const char * const toradex_modules[];

12
board/variscite/dart_6ul/Kconfig Normal file
View File

@ -0,0 +1,12 @@
if TARGET_DART_6UL
config SYS_BOARD
default "dart_6ul"
config SYS_VENDOR
default "variscite"
config SYS_CONFIG_NAME
default "dart_6ul"
endif

8
board/variscite/dart_6ul/MAINTAINERS Normal file
View File

@ -0,0 +1,8 @@
MX6UL_DART BOARD
M: Parthiban Nallathambi <parthitce@gmail.com>
S: Maintained
F: arch/arm/dts/imx6ull-dart-6ul.dts
F: arch/arm/dts/imx6ull-dart-6ul.dtsi
F: board/variscite/dart_6ul/
F: configs/variscite_dart6ul_defconfig
F: include/configs/dart_6ul.h

4
board/variscite/dart_6ul/Makefile Normal file
View File

@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := dart_6ul.o
obj-$(CONFIG_SPL_BUILD) += spl.o

41
board/variscite/dart_6ul/README Normal file
View File

@ -0,0 +1,41 @@
How to use U-Boot on variscite DART-6UL Evaluation Kit
------------------------------------------------------
- Configure and build U-Boot for DART-6UL iMX6ULL:
$ make mrproper
$ make variscite_dart6ul_defconfig
$ make
This will generate SPL and u-boot-dtb.img images.
Boot from MMC/SD:
- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Boot mode settings:
Boot switch position: SW1 -> 0
SW2 -> 0
Boot from eMMC:
- if bootpart is not enabled by default, to enable under Linux
echo 0 >/sys/block/mmcblk1boot0/force_ro
mmc bootpart enable 1 1 /dev/mmcblk1boot0
- Flash the SPL and u-boot-dtb.img to mmcblk1boot0
$ sudo dd if=SPL of=/dev/mmcblk1boot0 bs=1k seek=1; sync
$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk1boot0 bs=1k seek=69; sync
- Boot mode settings:
Boot switch position: SW1 -> 0
SW2 -> 1
- Connect the Serial cable to UART0 and the PC for the console.
- Insert the micro SD card in the board and power it up.
- U-Boot messages should come up.

228
board/variscite/dart_6ul/dart_6ul.c Normal file
View File

@ -0,0 +1,228 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2019 Variscite Ltd.
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc.h>
#include <linux/bitops.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
#ifdef CONFIG_NAND_MXS
#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
PAD_CTL_SRE_FAST)
#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
};
static void setup_gpmi_nand(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
clrbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
/*
* config gpmi and bch clock to 100 MHz
* bch/gpmi select PLL2 PFD2 400M
* 100M = 400M / 4
*/
clrbits_le32(&mxc_ccm->cscmr1,
MXC_CCM_CSCMR1_BCH_CLK_SEL |
MXC_CCM_CSCMR1_GPMI_CLK_SEL);
clrsetbits_le32(&mxc_ccm->cscdr1,
MXC_CCM_CSCDR1_BCH_PODF_MASK |
MXC_CCM_CSCDR1_GPMI_PODF_MASK,
(3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
(3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
/* enable gpmi and bch clock gating */
setbits_le32(&mxc_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
/* enable apbh clock gating */
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
}
#endif
#ifdef CONFIG_FEC_MXC
#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
PAD_CTL_SRE_FAST)
#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_ODE)
/*
* pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
* be used for ENET1 or ENET2, cannot be used for both.
*/
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const fec2_pads[] = {
MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static void setup_iomux_fec(int fec_id)
{
if (fec_id == 0)
imx_iomux_v3_setup_multiple_pads(fec1_pads,
ARRAY_SIZE(fec1_pads));
else
imx_iomux_v3_setup_multiple_pads(fec2_pads,
ARRAY_SIZE(fec2_pads));
}
int board_eth_init(bd_t *bis)
{
int ret = 0;
ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
#if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
/* USB Ethernet Gadget */
usb_eth_initialize(bis);
#endif
return ret;
}
static int setup_fec(int fec_id)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
if (fec_id == 0) {
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
} else {
/*
* Use 50M anatop loopback REF_CLK2 for ENET2,
* clear gpr1[14], set gpr1[18].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
}
ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/*
* Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
* 50 MHz RMII clock mode.
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif /* CONFIG_FEC_MXC */
int board_early_init_f(void)
{
setup_iomux_fec(CONFIG_FEC_ENET_DEV);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec(CONFIG_FEC_ENET_DEV);
#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
return 0;
}
int checkboard(void)
{
puts("Board: Variscite DART-6UL Evaluation Kit\n");
return 0;
}

215
board/variscite/dart_6ul/spl.c Normal file
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@ -0,0 +1,215 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015-2019 Variscite Ltd.
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
#include <common.h>
#include <spl.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <fsl_esdhc.h>
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000008,
.dram_sdqs0 = 0x00000038,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00000000,
.p0_mpdgctrl0 = 0x414C0158,
.p0_mprddlctl = 0x40403A3A,
.p0_mpwrdlctl = 0x40405A56,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
};
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 800,
.density = 4,
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0xFFFFFFFF, &ccm->CCGR7);
/* Enable Audio Clock for SOM codec */
writel(0x01130100, (long *)CCM_CCOSR);
}
static void spl_dram_init(void)
{
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifndef CONFIG_NAND_MXS
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#endif
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,
},
#ifndef CONFIG_NAND_MXS
{
.esdhc_base = USDHC2_BASE_ADDR,
.max_bus_width = 8,
},
#endif
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
#ifndef CONFIG_NAND_MXS
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
#endif
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
void board_init_f(ulong dummy)
{
/* setup AIPS and disable watchdog */
arch_cpu_init();
ccgr_init();
/* setup GP timer */
timer_init();
setup_iomux_uart();
/* iomux and setup of i2c */
board_early_init_f();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

6
board/warp7/warp7.c
View File

@ -14,7 +14,6 @@
#include <asm/io.h>
#include <common.h>
#include <asm/arch/crm_regs.h>
#include <usb.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
@ -128,11 +127,6 @@ int checkboard(void)
return 0;
}
int board_usb_phy_mode(int port)
{
return USB_INIT_DEVICE;
}
int board_late_init(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;

18
configs/colibri-imx6ull_defconfig
View File

@ -1,6 +1,5 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
# CONFIG_SPL_SYS_THUMB_BUILD is not set
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_TARGET_COLIBRI_IMX6ULL=y
@ -16,24 +15,27 @@ CONFIG_VERSION_VARIABLE=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SYS_PROMPT="Colibri iMX6ULL # "
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_CMD_ASKENV=y
CONFIG_CRC32_VERIFY=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_DFU=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_NAND_TORTURE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:512k(mx6ull-bcb),1536k(u-boot1)ro,1536k(u-boot2)ro,512k(u-boot-env),-(ubi)"
@ -48,6 +50,7 @@ CONFIG_DFU_NAND=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
CONFIG_NAND=y
@ -55,26 +58,25 @@ CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
# CONFIG_SPL_SERIAL_PRESENT is not set
CONFIG_DM_SERIAL=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Toradex"
CONFIG_USB_GADGET_VENDOR_NUM=0x1b67
CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_FUNCTION_SDP=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
# CONFIG_EFI_LOADER is not set

1
configs/colibri_imx6_defconfig
View File

@ -41,6 +41,7 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_UUID=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y

4
configs/imx6q_logic_defconfig
View File

@ -55,7 +55,10 @@ CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:2m(spl),2m(uboot),1m(env),16m(kernel),1m(dtb),-(fs)"
CONFIG_CMD_UBI=y
CONFIG_DEFAULT_DEVICE_TREE="imx6q-logicpd"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_ENV_FAT_INTERFACE="mmc"
CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_PCF8575_GPIO=y
CONFIG_LED=y
@ -85,4 +88,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FAT_WRITE=y

75
configs/imx8qm_mek_defconfig Normal file
View File

@ -0,0 +1,75 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_TARGET_IMX8QM_MEK=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_NR_DRAM_BANKS=3
CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/imx8qm_mek/imximage.cfg"
CONFIG_BOOTDELAY=3
CONFIG_LOG=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK=y
CONFIG_CLK_IMX8=y
CONFIG_CPU=y
CONFIG_DM_GPIO=y
CONFIG_MXC_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
CONFIG_MISC=y
CONFIG_DM_MMC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC_SHARE_MDIO=y
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPL_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_SPL_TINY_MEMSET=y
# CONFIG_EFI_LOADER is not set

4
configs/imx8qxp_mek_defconfig
View File

@ -4,7 +4,7 @@ CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_TARGET_IMX8QXP_MEK=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
@ -23,10 +23,12 @@ CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_CPU=y
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y

3
configs/kp_imx53_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="imx53-kp"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_I2C_DEFAULT_BUS_NUMBER=0x1
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_SMSC=y
CONFIG_FEC_MXC=y
@ -39,8 +40,10 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_PMIC_MC34708=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=2
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y

1
configs/m53menlo_defconfig
View File

@ -59,6 +59,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_RTC_M41T62=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

1
configs/mx51evk_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_MII=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

1
configs/mx53loco_defconfig
View File

@ -26,6 +26,7 @@ CONFIG_DWC_AHSATA=y
CONFIG_FSL_ESDHC=y
CONFIG_MII=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y

4
configs/mx53ppd_defconfig
View File

@ -45,7 +45,9 @@ CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX5=y
CONFIG_RTC_S35392A=y
CONFIG_USB=y
CONFIG_VIDEO_IPUV3=y
CONFIG_USB_EHCI_MX5=y
CONFIG_USB_STORAGE=y
CONFIG_VIDEO=y
CONFIG_VIDEO_IPUV3=y
# CONFIG_VIDEO_SW_CURSOR is not set
CONFIG_IMX_WATCHDOG=y

1
configs/omap35_logic_defconfig
View File

@ -31,6 +31,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"

1
configs/omap35_logic_somlv_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"

1
configs/omap3_logic_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs)"

1
configs/omap3_logic_somlv_defconfig
View File

@ -30,6 +30,7 @@ CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(MLO),1792k(u-boot),128k(spl-os),128k(u-boot-env),6m(kernel),-(fs);physmap-flash.0:-(nor)"

7
configs/pico-hobbit-imx7d_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-hobbit"
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_I2C_SUPPORT=y
@ -26,10 +28,14 @@ CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_GPIO=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_DM_MMC=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -59,4 +65,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y

7
configs/pico-imx7d_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="ask"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_I2C_SUPPORT=y
@ -26,6 +28,10 @@ CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_DFU=y
@ -59,4 +65,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y

7
configs/pico-pi-imx7d_defconfig
View File

@ -16,6 +16,8 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-pico-pi"
CONFIG_BOUNCE_BUFFER=y
CONFIG_SPL_TEXT_BASE=0x00911000
CONFIG_SPL_I2C_SUPPORT=y
@ -26,10 +28,14 @@ CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_CMD_BOOTMENU=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7=y
CONFIG_DM_GPIO=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_WRITE_SIZE=0x20000
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_DM_MMC=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
@ -59,4 +65,3 @@ CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_VIDEO=y
CONFIG_OF_LIBFDT=y

1
configs/usbarmory_defconfig
View File

@ -15,4 +15,5 @@ CONFIG_CMD_USB=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_ESDHC=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_OF_LIBFDT=y

55
configs/variscite_dart6ul_defconfig Normal file
View File

@ -0,0 +1,55 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x86000000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_TARGET_DART_6UL=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
# CONFIG_CMD_DEKBLOB is not set
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_NET=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-dart-6ul"
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_ESDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Variscite"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_LZO=y

3
configs/warp7_bl33_defconfig
View File

@ -38,7 +38,10 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y

3
configs/warp7_defconfig
View File

@ -47,8 +47,11 @@ CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_PFUZE100=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_DM_SERIAL=y
CONFIG_OPTEE=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_MXC_USB_OTG_HACTIVE=y
CONFIG_USB_GADGET=y

5
drivers/clk/imx/Makefile
View File

@ -3,3 +3,8 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
ifdef CONFIG_CLK_IMX8
obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
endif

308
drivers/clk/imx/clk-imx8.c
View File

@ -13,304 +13,23 @@
#include <dt-bindings/soc/imx_rsrc.h>
#include <misc.h>
struct imx8_clks {
ulong id;
const char *name;
};
#include "clk-imx8.h"
#if CONFIG_IS_ENABLED(CMD_CLK)
static struct imx8_clks imx8_clk_names[] = {
{ IMX8QXP_A35_DIV, "A35_DIV" },
{ IMX8QXP_I2C0_CLK, "I2C0" },
{ IMX8QXP_I2C1_CLK, "I2C1" },
{ IMX8QXP_I2C2_CLK, "I2C2" },
{ IMX8QXP_I2C3_CLK, "I2C3" },
{ IMX8QXP_UART0_CLK, "UART0" },
{ IMX8QXP_UART1_CLK, "UART1" },
{ IMX8QXP_UART2_CLK, "UART2" },
{ IMX8QXP_UART3_CLK, "UART3" },
{ IMX8QXP_SDHC0_CLK, "SDHC0" },
{ IMX8QXP_SDHC1_CLK, "SDHC1" },
{ IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
{ IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
{ IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
{ IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
{ IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
{ IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
};
#endif
static ulong imx8_clk_get_rate(struct clk *clk)
__weak ulong imx8_clk_get_rate(struct clk *clk)
{
sc_pm_clk_t pm_clk;
ulong rate;
u16 resource;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_A35_DIV:
resource = SC_R_A35;
pm_clk = SC_PM_CLK_CPU;
break;
case IMX8QXP_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC0_IPG_CLK:
case IMX8QXP_SDHC0_CLK:
case IMX8QXP_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC1_IPG_CLK:
case IMX8QXP_SDHC1_CLK:
case IMX8QXP_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_IPG_CLK:
case IMX8QXP_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET0_IPG_CLK:
case IMX8QXP_ENET0_AHB_CLK:
case IMX8QXP_ENET0_REF_DIV:
case IMX8QXP_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET1_IPG_CLK:
case IMX8QXP_ENET1_AHB_CLK:
case IMX8QXP_ENET1_REF_DIV:
case IMX8QXP_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QXP_UART0_IPG_CLK ||
clk->id >= IMX8QXP_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return rate;
}
static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
{
sc_pm_clk_t pm_clk;
u32 new_rate = rate;
u16 resource;
int ret;
debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
switch (clk->id) {
case IMX8QXP_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC0_IPG_CLK:
case IMX8QXP_SDHC0_CLK:
case IMX8QXP_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC1_SEL:
case IMX8QXP_SDHC0_SEL:
return 0;
case IMX8QXP_SDHC1_IPG_CLK:
case IMX8QXP_SDHC1_CLK:
case IMX8QXP_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET0_IPG_CLK:
case IMX8QXP_ENET0_AHB_CLK:
case IMX8QXP_ENET0_REF_DIV:
case IMX8QXP_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET1_IPG_CLK:
case IMX8QXP_ENET1_AHB_CLK:
case IMX8QXP_ENET1_REF_DIV:
case IMX8QXP_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QXP_UART0_IPG_CLK ||
clk->id >= IMX8QXP_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return new_rate;
}
static int __imx8_clk_enable(struct clk *clk, bool enable)
{
sc_pm_clk_t pm_clk;
u16 resource;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC0_IPG_CLK:
case IMX8QXP_SDHC0_CLK:
case IMX8QXP_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC1_IPG_CLK:
case IMX8QXP_SDHC1_CLK:
case IMX8QXP_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET0_IPG_CLK:
case IMX8QXP_ENET0_AHB_CLK:
case IMX8QXP_ENET0_REF_DIV:
case IMX8QXP_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET1_IPG_CLK:
case IMX8QXP_ENET1_AHB_CLK:
case IMX8QXP_ENET1_REF_DIV:
case IMX8QXP_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QXP_UART0_IPG_CLK ||
clk->id >= IMX8QXP_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return 0;
}
__weak ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
{
return 0;
}
__weak int __imx8_clk_enable(struct clk *clk, bool enable)
{
return -ENOTSUPP;
}
static int imx8_clk_disable(struct clk *clk)
{
return __imx8_clk_enable(clk, 0);
@ -336,7 +55,7 @@ int soc_clk_dump(void)
printf("Clk\t\tHz\n");
for (i = 0; i < ARRAY_SIZE(imx8_clk_names); i++) {
for (i = 0; i < num_clks; i++) {
clk.id = imx8_clk_names[i].id;
ret = clk_request(dev, &clk);
if (ret < 0) {
@ -382,6 +101,7 @@ static int imx8_clk_probe(struct udevice *dev)
static const struct udevice_id imx8_clk_ids[] = {
{ .compatible = "fsl,imx8qxp-clk" },
{ .compatible = "fsl,imx8qm-clk" },
{ },
};

19
drivers/clk/imx/clk-imx8.h Normal file
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@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Peng Fan <peng.fan@nxp.com>
*/
struct imx8_clks {
ulong id;
const char *name;
};
#if CONFIG_IS_ENABLED(CMD_CLK)
extern struct imx8_clks imx8_clk_names[];
extern int num_clks;
#endif
ulong imx8_clk_get_rate(struct clk *clk);
ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate);
int __imx8_clk_enable(struct clk *clk, bool enable);

307
drivers/clk/imx/clk-imx8qm.c Normal file
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@ -0,0 +1,307 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2018 NXP
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/clock.h>
#include <dt-bindings/clock/imx8qm-clock.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <misc.h>
#include "clk-imx8.h"
#if CONFIG_IS_ENABLED(CMD_CLK)
struct imx8_clks imx8_clk_names[] = {
{ IMX8QM_A53_DIV, "A53_DIV" },
{ IMX8QM_UART0_CLK, "UART0" },
{ IMX8QM_UART1_CLK, "UART1" },
{ IMX8QM_UART2_CLK, "UART2" },
{ IMX8QM_UART3_CLK, "UART3" },
{ IMX8QM_SDHC0_CLK, "SDHC0" },
{ IMX8QM_SDHC1_CLK, "SDHC1" },
{ IMX8QM_SDHC2_CLK, "SDHC2" },
{ IMX8QM_ENET0_AHB_CLK, "ENET0_AHB" },
{ IMX8QM_ENET0_IPG_CLK, "ENET0_IPG" },
{ IMX8QM_ENET0_REF_DIV, "ENET0_REF" },
{ IMX8QM_ENET0_PTP_CLK, "ENET0_PTP" },
{ IMX8QM_ENET1_AHB_CLK, "ENET1_AHB" },
{ IMX8QM_ENET1_IPG_CLK, "ENET1_IPG" },
{ IMX8QM_ENET1_REF_DIV, "ENET1_REF" },
{ IMX8QM_ENET1_PTP_CLK, "ENET1_PTP" },
};
int num_clks = ARRAY_SIZE(imx8_clk_names);
#endif
ulong imx8_clk_get_rate(struct clk *clk)
{
sc_pm_clk_t pm_clk;
ulong rate;
u16 resource;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_A53_DIV:
resource = SC_R_A53;
pm_clk = SC_PM_CLK_CPU;
break;
case IMX8QM_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC0_IPG_CLK:
case IMX8QM_SDHC0_CLK:
case IMX8QM_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC1_IPG_CLK:
case IMX8QM_SDHC1_CLK:
case IMX8QM_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART0_IPG_CLK:
case IMX8QM_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET0_IPG_CLK:
case IMX8QM_ENET0_AHB_CLK:
case IMX8QM_ENET0_REF_DIV:
case IMX8QM_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET1_IPG_CLK:
case IMX8QM_ENET1_AHB_CLK:
case IMX8QM_ENET1_REF_DIV:
case IMX8QM_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QM_UART0_IPG_CLK ||
clk->id >= IMX8QM_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return rate;
}
ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
{
sc_pm_clk_t pm_clk;
u32 new_rate = rate;
u16 resource;
int ret;
debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
switch (clk->id) {
case IMX8QM_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC0_IPG_CLK:
case IMX8QM_SDHC0_CLK:
case IMX8QM_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC1_IPG_CLK:
case IMX8QM_SDHC1_CLK:
case IMX8QM_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET0_IPG_CLK:
case IMX8QM_ENET0_AHB_CLK:
case IMX8QM_ENET0_REF_DIV:
case IMX8QM_ENET0_PTP_CLK:
case IMX8QM_ENET0_ROOT_DIV:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET1_IPG_CLK:
case IMX8QM_ENET1_AHB_CLK:
case IMX8QM_ENET1_REF_DIV:
case IMX8QM_ENET1_PTP_CLK:
case IMX8QM_ENET1_ROOT_DIV:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QM_UART0_IPG_CLK ||
clk->id >= IMX8QM_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return new_rate;
}
int __imx8_clk_enable(struct clk *clk, bool enable)
{
sc_pm_clk_t pm_clk;
u16 resource;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QM_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC0_IPG_CLK:
case IMX8QM_SDHC0_CLK:
case IMX8QM_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_SDHC1_IPG_CLK:
case IMX8QM_SDHC1_CLK:
case IMX8QM_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET0_IPG_CLK:
case IMX8QM_ENET0_AHB_CLK:
case IMX8QM_ENET0_REF_DIV:
case IMX8QM_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QM_ENET1_IPG_CLK:
case IMX8QM_ENET1_AHB_CLK:
case IMX8QM_ENET1_REF_DIV:
case IMX8QM_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QM_UART0_IPG_CLK ||
clk->id >= IMX8QM_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return 0;
}

311
drivers/clk/imx/clk-imx8qxp.c Normal file
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@ -0,0 +1,311 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2018 NXP
* Peng Fan <peng.fan@nxp.com>
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/clock.h>
#include <dt-bindings/clock/imx8qxp-clock.h>
#include <dt-bindings/soc/imx_rsrc.h>
#include <misc.h>
#include "clk-imx8.h"
#if CONFIG_IS_ENABLED(CMD_CLK)
struct imx8_clks imx8_clk_names[] = {
{ IMX8QXP_A35_DIV, "A35_DIV" },
{ IMX8QXP_I2C0_CLK, "I2C0" },
{ IMX8QXP_I2C1_CLK, "I2C1" },
{ IMX8QXP_I2C2_CLK, "I2C2" },
{ IMX8QXP_I2C3_CLK, "I2C3" },
{ IMX8QXP_UART0_CLK, "UART0" },
{ IMX8QXP_UART1_CLK, "UART1" },
{ IMX8QXP_UART2_CLK, "UART2" },
{ IMX8QXP_UART3_CLK, "UART3" },
{ IMX8QXP_SDHC0_CLK, "SDHC0" },
{ IMX8QXP_SDHC1_CLK, "SDHC1" },
{ IMX8QXP_ENET0_AHB_CLK, "ENET0_AHB" },
{ IMX8QXP_ENET0_IPG_CLK, "ENET0_IPG" },
{ IMX8QXP_ENET0_REF_DIV, "ENET0_REF" },
{ IMX8QXP_ENET0_PTP_CLK, "ENET0_PTP" },
{ IMX8QXP_ENET1_AHB_CLK, "ENET1_AHB" },
{ IMX8QXP_ENET1_IPG_CLK, "ENET1_IPG" },
{ IMX8QXP_ENET1_REF_DIV, "ENET1_REF" },
{ IMX8QXP_ENET1_PTP_CLK, "ENET1_PTP" },
};
int num_clks = ARRAY_SIZE(imx8_clk_names);
#endif
ulong imx8_clk_get_rate(struct clk *clk)
{
sc_pm_clk_t pm_clk;
ulong rate;
u16 resource;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_A35_DIV:
resource = SC_R_A35;
pm_clk = SC_PM_CLK_CPU;
break;
case IMX8QXP_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC0_IPG_CLK:
case IMX8QXP_SDHC0_CLK:
case IMX8QXP_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC1_IPG_CLK:
case IMX8QXP_SDHC1_CLK:
case IMX8QXP_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_IPG_CLK:
case IMX8QXP_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET0_IPG_CLK:
case IMX8QXP_ENET0_AHB_CLK:
case IMX8QXP_ENET0_REF_DIV:
case IMX8QXP_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET1_IPG_CLK:
case IMX8QXP_ENET1_AHB_CLK:
case IMX8QXP_ENET1_REF_DIV:
case IMX8QXP_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QXP_UART0_IPG_CLK ||
clk->id >= IMX8QXP_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
};
ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return rate;
}
ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
{
sc_pm_clk_t pm_clk;
u32 new_rate = rate;
u16 resource;
int ret;
debug("%s(#%lu), rate: %lu\n", __func__, clk->id, rate);
switch (clk->id) {
case IMX8QXP_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC0_IPG_CLK:
case IMX8QXP_SDHC0_CLK:
case IMX8QXP_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC1_SEL:
case IMX8QXP_SDHC0_SEL:
return 0;
case IMX8QXP_SDHC1_IPG_CLK:
case IMX8QXP_SDHC1_CLK:
case IMX8QXP_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET0_IPG_CLK:
case IMX8QXP_ENET0_AHB_CLK:
case IMX8QXP_ENET0_REF_DIV:
case IMX8QXP_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET1_IPG_CLK:
case IMX8QXP_ENET1_AHB_CLK:
case IMX8QXP_ENET1_REF_DIV:
case IMX8QXP_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QXP_UART0_IPG_CLK ||
clk->id >= IMX8QXP_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
};
ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return new_rate;
}
int __imx8_clk_enable(struct clk *clk, bool enable)
{
sc_pm_clk_t pm_clk;
u16 resource;
int ret;
debug("%s(#%lu)\n", __func__, clk->id);
switch (clk->id) {
case IMX8QXP_I2C0_CLK:
resource = SC_R_I2C_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C1_CLK:
resource = SC_R_I2C_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C2_CLK:
resource = SC_R_I2C_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_I2C3_CLK:
resource = SC_R_I2C_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART0_CLK:
resource = SC_R_UART_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART1_CLK:
resource = SC_R_UART_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART2_CLK:
resource = SC_R_UART_2;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_UART3_CLK:
resource = SC_R_UART_3;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC0_IPG_CLK:
case IMX8QXP_SDHC0_CLK:
case IMX8QXP_SDHC0_DIV:
resource = SC_R_SDHC_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_SDHC1_IPG_CLK:
case IMX8QXP_SDHC1_CLK:
case IMX8QXP_SDHC1_DIV:
resource = SC_R_SDHC_1;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET0_IPG_CLK:
case IMX8QXP_ENET0_AHB_CLK:
case IMX8QXP_ENET0_REF_DIV:
case IMX8QXP_ENET0_PTP_CLK:
resource = SC_R_ENET_0;
pm_clk = SC_PM_CLK_PER;
break;
case IMX8QXP_ENET1_IPG_CLK:
case IMX8QXP_ENET1_AHB_CLK:
case IMX8QXP_ENET1_REF_DIV:
case IMX8QXP_ENET1_PTP_CLK:
resource = SC_R_ENET_1;
pm_clk = SC_PM_CLK_PER;
break;
default:
if (clk->id < IMX8QXP_UART0_IPG_CLK ||
clk->id >= IMX8QXP_CLK_END) {
printf("%s(Invalid clk ID #%lu)\n",
__func__, clk->id);
return -EINVAL;
}
return -ENOTSUPP;
}
ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
if (ret) {
printf("%s err %d\n", __func__, ret);
return ret;
}
return 0;
}

4
drivers/ddr/imx/imx8m/Kconfig
View File

@ -1,3 +1,6 @@
menu "i.MX8M DDR controllers"
depends on ARCH_IMX8M
config IMX8M_DRAM
bool "imx8m dram"
@ -20,3 +23,4 @@ config SAVED_DRAM_TIMING_BASE
info into memory for low power use. OCRAM_S is used for this
purpose on i.MX8MM.
default 0x180000
endmenu

1
drivers/misc/imx8/Makefile
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y += scu_api.o scu.o
obj-$(CONFIG_CMD_FUSE) += fuse.o

86
drivers/misc/imx8/fuse.c Normal file
View File

@ -0,0 +1,86 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <console.h>
#include <errno.h>
#include <fuse.h>
#include <asm/arch/sci/sci.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define FSL_ECC_WORD_START_1 0x10
#define FSL_ECC_WORD_END_1 0x10F
#ifdef CONFIG_IMX8QXP
#define FSL_ECC_WORD_START_2 0x220
#define FSL_ECC_WORD_END_2 0x31F
#define FSL_QXP_FUSE_GAP_START 0x110
#define FSL_QXP_FUSE_GAP_END 0x21F
#endif
#define FSL_SIP_OTP_READ 0xc200000A
#define FSL_SIP_OTP_WRITE 0xc200000B
int fuse_read(u32 bank, u32 word, u32 *val)
{
return fuse_sense(bank, word, val);
}
int fuse_sense(u32 bank, u32 word, u32 *val)
{
unsigned long ret = 0, value = 0;
if (bank != 0) {
printf("Invalid bank argument, ONLY bank 0 is supported\n");
return -EINVAL;
}
ret = call_imx_sip_ret2(FSL_SIP_OTP_READ, (unsigned long)word, &value,
0, 0);
*val = (u32)value;
return ret;
}
int fuse_prog(u32 bank, u32 word, u32 val)
{
if (bank != 0) {
printf("Invalid bank argument, ONLY bank 0 is supported\n");
return -EINVAL;
}
if (IS_ENABLED(CONFIG_IMX8QXP)) {
if (word >= FSL_QXP_FUSE_GAP_START &&
word <= FSL_QXP_FUSE_GAP_END) {
printf("Invalid word argument for this SoC\n");
return -EINVAL;
}
}
if ((word >= FSL_ECC_WORD_START_1 && word <= FSL_ECC_WORD_END_1) ||
(word >= FSL_ECC_WORD_START_2 && word <= FSL_ECC_WORD_END_2)) {
puts("Warning: Words in this index range have ECC protection\n"
"and can only be programmed once per word. Individual bit\n"
"operations will be rejected after the first one.\n"
"\n\n Really program this word? <y/N>\n");
if (!confirm_yesno()) {
puts("Word programming aborted\n");
return -EPERM;
}
}
return call_imx_sip(FSL_SIP_OTP_WRITE, (unsigned long)word,
(unsigned long)val, 0);
}
int fuse_override(u32 bank, u32 word, u32 val)
{
printf("Override fuse to i.MX8 in u-boot is forbidden\n");
return -EPERM;
}

16
drivers/misc/imx8/scu.c
View File

@ -219,11 +219,21 @@ static int imx8_scu_bind(struct udevice *dev)
int ret;
struct udevice *child;
int node;
char *clk_compatible, *iomuxc_compatible;
if (IS_ENABLED(CONFIG_IMX8QXP)) {
clk_compatible = "fsl,imx8qxp-clk";
iomuxc_compatible = "fsl,imx8qxp-iomuxc";
} else if (IS_ENABLED(CONFIG_IMX8QM)) {
clk_compatible = "fsl,imx8qm-clk";
iomuxc_compatible = "fsl,imx8qm-iomuxc";
} else {
return -EINVAL;
}
debug("%s(dev=%p)\n", __func__, dev);
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx8qxp-clk");
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, clk_compatible);
if (node < 0)
panic("No clk node found\n");
@ -234,7 +244,7 @@ static int imx8_scu_bind(struct udevice *dev)
plat->clk = child;
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"fsl,imx8qxp-iomuxc");
iomuxc_compatible);
if (node < 0)
panic("No iomuxc node found\n");

21
drivers/misc/mxc_ocotp.c
View File

@ -321,6 +321,11 @@ int fuse_sense(u32 bank, u32 word, u32 *val)
struct ocotp_regs *regs;
int ret;
if (is_imx8mq() && is_soc_rev(CHIP_REV_2_1)) {
printf("mxc_ocotp %s(): fuse sense is disabled\n", __func__);
return -EPERM;
}
ret = prepare_read(&regs, bank, word, val, __func__);
if (ret)
return ret;
@ -354,13 +359,17 @@ static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word,
/* Only bank 0 and 1 are redundancy mode, others are ECC mode */
if (bank != 0 && bank != 1) {
ret = fuse_sense(bank, word, &val);
if (ret)
return ret;
if ((soc_rev() < CHIP_REV_2_0) ||
((soc_rev() >= CHIP_REV_2_0) &&
bank != 9 && bank != 10 && bank != 28)) {
ret = fuse_sense(bank, word, &val);
if (ret)
return ret;
if (val != 0) {
printf("mxc_ocotp: The word has been programmed, no more write\n");
return -EPERM;
if (val != 0) {
printf("mxc_ocotp: The word has been programmed, no more write\n");
return -EPERM;
}
}
}
#endif

1
drivers/pinctrl/nxp/pinctrl-imx8.c
View File

@ -25,6 +25,7 @@ static int imx8_pinctrl_probe(struct udevice *dev)
static const struct udevice_id imx8_pinctrl_match[] = {
{ .compatible = "fsl,imx8qxp-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
{ .compatible = "fsl,imx8qm-iomuxc", .data = (ulong)&imx8_pinctrl_soc_info },
{ /* sentinel */ }
};

7
drivers/usb/host/Kconfig
View File

@ -132,6 +132,13 @@ config USB_EHCI_MARVELL
---help---
Enables support for the on-chip EHCI controller on MVEBU SoCs.
config USB_EHCI_MX5
bool "Support for i.MX5 on-chip EHCI USB controller"
depends on ARCH_MX5
default n
help
Enables support for the on-chip EHCI controller on i.MX5 SoCs.
config USB_EHCI_MX6
bool "Support for i.MX6 on-chip EHCI USB controller"
depends on ARCH_MX6

103
drivers/usb/host/ehci-mx5.c
View File

@ -12,6 +12,8 @@
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <dm.h>
#include <power/regulator.h>
#include "ehci.h"
@ -223,6 +225,7 @@ __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
mdelay(50);
}
#if !CONFIG_IS_ENABLED(DM_USB)
static const struct ehci_ops mx5_ehci_ops = {
.powerup_fixup = mx5_ehci_powerup_fixup,
};
@ -267,3 +270,103 @@ int ehci_hcd_stop(int index)
{
return 0;
}
#else /* CONFIG_IS_ENABLED(DM_USB) */
struct ehci_mx5_priv_data {
struct ehci_ctrl ctrl;
struct usb_ehci *ehci;
struct udevice *vbus_supply;
enum usb_init_type init_type;
int portnr;
};
static const struct ehci_ops mx5_ehci_ops = {
.powerup_fixup = mx5_ehci_powerup_fixup,
};
static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
{
struct usb_platdata *plat = dev_get_platdata(dev);
const char *mode;
mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
if (mode) {
if (strcmp(mode, "peripheral") == 0)
plat->init_type = USB_INIT_DEVICE;
else if (strcmp(mode, "host") == 0)
plat->init_type = USB_INIT_HOST;
else
return -EINVAL;
}
return 0;
}
static int ehci_usb_probe(struct udevice *dev)
{
struct usb_platdata *plat = dev_get_platdata(dev);
struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
struct ehci_mx5_priv_data *priv = dev_get_priv(dev);
enum usb_init_type type = plat->init_type;
struct ehci_hccr *hccr;
struct ehci_hcor *hcor;
int ret;
set_usboh3_clk();
enable_usboh3_clk(true);
set_usb_phy_clk();
enable_usb_phy1_clk(true);
enable_usb_phy2_clk(true);
mdelay(1);
priv->ehci = ehci;
priv->portnr = dev->seq;
priv->init_type = type;
ret = device_get_supply_regulator(dev, "vbus-supply",
&priv->vbus_supply);
if (ret)
debug("%s: No vbus supply\n", dev->name);
if (!ret && priv->vbus_supply) {
ret = regulator_set_enable(priv->vbus_supply,
(type == USB_INIT_DEVICE) ?
false : true);
if (ret) {
puts("Error enabling VBUS supply\n");
return ret;
}
}
hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
hcor = (struct ehci_hcor *)((uint32_t)hccr +
HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
setbits_le32(&ehci->portsc, USB_EN);
mxc_set_usbcontrol(priv->portnr, CONFIG_MXC_USB_FLAGS);
mdelay(10);
return ehci_register(dev, hccr, hcor, &mx5_ehci_ops, 0,
priv->init_type);
}
static const struct udevice_id mx5_usb_ids[] = {
{ .compatible = "fsl,imx53-usb" },
{ }
};
U_BOOT_DRIVER(usb_mx5) = {
.name = "ehci_mx5",
.id = UCLASS_USB,
.of_match = mx5_usb_ids,
.ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
.probe = ehci_usb_probe,
.remove = ehci_deregister,
.ops = &ehci_usb_ops,
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
.priv_auto_alloc_size = sizeof(struct ehci_mx5_priv_data),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* !CONFIG_IS_ENABLED(DM_USB) */

4
include/configs/apalis_imx6.h
View File

@ -138,12 +138,12 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x20000000\0" \
"fdt_addr_r=0x12000000\0" \
"fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
"ramdisk_addr_r=0x12100000\0" \
"ramdisk_addr_r=0x12200000\0" \
"scriptaddr=0x17000000\0"
#define NFS_BOOTCMD \

14
include/configs/colibri-imx6ull.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 Toradex AG
* Copyright 2018-2019 Toradex AG
*
* Configuration settings for the Colibri iMX6ULL module.
*
@ -19,10 +19,6 @@
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* Network */
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
#define CONFIG_IP_DEFRAG
#define CONFIG_TFTP_BLOCKSIZE 16352
#define CONFIG_TFTP_TSIZE
@ -30,7 +26,7 @@
/* ENET1 */
#define IMX_FEC_BASE ENET2_BASE_ADDR
/* MMC Config*/
/* MMC Config */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_USDHC_NUM 1
@ -48,12 +44,12 @@
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x82000000\0" \
"fdt_addr_r=0x82100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
"ramdisk_addr_r=0x82100000\0" \
"ramdisk_addr_r=0x82200000\0" \
"scriptaddr=0x87000000\0"
#define NFS_BOOTCMD \
@ -182,4 +178,4 @@
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif
#endif /* __COLIBRI_IMX6ULL_CONFIG_H */

62
include/configs/colibri_imx6.h
View File

@ -115,25 +115,31 @@
"imx6dl-colibri-cam-eval-v3.dtb fat 0 1"
#define EMMC_BOOTCMD \
"emmcargs=ip=off root=/dev/mmcblk0p2 rw,noatime rootfstype=ext4 " \
"set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\
"rw,noatime rootfstype=ext4 " \
"rootwait\0" \
"emmcboot=run setup; " \
"emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \
"setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \
"${vidargs}; echo Booting from internal eMMC chip...; " \
"run emmcdtbload; load mmc 0:1 ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
"emmcdtbload=setenv dtbparam; load mmc 0:1 ${fdt_addr_r} " \
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
"emmcbootpart=1\0" \
"emmcdev=0\0" \
"emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \
"${fdt_addr_r} ${fdt_file} && " \
"setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \
"emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \
"emmcrootpart=2\0"
#define MEM_LAYOUT_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
"fdt_addr_r=0x12000000\0" \
"fdt_addr_r=0x12100000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x11000000\0" \
"pxefile_addr_r=0x17100000\0" \
"ramdisk_addr_r=0x12100000\0" \
"ramdisk_addr_r=0x12200000\0" \
"scriptaddr=0x17000000\0"
#define NFS_BOOTCMD \
@ -147,27 +153,40 @@
"&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
#define SD_BOOTCMD \
"sdargs=ip=off root=/dev/mmcblk1p2 rw,noatime rootfstype=ext4 " \
"rootwait\0" \
"sdboot=run setup; " \
"set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} rw,noatime " \
"rootfstype=ext4 rootwait\0" \
"sdboot=run setup; run sdfinduuid; run set_sdargs; " \
"setenv bootargs ${defargs} ${sdargs} ${setupargs} " \
"${vidargs}; echo Booting from SD card; " \
"run sddtbload; load mmc 1:1 ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"run sddtbload; load mmc ${sddev}:${sdbootpart} "\
"${kernel_addr_r} ${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
"sddtbload=setenv dtbparam; load mmc 1:1 ${fdt_addr_r} " \
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
"sdbootpart=1\0" \
"sddev=1\0" \
"sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \
"${fdt_addr_r} ${fdt_file} && setenv dtbparam \" - " \
"${fdt_addr_r}\" && true\0" \
"sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \
"sdrootpart=2\0"
#define USB_BOOTCMD \
"usbargs=ip=off root=/dev/sda2 rw,noatime rootfstype=ext4 " \
"rootwait\0" \
"usbboot=run setup; setenv bootargs ${defargs} ${setupargs} " \
"set_usbargs=setenv usbargs ip=off root=PARTUUID=${uuid} rw,noatime " \
"rootfstype=ext4 rootwait\0" \
"usbboot=run setup; usb start; run usbfinduuid; run set_usbargs; " \
"setenv bootargs ${defargs} ${setupargs} " \
"${usbargs} ${vidargs}; echo Booting from USB stick...; " \
"usb start && run usbdtbload; load usb 0:1 ${kernel_addr_r} " \
"run usbdtbload; " \
"load usb ${usbdev}:${usbbootpart} ${kernel_addr_r} " \
"${boot_file} && run fdt_fixup && " \
"bootz ${kernel_addr_r} ${dtbparam}\0" \
"usbdtbload=setenv dtbparam; load usb 0:1 ${fdt_addr_r} " \
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && true\0"
"usbbootpart=1\0" \
"usbdev=0\0" \
"usbdtbload=setenv dtbparam; load usb ${usbdev}:${usbbootpart} " \
"${fdt_addr_r} " \
"${fdt_file} && setenv dtbparam \" - ${fdt_addr_r}\" && " \
"true\0" \
"usbfinduuid=part uuid usb ${usbdev}:${usbrootpart} uuid\0" \
"usbrootpart=2\0"
#define FDT_FILE "imx6dl-colibri-eval-v3.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
@ -186,6 +205,7 @@
MEM_LAYOUT_ENV_SETTINGS \
NFS_BOOTCMD \
SD_BOOTCMD \
USB_BOOTCMD \
"setethupdate=if env exists ethaddr; then; else setenv ethaddr " \
"00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \
"flash_eth.img && source ${loadaddr}\0" \

131
include/configs/dart_6ul.h Normal file
View File

@ -0,0 +1,131 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Board configuration file for Variscite DART-6UL Evaluation Kit
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
*/
#ifndef __DART_6UL_H
#define __DART_6UL_H
#include <linux/sizes.h>
#include "mx6_common.h"
/* SPL options */
#include "imx6_spl.h"
/* NAND pin conflicts with usdhc2 */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_FSL_USDHC_NUM 1
#else
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
#ifdef CONFIG_CMD_NET
#define CONFIG_FEC_ENET_DEV 0
#if (CONFIG_FEC_ENET_DEV == 0)
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x1
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "eth0"
#elif (CONFIG_FEC_ENET_DEV == 1)
#define IMX_FEC_BASE ENET2_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x3
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "eth1"
#endif
#endif
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
/* Environment settings */
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_OFFSET (14 * SZ_64K)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_OFFSET_REDUND \
(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
/* Environment in SD */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 0
#define MMC_ROOTFS_DEV 0
#define MMC_ROOTFS_PART 2
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SUPPORT_EMMC_BOOT
/* I2C configs */
#ifdef CONFIG_CMD_I2C
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
#define CONFIG_SYS_I2C_SPEED 100000
#endif
/* Miscellaneous configurable options */
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_512M
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_IMX_THERMAL
#define ENV_MMC \
"mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \
"mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \
"fitpart=1\0" \
"bootdelay=3\0" \
"silent=1\0" \
"optargs=rw rootwait\0" \
"mmcautodetect=yes\0" \
"mmcrootfstype=ext4\0" \
"mmcfit_name=fitImage\0" \
"mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \
"${mmcfit_name}\0" \
"mmcargs=setenv bootargs " \
"root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \
"console=${console} rootfstype=${mmcrootfstype}\0" \
"mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \
/* Default environment */
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0xffffffff\0" \
"console=ttymxc0,115200n8\0" \
"addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \
"fit_addr=0x82000000\0" \
ENV_MMC
#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit"
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#endif /* __DART_6UL_H */

6
include/configs/imx6_logic.h
View File

@ -46,11 +46,11 @@
"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
"nandroot=ubi0:rootfs rootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console},${baudrate}" \
" root=PARTUUID=${uuid} rootwait rw\0 ${mtdparts}\0" \
" root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \
"nandargs=setenv bootargs console=${console},${baudrate}" \
" ubi.mtd=fs root=${nandroot} ${mtdparts}\0" \
" ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \
"ramargs=setenv bootargs console=${console},${baudrate}" \
" root=/dev/ram rw ${mtdparts}\0" \
" root=/dev/ram rw ${mtdparts} ${optargs}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...;" \

176
include/configs/imx8qm_mek.h Normal file
View File

@ -0,0 +1,176 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
*/
#ifndef __IMX8QM_MEK_H
#define __IMX8QM_MEK_H
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_TEXT_BASE 0x0
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK 0x013E000
#define CONFIG_SPL_BSS_START_ADDR 0x00128000
#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
#define CONFIG_SERIAL_LPUART_BASE 0x5a060000
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_MALLOC_F_ADDR 0x00120000
#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
#define CONFIG_OF_EMBED
#endif
#define CONFIG_REMAKE_ELF
#define CONFIG_BOARD_EARLY_INIT_F
/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP
#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define USDHC1_BASE_ADDR 0x5B010000
#define USDHC2_BASE_ADDR 0x5B020000
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8qxp-mek.dtb\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcautodetect=yes\0" \
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"echo wait for boot; " \
"fi;\0" \
"netargs=setenv bootargs console=${console} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${loadaddr} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
"booti ${loadaddr} - ${fdt_addr}; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"else " \
"booti; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else booti ${loadaddr} - ${fdt_addr}; fi"
/* Link Definitions */
#define CONFIG_LOADADDR 0x80280000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
/* Default environment is in SD */
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
#define CONFIG_SYS_FSL_USDHC_NUM 2
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
/* Serial */
#define CONFIG_BAUDRATE 115200
/* Monitor Command Prompt */
#define CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* Generic Timer Definitions */
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
/* Networking */
#define CONFIG_FEC_XCV_TYPE RGMII
#define FEC_QUIRK_ENET_MAC
#endif /* __IMX8QM_MEK_H */

5
include/configs/imx8qxp_mek.h
View File

@ -64,11 +64,11 @@
"script=boot.scr\0" \
"image=Image\0" \
"panel=NULL\0" \
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
"console=ttyLP0,${baudrate} earlycon\0" \
"fdt_addr=0x83000000\0" \
"fdt_high=0xffffffffffffffff\0" \
"boot_fdt=try\0" \
"fdt_file=fsl-imx8qxp-mek.dtb\0" \
"fdt_file=imx8qxp-mek.dtb\0" \
"initrd_addr=0x83800000\0" \
"initrd_high=0xffffffffffffffff\0" \
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
@ -158,7 +158,6 @@
#define CONFIG_BAUDRATE 115200
/* Monitor Command Prompt */
#define CONFIG_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_SYS_CBSIZE 2048
#define CONFIG_SYS_MAXARGS 64

9
include/configs/kp_imx53.h
View File

@ -15,14 +15,7 @@
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
/* MMC Configs */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_FSL_ESDHC_NUM 1
/* USB Configs */
#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
@ -57,7 +50,7 @@
"setexpr blkc ${blkc} + 1; " \
"mmc write ${loadaddr} 0x2 ${blkc}" \
"; fi\0" \
"upwic=setenv wic_file kp-image-kp${boardsoc}${boardtype}.wic; "\
"upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\
"if tftp ${loadaddr} ${wic_file}; then " \
"setexpr blkc ${filesize} / 0x200; " \
"setexpr blkc ${blkc} + 1; " \

1
include/configs/m53menlo.h
View File

@ -118,7 +118,6 @@
* USB
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI_MX5
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0

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