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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 19:09:43 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
commit
6b67962fd6
4
README
4
README
@ -2603,6 +2603,10 @@ Low Level (hardware related) configuration options:
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CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
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CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
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Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
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Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
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- CONFIG_PCI_DISABLE_PCIE:
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Disable PCI-Express on systems where it is supported but not
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required.
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- CONFIG_SPD_EEPROM
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- CONFIG_SPD_EEPROM
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Get DDR timing information from an I2C EEPROM. Common
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Get DDR timing information from an I2C EEPROM. Common
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with pluggable memory modules such as SODIMMs
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with pluggable memory modules such as SODIMMs
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@ -451,5 +451,6 @@ int post_hotkeys_pressed(void)
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int board_eth_init(bd_t *bis)
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int board_eth_init(bd_t *bis)
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{
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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return pci_eth_init(bis);
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}
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}
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@ -195,5 +195,6 @@ int pci_pre_init(struct pci_controller *hose)
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int board_eth_init(bd_t *bis)
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int board_eth_init(bd_t *bis)
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{
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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return pci_eth_init(bis);
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}
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}
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@ -315,5 +315,6 @@ int post_hotkeys_pressed(void)
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int board_eth_init(bd_t *bis)
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int board_eth_init(bd_t *bis)
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{
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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return pci_eth_init(bis);
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}
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}
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@ -956,5 +956,6 @@ int onboard_pci_arbiter_selected(int core_pci)
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int board_eth_init(bd_t *bis)
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int board_eth_init(bd_t *bis)
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{
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{
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cpu_eth_init(bis);
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return pci_eth_init(bis);
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return pci_eth_init(bis);
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}
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}
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@ -1101,11 +1101,8 @@ static void program_codt(unsigned long *dimm_populated,
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* Set the SDRAM Controller On Die Termination Register
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* Set the SDRAM Controller On Die Termination Register
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*-----------------------------------------------------------------*/
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*-----------------------------------------------------------------*/
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mfsdram(SDRAM_CODT, codt);
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mfsdram(SDRAM_CODT, codt);
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codt |= (SDRAM_CODT_IO_NMODE
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codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
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& (~SDRAM_CODT_DQS_SINGLE_END
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codt |= SDRAM_CODT_IO_NMODE;
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& ~SDRAM_CODT_CKSE_SINGLE_END
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& ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
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& ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
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for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
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for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
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if (dimm_populated[dimm_num] != SDRAM_NONE) {
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if (dimm_populated[dimm_num] != SDRAM_NONE) {
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@ -61,6 +61,8 @@
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#define NUMLOOPS 1 /* configure as you deem approporiate */
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#define NUMLOOPS 1 /* configure as you deem approporiate */
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#define NUMMEMWORDS 16
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#define NUMMEMWORDS 16
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#define SDRAM_RDCC_RDSS_VAL(n) SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
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/* Private Structure Definitions */
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/* Private Structure Definitions */
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struct autocal_regs {
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struct autocal_regs {
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@ -147,6 +149,13 @@ ulong __ddr_scan_option(ulong default_val)
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}
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}
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ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
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ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
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u32 __ddr_rdss_opt(u32 default_val)
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{
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return default_val;
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}
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u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
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static u32 *get_membase(int bxcr_num)
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static u32 *get_membase(int bxcr_num)
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{
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{
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ulong bxcf;
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ulong bxcf;
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@ -341,6 +350,7 @@ static int short_mem_test(u32 *base_address)
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ppcDcbf((ulong)&(base_address[j]));
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ppcDcbf((ulong)&(base_address[j]));
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}
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}
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sync();
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sync();
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iobarrier_rw();
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for (l = 0; l < NUMLOOPS; l++) {
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for (l = 0; l < NUMLOOPS; l++) {
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for (j = 0; j < NUMMEMWORDS; j++) {
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for (j = 0; j < NUMMEMWORDS; j++) {
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if (base_address[j] != test[i][j]) {
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if (base_address[j] != test[i][j]) {
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@ -355,6 +365,7 @@ static int short_mem_test(u32 *base_address)
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ppcDcbf((u32)&(base_address[j]));
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ppcDcbf((u32)&(base_address[j]));
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} /* for (j = 0; j < NUMMEMWORDS; j++) */
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} /* for (j = 0; j < NUMMEMWORDS; j++) */
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sync();
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sync();
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iobarrier_rw();
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} /* for (l=0; l<NUMLOOPS; l++) */
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} /* for (l=0; l<NUMLOOPS; l++) */
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}
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}
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@ -447,7 +458,8 @@ static u32 DQS_calibration_methodA(struct ddrautocal *cal)
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* Program RDCC register
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* Program RDCC register
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* Read sample cycle auto-update enable
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* Read sample cycle auto-update enable
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*/
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*/
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mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE);
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mtsdram(SDRAM_RDCC,
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ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
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#ifdef DEBUG
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#ifdef DEBUG
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mfsdram(SDRAM_RDCC, temp);
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mfsdram(SDRAM_RDCC, temp);
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@ -633,7 +645,8 @@ static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
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* Program RDCC register
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* Program RDCC register
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* Read sample cycle auto-update enable
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* Read sample cycle auto-update enable
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*/
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*/
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mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE);
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mtsdram(SDRAM_RDCC,
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ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
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#ifdef DEBUG
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#ifdef DEBUG
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mfsdram(SDRAM_RDCC, temp);
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mfsdram(SDRAM_RDCC, temp);
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@ -1091,32 +1104,36 @@ u32 DQS_autocalibration(void)
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* if no passing window was found, or is the
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* if no passing window was found, or is the
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* size of the RFFD passing window.
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* size of the RFFD passing window.
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*/
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*/
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if (result != 0) {
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/*
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tcal.autocal.flags = 1;
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* want the lowest Read Sample Cycle Select
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debug("*** (%d)(%d) result passed window size: 0x%08x, "
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*/
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"rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n",
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val = SDRAM_RDCC_RDSS_DECODE(val);
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wdtr, clkp, result, ddrcal.rqfd,
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debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
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ddrcal.rffd, ddrcal.rdcc);
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val, best_rdcc);
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/*
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* Save the SDRAM_WRDTR and SDRAM_CLKTR
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if ((result != 0) &&
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* settings for the largest returned
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(val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) {
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* RFFD passing window size.
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if (((result == best_result) && (val < best_rdcc)) ||
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*/
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((result > best_result) && (val <= best_rdcc))) {
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if (result > best_result) {
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tcal.autocal.flags = 1;
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debug("*** (%d)(%d) result passed window "
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"size: 0x%08x, rqfd = 0x%08x, "
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"rffd = 0x%08x, rdcc = 0x%08x\n",
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wdtr, clkp, result, ddrcal.rqfd,
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ddrcal.rffd, ddrcal.rdcc);
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/*
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/*
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* want the lowest Read Sample Cycle Select
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* Save the SDRAM_WRDTR and SDRAM_CLKTR
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* settings for the largest returned
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* RFFD passing window size.
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*/
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*/
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val = (val & SDRAM_RDCC_RDSS_MASK) >> 30;
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best_rdcc = val;
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debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
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tcal.clocks.wrdtr = wdtr;
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val, best_rdcc);
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tcal.clocks.clktr = clkp;
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if (val <= best_rdcc) {
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tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val);
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best_rdcc = val;
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tcal.autocal.rqfd = ddrcal.rqfd;
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tcal.clocks.wrdtr = wdtr;
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tcal.autocal.rffd = ddrcal.rffd;
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tcal.clocks.clktr = clkp;
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best_result = result;
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tcal.clocks.rdcc = (val << 30);
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tcal.autocal.rqfd = ddrcal.rqfd;
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tcal.autocal.rffd = ddrcal.rffd;
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best_result = result;
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if (verbose_lvl > 2) {
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if (verbose_lvl > 2) {
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printf("** (%d)(%d) "
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printf("** (%d)(%d) "
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@ -1152,9 +1169,8 @@ u32 DQS_autocalibration(void)
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"loop FCSR: 0x%08x\n",
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"loop FCSR: 0x%08x\n",
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wdtr, clkp, val);
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wdtr, clkp, val);
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}
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}
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} /* if (val <= best_rdcc) */
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}
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} /* if (result >= best_result) */
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} /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
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} /* if (result != 0) */
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scan_list++;
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scan_list++;
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} /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
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} /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
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@ -22,10 +22,10 @@
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#define _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#ifndef CONFIG_MAX_MEM_MAPPED
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#ifndef CONFIG_MAX_MEM_MAPPED
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) && defined(CONFIG_SPD_EEPROM)
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#if defined(CONFIG_4xx)
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#else
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#else
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#define CONFIG_MAX_MEM_MAPPED (256 << 20)
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#define CONFIG_MAX_MEM_MAPPED (256 << 20)
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#endif
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#endif
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#endif
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#endif
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@ -566,6 +566,8 @@
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#define SDRAM_RDCC_RSAE_MASK 0x00000001
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#define SDRAM_RDCC_RSAE_MASK 0x00000001
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#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
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#define SDRAM_RDCC_RSAE_DISABLE 0x00000001
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#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
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#define SDRAM_RDCC_RSAE_ENABLE 0x00000000
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#define SDRAM_RDCC_RDSS_ENCODE(n) ((((u32)(n))&0x03)<<30)
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#define SDRAM_RDCC_RDSS_DECODE(n) ((((u32)(n))>>30)&0x03)
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/*
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/*
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* SDRAM Read Feedback Delay Control Register
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* SDRAM Read Feedback Delay Control Register
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@ -45,7 +45,6 @@
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*/
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*/
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#define CONFIG_PHYS_64BIT
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#define CONFIG_PHYS_64BIT
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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/*
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/*
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* Include common defines/options for all AMCC eval boards
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* Include common defines/options for all AMCC eval boards
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@ -234,16 +234,9 @@
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*
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*
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* DDR Autocalibration Method_B is the default.
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* DDR Autocalibration Method_B is the default.
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*/
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*/
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#if 0
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/*
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* Needs FIX!!!
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* Disable autocalibration for now, because of the unresolved problem
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* with kilauea board using 200MHz PLB/DDR2 frequency
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*/
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
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#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
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#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
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#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
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#undef CONFIG_PPC4xx_DDR_METHOD_A
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#undef CONFIG_PPC4xx_DDR_METHOD_A
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#endif
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#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM0_MB0CF_BASE (( 0 << 20) + CONFIG_SYS_SDRAM_BASE)
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