diff --git a/README b/README
index 56e981d625..b23a51258e 100644
--- a/README
+++ b/README
@@ -2603,6 +2603,10 @@ Low Level (hardware related) configuration options:
   CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only)
 		Overrides the default PCI memory map in cpu/mpc8260/pci.c if set.
 
+- CONFIG_PCI_DISABLE_PCIE:
+		Disable PCI-Express on systems where it is supported but not
+		required.
+
 - CONFIG_SPD_EEPROM
 		Get DDR timing information from an I2C EEPROM. Common
 		with pluggable memory modules such as SODIMMs
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index b6c0c11ef2..e078ba4f9c 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -451,5 +451,6 @@ int post_hotkeys_pressed(void)
 
 int board_eth_init(bd_t *bis)
 {
+	cpu_eth_init(bis);
 	return pci_eth_init(bis);
 }
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index 522437805b..669429b67f 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -195,5 +195,6 @@ int pci_pre_init(struct pci_controller *hose)
 
 int board_eth_init(bd_t *bis)
 {
+	cpu_eth_init(bis);
 	return pci_eth_init(bis);
 }
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index 28bdab5dbb..53ce88c6cd 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -315,5 +315,6 @@ int post_hotkeys_pressed(void)
 
 int board_eth_init(bd_t *bis)
 {
+	cpu_eth_init(bis);
 	return pci_eth_init(bis);
 }
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index c8055689f7..06c7d625a4 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -956,5 +956,6 @@ int onboard_pci_arbiter_selected(int core_pci)
 
 int board_eth_init(bd_t *bis)
 {
+	cpu_eth_init(bis);
 	return pci_eth_init(bis);
 }
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 1e495716b5..33788cc900 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -1101,11 +1101,8 @@ static void program_codt(unsigned long *dimm_populated,
 	 * Set the SDRAM Controller On Die Termination Register
 	 *-----------------------------------------------------------------*/
 	mfsdram(SDRAM_CODT, codt);
-	codt |= (SDRAM_CODT_IO_NMODE
-		 & (~SDRAM_CODT_DQS_SINGLE_END
-		    & ~SDRAM_CODT_CKSE_SINGLE_END
-		    & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
-		    & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
+	codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
+	codt |= SDRAM_CODT_IO_NMODE;
 
 	for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 		if (dimm_populated[dimm_num] != SDRAM_NONE) {
diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
index 1e3e20df2e..91bf582d6e 100644
--- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
+++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c
@@ -61,6 +61,8 @@
 #define NUMLOOPS		1	/* configure as you deem approporiate */
 #define NUMMEMWORDS		16
 
+#define SDRAM_RDCC_RDSS_VAL(n)	SDRAM_RDCC_RDSS_DECODE(ddr_rdss_opt(n))
+
 /* Private Structure Definitions */
 
 struct autocal_regs {
@@ -147,6 +149,13 @@ ulong __ddr_scan_option(ulong default_val)
 }
 ulong ddr_scan_option(ulong) __attribute__((weak, alias("__ddr_scan_option")));
 
+u32 __ddr_rdss_opt(u32 default_val)
+{
+	return default_val;
+}
+u32 ddr_rdss_opt(ulong) __attribute__((weak, alias("__ddr_rdss_opt")));
+
+
 static u32 *get_membase(int bxcr_num)
 {
 	ulong bxcf;
@@ -341,6 +350,7 @@ static int short_mem_test(u32 *base_address)
 			ppcDcbf((ulong)&(base_address[j]));
 		}
 		sync();
+		iobarrier_rw();
 		for (l = 0; l < NUMLOOPS; l++) {
 			for (j = 0; j < NUMMEMWORDS; j++) {
 				if (base_address[j] != test[i][j]) {
@@ -355,6 +365,7 @@ static int short_mem_test(u32 *base_address)
 				ppcDcbf((u32)&(base_address[j]));
 			} /* for (j = 0; j < NUMMEMWORDS; j++) */
 			sync();
+			iobarrier_rw();
 		} /* for (l=0; l<NUMLOOPS; l++) */
 	}
 
@@ -447,7 +458,8 @@ static u32 DQS_calibration_methodA(struct ddrautocal *cal)
 	 * Program RDCC register
 	 * Read sample cycle auto-update enable
 	 */
-	mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T1 | SDRAM_RDCC_RSAE_ENABLE);
+	mtsdram(SDRAM_RDCC,
+		ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
 
 #ifdef DEBUG
 	mfsdram(SDRAM_RDCC, temp);
@@ -633,7 +645,8 @@ static u32 program_DQS_calibration_methodB(struct ddrautocal *ddrcal)
 	 * Program RDCC register
 	 * Read sample cycle auto-update enable
 	 */
-	mtsdram(SDRAM_RDCC, SDRAM_RDCC_RDSS_T2 | SDRAM_RDCC_RSAE_ENABLE);
+	mtsdram(SDRAM_RDCC,
+		ddr_rdss_opt(SDRAM_RDCC_RDSS_T2) | SDRAM_RDCC_RSAE_ENABLE);
 
 #ifdef DEBUG
 	mfsdram(SDRAM_RDCC, temp);
@@ -1091,32 +1104,36 @@ u32 DQS_autocalibration(void)
 		 * if no passing window was found, or is the
 		 * size of the RFFD passing window.
 		 */
-		if (result != 0) {
-			tcal.autocal.flags = 1;
-			debug("*** (%d)(%d) result passed window size: 0x%08x, "
-			      "rqfd = 0x%08x, rffd = 0x%08x, rdcc = 0x%08x\n",
-				wdtr, clkp, result, ddrcal.rqfd,
-				ddrcal.rffd, ddrcal.rdcc);
-			/*
-			 * Save the SDRAM_WRDTR and SDRAM_CLKTR
-			 * settings for the largest returned
-			 * RFFD passing window size.
-			 */
-			if (result > best_result) {
+		/*
+		 * want the lowest Read Sample Cycle Select
+		 */
+		val = SDRAM_RDCC_RDSS_DECODE(val);
+		debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
+			val, best_rdcc);
+
+		if ((result != 0) &&
+		    (val >= SDRAM_RDCC_RDSS_VAL(SDRAM_RDCC_RDSS_T2))) {
+			if (((result == best_result) && (val < best_rdcc)) ||
+			    ((result > best_result) && (val <= best_rdcc))) {
+				tcal.autocal.flags = 1;
+				debug("*** (%d)(%d) result passed window "
+					"size: 0x%08x, rqfd = 0x%08x, "
+					"rffd = 0x%08x, rdcc = 0x%08x\n",
+					wdtr, clkp, result, ddrcal.rqfd,
+					ddrcal.rffd, ddrcal.rdcc);
+
 				/*
-				 * want the lowest Read Sample Cycle Select
+				 * Save the SDRAM_WRDTR and SDRAM_CLKTR
+				 * settings for the largest returned
+				 * RFFD passing window size.
 				 */
-				val = (val & SDRAM_RDCC_RDSS_MASK) >> 30;
-				debug("*** (%d) (%d) current_rdcc, best_rdcc\n",
-							val, best_rdcc);
-				if (val <= best_rdcc) {
-					best_rdcc = val;
-					tcal.clocks.wrdtr = wdtr;
-					tcal.clocks.clktr = clkp;
-					tcal.clocks.rdcc = (val << 30);
-					tcal.autocal.rqfd = ddrcal.rqfd;
-					tcal.autocal.rffd = ddrcal.rffd;
-					best_result = result;
+				best_rdcc = val;
+				tcal.clocks.wrdtr = wdtr;
+				tcal.clocks.clktr = clkp;
+				tcal.clocks.rdcc = SDRAM_RDCC_RDSS_ENCODE(val);
+				tcal.autocal.rqfd = ddrcal.rqfd;
+				tcal.autocal.rffd = ddrcal.rffd;
+				best_result = result;
 
 					if (verbose_lvl > 2) {
 						printf("** (%d)(%d)  "
@@ -1152,9 +1169,8 @@ u32 DQS_autocalibration(void)
 						       "loop FCSR: 0x%08x\n",
 							wdtr, clkp, val);
 					}
-				} /* if (val <= best_rdcc) */
-			} /* if (result >= best_result) */
-		} /* if (result != 0) */
+			}
+		} /* if ((result != 0) && (val >= (ddr_rdss_opt()))) */
 		scan_list++;
 	} /* while ((scan_list->wrdtr != -1) && (scan_list->clktr != -1)) */
 
diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h
index 6d27cb1db3..2a4ee15b7d 100644
--- a/include/asm-ppc/config.h
+++ b/include/asm-ppc/config.h
@@ -22,10 +22,10 @@
 #define _ASM_CONFIG_H_
 
 #ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) && defined(CONFIG_SPD_EEPROM)
+#if defined(CONFIG_4xx)
 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
-#define CONFIG_MAX_MEM_MAPPED (256 << 20)
+#define CONFIG_MAX_MEM_MAPPED	(256 << 20)
 #endif
 #endif
 
diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h
index 98faced366..992a3d2210 100644
--- a/include/asm-ppc/ppc4xx-sdram.h
+++ b/include/asm-ppc/ppc4xx-sdram.h
@@ -566,6 +566,8 @@
 #define SDRAM_RDCC_RSAE_MASK		0x00000001
 #define SDRAM_RDCC_RSAE_DISABLE		0x00000001
 #define SDRAM_RDCC_RSAE_ENABLE		0x00000000
+#define SDRAM_RDCC_RDSS_ENCODE(n)	((((u32)(n))&0x03)<<30)
+#define SDRAM_RDCC_RDSS_DECODE(n)	((((u32)(n))>>30)&0x03)
 
 /*
  * SDRAM Read Feedback Delay Control Register
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index ea6cf0d23f..0d89594f20 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -45,7 +45,6 @@
  */
 #define CONFIG_PHYS_64BIT
 #define	CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 
 /*
  * Include common defines/options for all AMCC eval boards
diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h
index 4d3ccf568b..26cb854394 100644
--- a/include/configs/kilauea.h
+++ b/include/configs/kilauea.h
@@ -234,16 +234,9 @@
  *
  * DDR Autocalibration Method_B is the default.
  */
-#if 0
-/*
- * Needs FIX!!!
- * Disable autocalibration for now, because of the unresolved problem
- * with kilauea board using 200MHz PLB/DDR2 frequency
- */
 #define	CONFIG_PPC4xx_DDR_AUTOCALIBRATION	/* IBM DDR autocalibration */
 #define	DEBUG_PPC4xx_DDR_AUTOCALIBRATION	/* dynamic DDR autocal debug */
 #undef	CONFIG_PPC4xx_DDR_METHOD_A
-#endif
 
 #define	CONFIG_SYS_SDRAM0_MB0CF_BASE	((  0 << 20) + CONFIG_SYS_SDRAM_BASE)