pwsh1: get rid of unused lines
This commit is contained in:
Takumi Sueda
Suguru Saito
parent
107a5a5b9b
commit
61671339a9
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@ -54,7 +54,7 @@ int board_early_init_f(void)
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int dram_init(void)
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{
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gd->ram_size = 0x8000000; // 128MiB
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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@ -67,20 +67,20 @@ int board_init(void)
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}
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#ifdef CONFIG_CMD_MMC
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static int mx28evk_mmc_wp(int id)
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static int brain_mmc_wp(int id)
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{
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return 0;
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}
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static int mx28evk_mmc_cd(int id)
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static int brain_mmc_cd(int id)
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{
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return 1;
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}
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int board_mmc_init(bd_t *bis)
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{
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mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, mx28evk_mmc_cd);
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mxsmmc_initialize(bis, 1, mx28evk_mmc_wp, mx28evk_mmc_cd);
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mxsmmc_initialize(bis, 0, brain_mmc_wp, brain_mmc_cd);
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mxsmmc_initialize(bis, 1, brain_mmc_wp, brain_mmc_cd);
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/* Turn on the SD*/
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gpio_direction_output(MX28_PAD_SSP2_SS2__GPIO_2_21, 0);
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@ -88,60 +88,6 @@ int board_mmc_init(bd_t *bis)
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}
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#endif
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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struct mxs_clkctrl_regs *clkctrl_regs =
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(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
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struct eth_device *dev;
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int ret;
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ret = cpu_eth_init(bis);
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if (ret)
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return ret;
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/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
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writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
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&clkctrl_regs->hw_clkctrl_enet);
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/* Power-on FECs */
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gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
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/* Reset FEC PHYs */
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gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
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udelay(200);
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gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
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ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC0\n");
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return ret;
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}
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ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
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if (ret) {
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puts("FEC MXS: Unable to init FEC1\n");
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return ret;
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}
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dev = eth_get_dev_by_name("FEC0");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC0 device entry\n");
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return -EINVAL;
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}
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dev = eth_get_dev_by_name("FEC1");
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if (!dev) {
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puts("FEC MXS: Unable to get FEC1 device entry\n");
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return -EINVAL;
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}
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return ret;
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}
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#endif
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#ifdef CONFIG_VIDEO_MXS
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static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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{
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@ -10,20 +10,21 @@ CONFIG_SPL=y
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CONFIG_NR_DRAM_BANKS=1
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_ARCH_MISC_INIT=y
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# CONFIG_SPL_FRAMEWORK is not set
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_DATE=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_ENV_IS_IN_MMC=y
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# CONFIG_NET is not set
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CONFIG_MMC_MXS=y
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CONFIG_CONS_INDEX=0
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CONFIG_SPI=y
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CONFIG_MXS_SPI=y
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CONFIG_OF_LIBFDT=y
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@ -22,11 +22,7 @@
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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/* Environment */
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#ifndef CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE (16 * 1024)
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#else
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#define CONFIG_ENV_SIZE (4 * 1024)
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#endif
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#define CONFIG_ENV_OVERWRITE
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/* Environment is in MMC */
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@ -35,64 +31,12 @@
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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/* Environment is in NAND */
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#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#define CONFIG_ENV_SECT_SIZE (128 * 1024)
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#define CONFIG_ENV_RANGE (512 * 1024)
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#define CONFIG_ENV_OFFSET 0x300000
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#define CONFIG_ENV_OFFSET_REDUND \
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(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
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#endif
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/* Environment is in SPI flash */
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#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_OFFSET 0x40000 /* 256K */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
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#define CONFIG_ENV_SECT_SIZE 0x1000
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_BUS 2
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#define CONFIG_ENV_SPI_MAX_HZ 24000000
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#define CONFIG_ENV_SPI_MODE SPI_MODE_0
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#endif
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/* UBI and NAND partitioning */
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/* FEC Ethernet on SoC */
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#ifdef CONFIG_CMD_NET
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#define CONFIG_FEC_MXC
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#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE
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#define CONFIG_MX28_FEC_MAC_IN_OCOTP
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#endif
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/* RTC */
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#ifdef CONFIG_CMD_DATE
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#define CONFIG_RTC_MXS
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#endif
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_EHCI_MXS_PORT1
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
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#endif
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/* SPI */
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#ifdef CONFIG_CMD_SPI
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#define CONFIG_DEFAULT_SPI_BUS 2
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#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
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/* SPI Flash */
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#ifdef CONFIG_CMD_SF
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#define CONFIG_SF_DEFAULT_BUS 2
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#define CONFIG_SF_DEFAULT_CS 0
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/* this may vary and depends on the installed chip */
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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#define CONFIG_SF_DEFAULT_SPEED 24000000
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#endif
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#endif
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/* Framebuffer support */
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_MXS_MODE_SYSTEM
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