pwsh1: add board
This commit is contained in:
Takumi Sueda
Suguru Saito
parent
ea57b7c46c
commit
107a5a5b9b
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@ -49,6 +49,10 @@ config TARGET_MX28EVK
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config TARGET_XEA
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bool "Support XEA"
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config TARGET_PWSH1
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bool "Support PW-SH1"
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select BOARD_EARLY_INIT_F
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endchoice
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config SYS_SOC
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@ -57,5 +61,6 @@ config SYS_SOC
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source "board/freescale/mx28evk/Kconfig"
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source "board/liebherr/xea/Kconfig"
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source "board/ppcag/bg0900/Kconfig"
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source "board/sharp/pwsh1/Kconfig"
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endif
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@ -0,0 +1,15 @@
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if TARGET_PWSH1
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config SYS_BOARD
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default "pwsh1"
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config SYS_VENDOR
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default "sharp"
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config SYS_SOC
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default "mxs"
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config SYS_CONFIG_NAME
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default "pwsh1"
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endif
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@ -0,0 +1,6 @@
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PW-SH1 BOARD
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M: Takumi Sueda <puhitaku@gmail.com>
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S: Maintained
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F: board/sharp/pwsh1/
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F: include/configs/pwsh1.h
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F: configs/pwsh1_defconfig
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@ -0,0 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2020 Takumi Sueda <puhitaku@gmail.com>
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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ifndef CONFIG_SPL_BUILD
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obj-y := pwsh1.o
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else
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obj-y := iomux.o
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endif
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@ -0,0 +1,13 @@
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SHARP Brain PW-SH1
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==================
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Support for PW-SH1 and as-yet-unknown forthcoming Brain boards.
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Files of the PW-SH1 port
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--------------------------
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arch/arm/cpu/arm926ejs/mxs/ - The CPU support code for the Freescale i.MX28
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arch/arm/include/asm/arch-mxs/ - Header files for the Freescale i.MX28
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board/sharp/pwsh1/ - PW-SH1 board specific files
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include/configs/pwsh1.h - PW-SH1 configuration file
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@ -0,0 +1,227 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SHARP PW-SH1 IOMUX setup
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*
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* Copyright (C) 2020 Takumi Sueda <puhitaku@gmail.com>
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <config.h>
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#include <asm/io.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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#define MUX_CONFIG_LCD (MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
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#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
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const iomux_cfg_t iomux_setup[] = {
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///* MMC0 */
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MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA4__SSP0_D4 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA5__SSP0_D5 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA6__SSP0_D6 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DATA7__SSP0_D7 | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
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MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
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(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SSP0_SCK__SSP0_SCK |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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/* write protect */
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//MX28_PAD_SSP1_SCK__GPIO_2_12,
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/* eMMC power enable */
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MX28_PAD_PWM3__GPIO_3_28 |
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(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
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/* MMC1 */
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MX28_PAD_GPMI_D00__SSP1_D0 | MUX_CONFIG_SSP1,
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MX28_PAD_GPMI_D01__SSP1_D1 | MUX_CONFIG_SSP1,
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MX28_PAD_GPMI_D02__SSP1_D2 | MUX_CONFIG_SSP1,
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MX28_PAD_GPMI_D03__SSP1_D3 | MUX_CONFIG_SSP1,
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MX28_PAD_GPMI_RDY1__SSP1_CMD | MUX_CONFIG_SSP1,
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MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT |
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(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_GPMI_WRN__SSP1_SCK |
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(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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/* SD slot power enable */
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MX28_PAD_SSP2_SS2__GPIO_2_21 |
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(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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/* USB */
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//MX28_PAD_GPMI_RDY0__USB0_ID,
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MX28_PAD_ENET0_COL__GPIO_4_14 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
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MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TXD1__GPIO_4_8 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TXD0__GPIO_4_7 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TX_EN__GPIO_4_6 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_TX_CLK__GPIO_4_5 |
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MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_RX_EN__GPIO_4_2| MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_MDIO__GPIO_4_1 | MUX_CONFIG_GPIO,
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MX28_PAD_ENET0_MDC__GPIO_4_0 | MUX_CONFIG_GPIO,
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/* EMI */
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MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
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MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
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/* SPI2 (for SPI flash) */
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MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
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MX28_PAD_SSP2_SS0__SSP2_D3 |
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(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
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/* I2C */
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MX28_PAD_I2C0_SCL__I2C0_SCL,
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MX28_PAD_I2C0_SDA__I2C0_SDA,
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MX28_PAD_PWM1__I2C1_SDA,
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MX28_PAD_PWM0__I2C1_SCL,
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MX28_PAD_AUART0_RTS__DUART_TX, // TP302
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MX28_PAD_AUART0_CTS__DUART_RX, // TP301
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/* LCD */
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MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
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MX28_PAD_LCD_RD_E__LCD_RD_E | MUX_CONFIG_LCD,
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MX28_PAD_LCD_WR_RWN__LCD_WR_RWN | MUX_CONFIG_LCD,
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MX28_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
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MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
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MX28_PAD_LCD_RESET__LCD_VSYNC | MUX_CONFIG_LCD,
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/* Regulator EN? */
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MX28_PAD_GPMI_ALE__GPIO_0_26 | (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL),
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MX28_PAD_GPMI_CLE__GPIO_0_27 | (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP),
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/* ILI9805 Reset? */
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MX28_PAD_ENET_CLK__GPIO_4_16 | MUX_CONFIG_LCD,
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/* GPIO */
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MX28_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D18__GPIO_1_18 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D19__GPIO_1_19 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D20__GPIO_1_20 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D21__GPIO_1_21 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D22__GPIO_1_22 | MUX_CONFIG_GPIO,
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MX28_PAD_LCD_D23__GPIO_1_23 | MUX_CONFIG_GPIO,
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MX28_PAD_SSP2_MISO__GPIO_2_18 | MUX_CONFIG_GPIO,
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MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO,
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MX28_PAD_SPDIF__GPIO_3_27 | MUX_CONFIG_GPIO,
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MX28_PAD_PWM3__GPIO_3_28 | MUX_CONFIG_GPIO,
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MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_GPIO,
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/* PWM */
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MX28_PAD_AUART1_RX__PWM_0 |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_AUART1_TX__PWM_1 |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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/* SAIF */
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MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SAIF0_MCLK__SAIF0_MCLK |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 |
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(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
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};
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#define HW_DRAM_CTL29 (0x74 >> 2)
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#define CS_MAP 0x1
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#define COLUMN_SIZE 0x2
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#define ADDR_PINS 0x1
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#define APREBIT 0xa
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#define HW_DRAM_CTL29_CONFIG (CS_MAP << 24 | COLUMN_SIZE << 16 | \
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ADDR_PINS << 8 | APREBIT)
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void mxs_adjust_memory_params(uint32_t *dram_vals)
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{
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}
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void board_init_ll(const uint32_t arg, const uint32_t *resptr)
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{
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mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
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}
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@ -0,0 +1,315 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* SHARP PW-SH1
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*
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* (C) Copyright 2020 Takumi Sueda.
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* Author: Takumi Sueda <puhitaku@gmail.com>
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*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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* Author: Fabio Estevam <fabio.estevam@freescale.com>
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*
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* Based on m28evk.c:
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/iomux-mx28.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <linux/mii.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <errno.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Functions
|
||||
*/
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* IO0 clock at 480MHz */
|
||||
mxs_set_ioclk(MXC_IOCLK0, 480000);
|
||||
/* IO1 clock at 480MHz */
|
||||
mxs_set_ioclk(MXC_IOCLK1, 480000);
|
||||
|
||||
/* SSP0 clock at 96MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
|
||||
/* SSP1 clock at 96MHz */
|
||||
mxs_set_sspclk(MXC_SSPCLK1, 96000, 0);
|
||||
|
||||
#ifdef CONFIG_CMD_USB
|
||||
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
|
||||
mxs_iomux_setup_pad(MX28_PAD_AUART2_RX__GPIO_3_8 |
|
||||
MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
|
||||
gpio_direction_output(MX28_PAD_AUART2_RX__GPIO_3_8, 1);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = 0x8000000; // 128MiB
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_MMC
|
||||
static int mx28evk_mmc_wp(int id)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mx28evk_mmc_cd(int id)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
||||
int board_mmc_init(bd_t *bis)
|
||||
{
|
||||
mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, mx28evk_mmc_cd);
|
||||
mxsmmc_initialize(bis, 1, mx28evk_mmc_wp, mx28evk_mmc_cd);
|
||||
|
||||
/* Turn on the SD*/
|
||||
gpio_direction_output(MX28_PAD_SSP2_SS2__GPIO_2_21, 0);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CMD_NET
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct mxs_clkctrl_regs *clkctrl_regs =
|
||||
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
struct eth_device *dev;
|
||||
int ret;
|
||||
|
||||
ret = cpu_eth_init(bis);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* MX28EVK uses ENET_CLK PAD to drive FEC clock */
|
||||
writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
|
||||
&clkctrl_regs->hw_clkctrl_enet);
|
||||
|
||||
/* Power-on FECs */
|
||||
gpio_direction_output(MX28_PAD_SSP1_DATA3__GPIO_2_15, 0);
|
||||
|
||||
/* Reset FEC PHYs */
|
||||
gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
|
||||
udelay(200);
|
||||
gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
|
||||
if (ret) {
|
||||
puts("FEC MXS: Unable to init FEC0\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = fecmxc_initialize_multi(bis, 1, 3, MXS_ENET1_BASE);
|
||||
if (ret) {
|
||||
puts("FEC MXS: Unable to init FEC1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev = eth_get_dev_by_name("FEC0");
|
||||
if (!dev) {
|
||||
puts("FEC MXS: Unable to get FEC0 device entry\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev = eth_get_dev_by_name("FEC1");
|
||||
if (!dev) {
|
||||
puts("FEC MXS: Unable to get FEC1 device entry\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VIDEO_MXS
|
||||
static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
|
||||
{
|
||||
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
|
||||
const unsigned int timeout = 0x10000;
|
||||
|
||||
if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
|
||||
(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
|
||||
®s->hw_lcdif_transfer_count);
|
||||
|
||||
writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
|
||||
®s->hw_lcdif_ctrl_clr);
|
||||
|
||||
if (data)
|
||||
writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
|
||||
|
||||
writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
|
||||
|
||||
if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
|
||||
timeout))
|
||||
return -ETIMEDOUT;
|
||||
|
||||
writel(payload, ®s->hw_lcdif_data);
|
||||
return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
|
||||
timeout);
|
||||
}
|
||||
|
||||
/* https://github.com/muojie/spec_mtk/blob/master/MTK_driver/spec/LCM/ILI9805/ILI9805_AN_V0.4_20120330.pdf */
|
||||
|
||||
static const struct {
|
||||
uint32_t payload;
|
||||
unsigned int data;
|
||||
uint32_t delay;
|
||||
} lcd_regs[] = {
|
||||
{ 0xff, 0, 0 }, /* EXTC Command Set Enable */
|
||||
{ 0xff, 1, 0 }, { 0x98, 1, 0 }, { 0x05, 1, 0 },
|
||||
{ 0xfd, 0, 0 }, /* PFM Type C */
|
||||
{ 0x03, 1, 0 }, { 0x13, 1, 0 }, { 0x44, 1, 0 }, { 0x00, 1, 0 },
|
||||
{ 0xf8, 0, 0 }, /* PFM Type C */
|
||||
{ 0x18, 1, 0 }, { 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x18, 1, 0 },
|
||||
{ 0x02, 1, 0 }, { 0x02, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 },
|
||||
{ 0x01, 1, 0 }, { 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
|
||||
{ 0x30, 1, 0 }, { 0x01, 1, 0 }, { 0x01, 1, 0 },
|
||||
{ 0xb8, 0, 0 }, /* DBI Type B Interface Setting */
|
||||
{ 0x72, 1, 0 },
|
||||
{ 0xf1, 0, 0 }, /* Gate Modulation */
|
||||
{ 0x00, 1, 0 },
|
||||
{ 0xf2, 0, 0 }, /* CR/EQ/PC */
|
||||
{ 0x00, 1, 0 }, { 0x58, 1, 0 }, { 0x40, 1, 0 },
|
||||
{ 0xfc, 0, 0 }, /* LVGL Voltage Setting? */
|
||||
{ 0x04, 1, 0 }, { 0x0f, 1, 0 }, { 0x01, 1, 0 },
|
||||
{ 0xeb, 0, 0 }, /* ? */
|
||||
{ 0x08, 1, 0 }, { 0x0f, 1, 0 },
|
||||
{ 0xe0, 0, 0 }, /* Positive Gamma Control */
|
||||
{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x35, 1, 0 }, { 0x15, 1, 0 },
|
||||
{ 0x13, 1, 0 }, { 0x16, 1, 0 }, { 0x0a, 1, 0 }, { 0x06, 1, 0 },
|
||||
{ 0x03, 1, 0 }, { 0x06, 1, 0 }, { 0x05, 1, 0 }, { 0x0a, 1, 0 },
|
||||
{ 0x08, 1, 0 }, { 0x23, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
|
||||
{ 0xe1, 0, 0 }, /* Negative Gamma Control */
|
||||
{ 0x0a, 1, 0 }, { 0x23, 1, 0 }, { 0x28, 1, 0 }, { 0x10, 1, 0 },
|
||||
{ 0x11, 1, 0 }, { 0x16, 1, 0 }, { 0x0b, 1, 0 }, { 0x0a, 1, 0 },
|
||||
{ 0x02, 1, 0 }, { 0x05, 1, 0 }, { 0x04, 1, 0 }, { 0x0a, 1, 0 },
|
||||
{ 0x08, 1, 0 }, { 0x1d, 1, 0 }, { 0x1a, 1, 0 }, { 0x00, 1, 0 },
|
||||
{ 0xc1, 0, 0 }, /* Power Control 1 */
|
||||
{ 0x13, 1, 0 }, { 0x28, 1, 0 }, { 0x08, 1, 0 }, { 0x26, 1, 0 },
|
||||
{ 0xc7, 0, 0 }, /* VCOM Control */
|
||||
{ 0x90, 1, 0 },
|
||||
{ 0xb1, 0, 0 }, /* Frame Rate Control */
|
||||
{ 0x00, 1, 0 }, { 0x12, 1, 0 }, { 0x14, 1, 0 },
|
||||
{ 0xb4, 0, 0 }, /* Display Inversion Control */
|
||||
{ 0x02, 1, 0 },
|
||||
{ 0xbb, 0, 0 }, /* ? */
|
||||
{ 0x14, 1, 0 }, { 0x55, 1, 0 },
|
||||
{ 0x36, 0, 0 }, /* Memory Access Control */
|
||||
{ 0x28, 1, 0 },
|
||||
{ 0x3a, 0, 0 }, /* Interface Pixel Format */
|
||||
{ 0x55, 1, 0 },
|
||||
{ 0x21, 0, 0 }, /* Display Inversion On */
|
||||
{ 0xb6, 0, 0 }, /* MCU/RGB Interface Select */
|
||||
{ 0x01, 1, 0 }, { 0x80, 1, 0 }, { 0x8f, 1, 0 },
|
||||
{ 0x44, 0, 0 }, /* Write Tear Scan Line? */
|
||||
{ 0x00, 1, 0 }, { 0x00, 1, 0 },
|
||||
{ 0x35, 0, 0 }, /* Tearing Effect Line On */
|
||||
{ 0x00, 1, 0 },
|
||||
{ 0x11, 0, 120 }, /* Sleep Out */
|
||||
{ 0x29, 0, 20 }, /* Display On */
|
||||
{ 0x2a, 0, 0 }, /* Column Address Set */
|
||||
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x03, 1, 0 }, { 0x1f, 1, 0 },
|
||||
{ 0x2b, 0, 0 }, /* Page Address Set */
|
||||
{ 0x00, 1, 0 }, { 0x00, 1, 0 }, { 0x01, 1, 0 }, { 0xdf, 1, 0 },
|
||||
{ 0x2c, 0, 0 }, /* Memory Write*/
|
||||
};
|
||||
|
||||
void mxsfb_system_setup(void)
|
||||
{
|
||||
struct mxs_lcdif_regs *lcdif = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
|
||||
struct mxs_clkctrl_regs *xtal = (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
|
||||
struct mxs_pwm_regs *pwm = (struct mxs_pwm_regs *)MXS_PWM_BASE;
|
||||
int i, j;
|
||||
uint32_t valid_data;
|
||||
|
||||
valid_data = readl(&lcdif->hw_lcdif_ctrl1) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
|
||||
writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
|
||||
&lcdif->hw_lcdif_ctrl1);
|
||||
|
||||
/* Switch the LCDIF into System-Mode */
|
||||
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
|
||||
LCDIF_CTRL_BYPASS_COUNT, &lcdif->hw_lcdif_ctrl_clr);
|
||||
writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
|
||||
writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
|
||||
|
||||
writel((0x01 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
|
||||
(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
|
||||
(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
|
||||
(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
|
||||
&lcdif->hw_lcdif_timing);
|
||||
|
||||
/* Enable LCD Controller */
|
||||
gpio_direction_output(MX28_PAD_GPMI_ALE__GPIO_0_26, 1);
|
||||
gpio_direction_output(MX28_PAD_GPMI_CLE__GPIO_0_27, 1);
|
||||
gpio_direction_output(MX28_PAD_ENET_CLK__GPIO_4_16, 1);
|
||||
mdelay(20);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
|
||||
mxsfb_write_byte(lcd_regs[i].payload, lcd_regs[i].data);
|
||||
if (lcd_regs[i].delay)
|
||||
mdelay(lcd_regs[i].delay);
|
||||
}
|
||||
|
||||
/* Fill black */
|
||||
for (i = 0; i < 480; i++) {
|
||||
for (j = 0; j < 800; j++) {
|
||||
mxsfb_write_byte(0, 1);
|
||||
}
|
||||
}
|
||||
|
||||
writel(valid_data, &lcdif->hw_lcdif_ctrl1);
|
||||
|
||||
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
|
||||
&lcdif->hw_lcdif_ctrl_set);
|
||||
|
||||
/* Turn on backlight */
|
||||
writel(CLKCTRL_XTAL_PWM_CLK24M_GATE, &xtal->hw_clkctrl_xtal_clr);
|
||||
mdelay(1);
|
||||
writel(PWM_CTRL_SFTRST, &pwm->hw_pwm_ctrl_clr);
|
||||
writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
|
||||
|
||||
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_clr);
|
||||
|
||||
writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
|
||||
(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET), &pwm->hw_pwm_active0_set);
|
||||
|
||||
writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
|
||||
(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET), &pwm->hw_pwm_active1_set);
|
||||
|
||||
writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
|
||||
(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
|
||||
(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
|
||||
(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET), &pwm->hw_pwm_period0_set);
|
||||
|
||||
writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
|
||||
(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
|
||||
(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
|
||||
(0x07cf << PWM_PERIOD1_PERIOD_OFFSET), &pwm->hw_pwm_period1_set);
|
||||
|
||||
writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE, &pwm->hw_pwm_ctrl_set);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX28=y
|
||||
CONFIG_SYS_TEXT_BASE=0x40200000
|
||||
CONFIG_SPL_GPIO_SUPPORT=y
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_TARGET_PWSH1=y
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_ARCH_MISC_INIT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_MMC_MXS=y
|
||||
CONFIG_CONS_INDEX=0
|
||||
CONFIG_SPI=y
|
||||
CONFIG_MXS_SPI=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2011 Takumi Sueda.
|
||||
* Author: Takumi Sueda <puhitaku@gmail.com>
|
||||
*
|
||||
* (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
* Author: Fabio Estevam <fabio.estevam@freescale.com>
|
||||
*
|
||||
* Based on m28evk.h:
|
||||
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
|
||||
* on behalf of DENX Software Engineering GmbH
|
||||
*/
|
||||
#ifndef __CONFIGS_PWSH1_H__
|
||||
#define __CONFIGS_PWSH1_H__
|
||||
|
||||
/* System configurations */
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK
|
||||
|
||||
/* Memory configuration */
|
||||
#define PHYS_SDRAM_1 0x40000000 /* Base address */
|
||||
#define PHYS_SDRAM_1_SIZE 0x8000000 /* Max 128 MB RAM */
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
|
||||
/* Environment */
|
||||
#ifndef CONFIG_ENV_IS_IN_SPI_FLASH
|
||||
#define CONFIG_ENV_SIZE (16 * 1024)
|
||||
#else
|
||||
#define CONFIG_ENV_SIZE (4 * 1024)
|
||||
#endif
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/* Environment is in MMC */
|
||||
#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC)
|
||||
#define CONFIG_ENV_OFFSET (256 * 1024)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#endif
|
||||
|
||||
/* Environment is in NAND */
|
||||
#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND)
|
||||
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
|
||||
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
|
||||
#define CONFIG_ENV_RANGE (512 * 1024)
|
||||
#define CONFIG_ENV_OFFSET 0x300000
|
||||
#define CONFIG_ENV_OFFSET_REDUND \
|
||||
(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
|
||||
#endif
|
||||
|
||||
/* Environment is in SPI flash */
|
||||
#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
|
||||
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
|
||||
#define CONFIG_ENV_OFFSET 0x40000 /* 256K */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x1000
|
||||
#define CONFIG_ENV_SPI_CS 0
|
||||
#define CONFIG_ENV_SPI_BUS 2
|
||||
#define CONFIG_ENV_SPI_MAX_HZ 24000000
|
||||
#define CONFIG_ENV_SPI_MODE SPI_MODE_0
|
||||
#endif
|
||||
|
||||
/* UBI and NAND partitioning */
|
||||
|
||||
/* FEC Ethernet on SoC */
|
||||
#ifdef CONFIG_CMD_NET
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE
|
||||
#define CONFIG_MX28_FEC_MAC_IN_OCOTP
|
||||
#endif
|
||||
|
||||
/* RTC */
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_MXS
|
||||
#endif
|
||||
|
||||
/* USB */
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#define CONFIG_EHCI_MXS_PORT1
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
||||
#endif
|
||||
|
||||
/* SPI */
|
||||
#ifdef CONFIG_CMD_SPI
|
||||
#define CONFIG_DEFAULT_SPI_BUS 2
|
||||
#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0
|
||||
|
||||
/* SPI Flash */
|
||||
#ifdef CONFIG_CMD_SF
|
||||
#define CONFIG_SF_DEFAULT_BUS 2
|
||||
#define CONFIG_SF_DEFAULT_CS 0
|
||||
/* this may vary and depends on the installed chip */
|
||||
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
|
||||
#define CONFIG_SF_DEFAULT_SPEED 24000000
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Framebuffer support */
|
||||
#ifdef CONFIG_VIDEO
|
||||
#define CONFIG_VIDEO_MXS_MODE_SYSTEM
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
#define CONFIG_BMP_16BPP
|
||||
#define CONFIG_VIDEO_BMP_RLE8
|
||||
#define CONFIG_VIDEO_BMP_GZIP
|
||||
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
|
||||
#define LCD_BPP LCD_COLOR16
|
||||
#endif
|
||||
|
||||
/* Boot Linux */
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_LOADADDR 0x42000000
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Extra Environment */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"videomode=video=ctfb:x:800,y:480,depth:16,pclk:30857,le:0,ri:0,up:0,lo:0,hs:0,vs:0,sync:0,vmode:0\0" \
|
||||
"bootdelay=0\0" \
|
||||
"image=zImage\0" \
|
||||
"console_mainline=ttyAMA0\0" \
|
||||
"fdt_file=imx28-evk.dtb\0" \
|
||||
"fdt_addr=0x41000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"mmcdev=1\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk1p2 rw rootwait\0" \
|
||||
"mmcargs=setenv bootargs console=${console_mainline},${baudrate} console=tty1 " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
/* The rest of the configuration is shared */
|
||||
#include <configs/mxs.h>
|
||||
|
||||
#endif /* __CONFIGS_PWSH1_H__ */
|
||||
Loading…
Reference in New Issue