mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
powerpc, qe: add DTS support for parallel I/O ports
add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END
This commit is contained in:
Heiko Schocher
parent
9bd6444826
commit
5990b05951
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@ -27,7 +27,9 @@ obj-y += cpu_init.o
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obj-y += speed.o
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obj-y += interrupts.o
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obj-y += ecc.o
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ifndef CONFIG_PINCTRL
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obj-$(CONFIG_QE) += qe_io.o
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endif
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obj-$(CONFIG_FSL_SERDES) += serdes.o
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ifndef CONFIG_ARCH_MPC8308
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obj-$(CONFIG_PCI) += pci.o
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@ -14,6 +14,9 @@
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#include <usb/ehci-ci.h>
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#endif
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#include <linux/delay.h>
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#ifdef CONFIG_QE
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#include <fsl_qe.h>
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#endif
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#include "lblaw/lblaw.h"
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#include "elbc/elbc.h"
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@ -28,6 +31,7 @@ extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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#if !defined(CONFIG_PINCTRL)
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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@ -44,6 +48,7 @@ static void config_qe_ioports(void)
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}
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}
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#endif
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#endif
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/*
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* Breathe some life into the CPU...
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@ -190,10 +195,13 @@ void cpu_init_f (volatile immap_t * im)
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__raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir);
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#endif
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#if !defined(CONFIG_PINCTRL)
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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#endif
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/* Set up preliminary BR/OR regs */
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init_early_memctl_regs();
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@ -12,24 +12,35 @@
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#include <asm/immap_83xx.h>
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#define NUM_OF_PINS 32
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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u32 2bit_mask;
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u32 2bit_dir;
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u32 2bit_assign;
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u32 1bit_mask;
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u32 tmp_val;
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immap_t *im;
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qepio83xx_t *par_io;
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int offset;
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im = (immap_t *)CONFIG_SYS_IMMR;
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par_io = (qepio83xx_t *)&im->qepio;
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/** qe_cfg_iopin configure one io pin setting
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*
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* @par_io: pointer to parallel I/O base
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
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int open_drain, int assign)
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{
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u32 dbit_mask;
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u32 dbit_dir;
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u32 dbit_asgn;
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u32 bit_mask;
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u32 tmp_val;
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int offset;
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offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
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/* Calculate pin location and 2bit mask and dir */
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2bit_mask = (u32)(0x3 << offset);
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2bit_dir = (u32)(dir << offset);
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dbit_mask = (u32)(0x3 << offset);
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dbit_dir = (u32)(dir << offset);
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/* Setup the direction */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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@ -37,35 +48,57 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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in_be32(&par_io->ioport[port].dir1);
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].dir2, ~2bit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir2, 2bit_dir | tmp_val);
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out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].dir1, ~2bit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir1, 2bit_dir | tmp_val);
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out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
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}
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/* Calculate pin location for 1bit mask */
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1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
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bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
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/* Setup the open drain */
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tmp_val = in_be32(&par_io->ioport[port].podr);
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if (open_drain)
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out_be32(&par_io->ioport[port].podr, 1bit_mask | tmp_val);
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out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
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else
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out_be32(&par_io->ioport[port].podr, ~1bit_mask & tmp_val);
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out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
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/* Setup the assignment */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].ppar2) :
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in_be32(&par_io->ioport[port].ppar1);
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2bit_assign = (u32)(assign << offset);
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dbit_asgn = (u32)(assign << offset);
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/* Clear and set 2 bits mask */
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].ppar2, ~2bit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar2, 2bit_assign | tmp_val);
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out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].ppar1, ~2bit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar1, 2bit_assign | tmp_val);
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out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
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}
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}
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#if !defined(CONFIG_PINCTRL)
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/** qe_config_iopin configure one io pin setting
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*
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
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qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
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}
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#endif
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@ -205,6 +205,13 @@ config PINCTRL_QCA953X
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the GPIO definitions and pin control functions for each available
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multiplex function.
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config PINCTRL_QE
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bool "QE based pinctrl driver, like on mpc83xx"
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depends on DM
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help
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This option is to enable the QE pinctrl driver for QE based io
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controller.
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config PINCTRL_ROCKCHIP_RV1108
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bool "Rockchip rv1108 pin control driver"
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depends on DM
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@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MTK) += mediatek/
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obj-$(CONFIG_PINCTRL_MSCC) += mscc/
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obj-$(CONFIG_ARCH_MVEBU) += mvebu/
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obj-$(CONFIG_ARCH_NEXELL) += nexell/
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obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o
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obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
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obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
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obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
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255
drivers/pinctrl/pinctrl-qe-io.c
Normal file
255
drivers/pinctrl/pinctrl-qe-io.c
Normal file
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@ -0,0 +1,255 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on source code of Shlomi Gridish
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/immap_83xx.h>
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#if defined(CONFIG_PINCTRL)
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <linux/ioport.h>
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/**
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* struct qe_io_platdata
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*
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* @base: Base register address
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* @num_par_io_ports number of io ports
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*/
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struct qe_io_platdata {
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qepio83xx_t *base;
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u32 num_io_ports;
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};
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#endif
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#define NUM_OF_PINS 32
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/** qe_cfg_iopin configure one io pin setting
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*
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* @par_io: pointer to parallel I/O base
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir,
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int open_drain, int assign)
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{
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u32 dbit_mask;
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u32 dbit_dir;
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u32 dbit_asgn;
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u32 bit_mask;
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u32 tmp_val;
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int offset;
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offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2);
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/* Calculate pin location and 2bit mask and dir */
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dbit_mask = (u32)(0x3 << offset);
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dbit_dir = (u32)(dir << offset);
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/* Setup the direction */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].dir2) :
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in_be32(&par_io->ioport[port].dir1);
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val);
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}
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/* Calculate pin location for 1bit mask */
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bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1)));
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/* Setup the open drain */
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tmp_val = in_be32(&par_io->ioport[port].podr);
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if (open_drain)
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out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val);
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else
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out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val);
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/* Setup the assignment */
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tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ?
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in_be32(&par_io->ioport[port].ppar2) :
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in_be32(&par_io->ioport[port].ppar1);
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dbit_asgn = (u32)(assign << offset);
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/* Clear and set 2 bits mask */
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if (pin > (NUM_OF_PINS / 2) - 1) {
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out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val);
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} else {
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out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val);
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out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val);
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}
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}
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#if !defined(CONFIG_PINCTRL)
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/** qe_config_iopin configure one io pin setting
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*
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* @port: io pin port
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* @pin: io pin number which get configured
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* @dir: direction of io pin 2 bits valid
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* 00 = pin disabled
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* 01 = output
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* 10 = input
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* 11 = pin is I/O
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* @open_drain: is pin open drain
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* @assign: pin assignment registers select the function of the pin
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*/
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void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign)
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio;
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qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign);
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}
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#else
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static int qe_io_ofdata_to_platdata(struct udevice *dev)
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{
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struct qe_io_platdata *plat = dev->platdata;
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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plat->base = (qepio83xx_t *)addr;
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if (dev_read_u32(dev, "num-ports", &plat->num_io_ports))
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return -EINVAL;
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return 0;
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}
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/**
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* par_io_of_config_node config
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* @dev: pointer to pinctrl device
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* @pio: ofnode of pinconfig property
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*/
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static int par_io_of_config_node(struct udevice *dev, ofnode pio)
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{
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struct qe_io_platdata *plat = dev->platdata;
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qepio83xx_t *par_io = plat->base;
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const unsigned int *pio_map;
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int pio_map_len;
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pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len);
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if (!pio_map)
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return -ENOENT;
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pio_map_len /= sizeof(unsigned int);
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if ((pio_map_len % 6) != 0) {
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dev_err(dev, "%s: pio-map format wrong!\n", __func__);
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return -EINVAL;
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}
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while (pio_map_len > 0) {
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/*
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* column pio_map[5] from linux (has_irq) not
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* supported in u-boot yet.
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*/
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qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1],
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(int)pio_map[2], (int)pio_map[3],
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(int)pio_map[4]);
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pio_map += 6;
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pio_map_len -= 6;
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}
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return 0;
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}
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int par_io_of_config(struct udevice *dev)
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{
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u32 phandle;
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ofnode pio;
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int err;
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err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle);
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if (err) {
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dev_err(dev, "%s: pio-handle not available\n", __func__);
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return err;
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}
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pio = ofnode_get_by_phandle(phandle);
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if (!ofnode_valid(pio)) {
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dev_err(dev, "%s: unable to find node\n", __func__);
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return -EINVAL;
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}
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/* To Do: find pinctrl device and pass it */
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return par_io_of_config_node(NULL, pio);
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}
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/*
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* This is not nice!
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* pinsettings should work with "pinctrl-" properties.
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* Unfortunately on mpc83xx powerpc linux device trees
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* devices handle this with "pio-handle" properties ...
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*
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* Even worser, old board code inits all par_io
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* pins in one step, if U-Boot uses the device
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* or not. So init all par_io definitions here too
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* as linux does this also.
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*/
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static void config_qe_ioports(struct udevice *dev)
|
||||
{
|
||||
ofnode ofn;
|
||||
|
||||
for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn);
|
||||
ofn = dev_read_next_subnode(ofn)) {
|
||||
/*
|
||||
* ignore errors here, as may the subnode
|
||||
* has no pio-handle
|
||||
*/
|
||||
par_io_of_config_node(dev, ofn);
|
||||
}
|
||||
}
|
||||
|
||||
static int par_io_pinctrl_probe(struct udevice *dev)
|
||||
{
|
||||
config_qe_ioports(dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
const struct pinctrl_ops par_io_pinctrl_ops = {
|
||||
.set_state = par_io_pinctrl_set_state,
|
||||
};
|
||||
|
||||
static const struct udevice_id par_io_pinctrl_match[] = {
|
||||
{ .compatible = "fsl,mpc8360-par_io"},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(par_io_pinctrl) = {
|
||||
.name = "par-io-pinctrl",
|
||||
.id = UCLASS_PINCTRL,
|
||||
.of_match = of_match_ptr(par_io_pinctrl_match),
|
||||
.probe = par_io_pinctrl_probe,
|
||||
.ofdata_to_platdata = qe_io_ofdata_to_platdata,
|
||||
.platdata_auto_alloc_size = sizeof(struct qe_io_platdata),
|
||||
.ops = &par_io_pinctrl_ops,
|
||||
#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
#endif
|
||||
};
|
||||
#endif
|
||||
|
|
@ -296,4 +296,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware,
|
|||
qe_map_t *qe_immrr);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PINCTRL)
|
||||
int par_io_of_config(struct udevice *dev);
|
||||
#endif
|
||||
#endif /* __QE_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user