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https://github.com/brain-hackers/u-boot-brain
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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- No need to check before free in kendryte clk. - Only enable OF_BOARD_FIXUP if U-Boot is configured for S-Mode. - Reduce k210 dts DMA block size - Move timers into drivers/timer - Correct fu540 dts reg size of clint node
This commit is contained in:
commit
54908d9ae1
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@ -938,6 +938,8 @@ S: Maintained
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T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
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T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git
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F: arch/riscv/
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F: arch/riscv/
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F: cmd/riscv/
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F: cmd/riscv/
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F: drivers/timer/andes_plmt_timer.c
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F: drivers/timer/sifive_clint_timer.c
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F: tools/prelink-riscv.c
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F: tools/prelink-riscv.c
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RISC-V KENDRYTE
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RISC-V KENDRYTE
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@ -170,13 +170,6 @@ config ANDES_PLIC
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The Andes PLIC block holds memory-mapped claim and pending registers
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The Andes PLIC block holds memory-mapped claim and pending registers
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associated with software interrupt.
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associated with software interrupt.
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config ANDES_PLMT
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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config SYS_MALLOC_F_LEN
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config SYS_MALLOC_F_LEN
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default 0x1000
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default 0x1000
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@ -272,6 +265,6 @@ config STACK_SIZE_SHIFT
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default 14
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default 14
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config OF_BOARD_FIXUP
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config OF_BOARD_FIXUP
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default y if OF_SEPARATE
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default y if OF_SEPARATE && RISCV_SMODE
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endmenu
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endmenu
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@ -5,7 +5,7 @@ config RISCV_NDS
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imply CPU_RISCV
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
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imply SPL_CPU_SUPPORT
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imply SPL_CPU_SUPPORT
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imply SPL_OPENSBI
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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imply SPL_LOAD_FIT
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@ -62,7 +62,7 @@
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&cpu2_intc 3 &cpu2_intc 7
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&cpu2_intc 3 &cpu2_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu3_intc 3 &cpu3_intc 7
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&cpu4_intc 3 &cpu4_intc 7>;
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&cpu4_intc 3 &cpu4_intc 7>;
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reg = <0x0 0x2000000 0x0 0xc0000>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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u-boot,dm-spl;
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u-boot,dm-spl;
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};
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};
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prci: clock-controller@10000000 {
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prci: clock-controller@10000000 {
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@ -200,8 +200,8 @@
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dma-channels = <6>;
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dma-channels = <6>;
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snps,dma-masters = <2>;
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snps,dma-masters = <2>;
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snps,data-width = <5>;
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snps,data-width = <5>;
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snps,block-size = <0x400000 0x400000 0x400000
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snps,block-size = <0x200000 0x200000 0x200000
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0x400000 0x400000 0x400000>;
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0x200000 0x200000 0x200000>;
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snps,axi-max-burst-len = <256>;
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snps,axi-max-burst-len = <256>;
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status = "disabled";
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status = "disabled";
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};
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};
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@ -13,7 +13,6 @@ obj-y += cache.o
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ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
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ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
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obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
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obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
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obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
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obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
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obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o
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else
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else
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obj-$(CONFIG_SBI) += sbi.o
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obj-$(CONFIG_SBI) += sbi.o
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obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
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obj-$(CONFIG_SBI_IPI) += sbi_ipi.o
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@ -1,5 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: GPL-2.0+
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/*
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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*
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* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
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* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
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@ -8,19 +9,13 @@
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*/
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*/
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#include <common.h>
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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#include <asm/smp.h>
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#include <linux/err.h>
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#include <linux/err.h>
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/* MSIP registers */
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/* MSIP registers */
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#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
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#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
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/* mtime compare register */
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#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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@ -61,35 +56,3 @@ int riscv_get_ipi(int hart, int *pending)
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return 0;
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return 0;
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}
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}
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static u64 sifive_clint_get_count(struct udevice *dev)
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{
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return readq((void __iomem *)MTIME_REG(dev->priv));
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}
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static const struct timer_ops sifive_clint_ops = {
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.get_count = sifive_clint_get_count,
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};
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static int sifive_clint_probe(struct udevice *dev)
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{
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dev->priv = dev_read_addr_ptr(dev);
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if (!dev->priv)
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0" },
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{ }
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};
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U_BOOT_DRIVER(sifive_clint) = {
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.name = "sifive_clint",
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.id = UCLASS_TIMER,
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.of_match = sifive_clint_ids,
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.probe = sifive_clint_probe,
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.ops = &sifive_clint_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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@ -471,8 +471,7 @@ cleanup_gate:
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cleanup_div:
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cleanup_div:
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free(div);
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free(div);
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cleanup_mux:
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cleanup_mux:
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if (mux)
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free(mux);
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free(mux);
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return comp;
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return comp;
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}
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}
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@ -53,6 +53,13 @@ config ALTERA_TIMER
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Select this to enable a timer for Altera devices. Please find
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Select this to enable a timer for Altera devices. Please find
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details on the "Embedded Peripherals IP User Guide" of Altera.
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details on the "Embedded Peripherals IP User Guide" of Altera.
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config ANDES_PLMT_TIMER
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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config ARC_TIMER
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config ARC_TIMER
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bool "ARC timer support"
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bool "ARC timer support"
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depends on TIMER && ARC && CLK
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depends on TIMER && ARC && CLK
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@ -5,6 +5,7 @@
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obj-y += timer-uclass.o
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obj-y += timer-uclass.o
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obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
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obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
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obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
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obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
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obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o
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obj-$(CONFIG_ARC_TIMER) += arc_timer.o
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obj-$(CONFIG_ARC_TIMER) += arc_timer.o
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obj-$(CONFIG_AST_TIMER) += ast_timer.o
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obj-$(CONFIG_AST_TIMER) += ast_timer.o
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obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
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obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o
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@ -18,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
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obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
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obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
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obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
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obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
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obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
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obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o
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obj-$(CONFIG_STI_TIMER) += sti-timer.o
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obj-$(CONFIG_STI_TIMER) += sti-timer.o
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obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
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obj-$(CONFIG_STM32_TIMER) += stm32_timer.o
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obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
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obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o
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47
drivers/timer/sifive_clint_timer.c
Normal file
47
drivers/timer/sifive_clint_timer.c
Normal file
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@ -0,0 +1,47 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020, Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <linux/err.h>
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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static u64 sifive_clint_get_count(struct udevice *dev)
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{
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return readq((void __iomem *)MTIME_REG(dev->priv));
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}
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static const struct timer_ops sifive_clint_ops = {
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.get_count = sifive_clint_get_count,
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};
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static int sifive_clint_probe(struct udevice *dev)
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{
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dev->priv = dev_read_addr_ptr(dev);
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if (!dev->priv)
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0" },
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{ }
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};
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U_BOOT_DRIVER(sifive_clint) = {
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.name = "sifive_clint",
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.id = UCLASS_TIMER,
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.of_match = sifive_clint_ids,
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.probe = sifive_clint_probe,
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.ops = &sifive_clint_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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