diff --git a/MAINTAINERS b/MAINTAINERS index fc4fad46ee..69a5bc3768 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -938,6 +938,8 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-riscv.git F: arch/riscv/ F: cmd/riscv/ +F: drivers/timer/andes_plmt_timer.c +F: drivers/timer/sifive_clint_timer.c F: tools/prelink-riscv.c RISC-V KENDRYTE diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index aaa3b833a5..30b05408b1 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -170,13 +170,6 @@ config ANDES_PLIC The Andes PLIC block holds memory-mapped claim and pending registers associated with software interrupt. -config ANDES_PLMT - bool - depends on RISCV_MMODE || SPL_RISCV_MMODE - help - The Andes PLMT block holds memory-mapped mtime register - associated with timer tick. - config SYS_MALLOC_F_LEN default 0x1000 @@ -272,6 +265,6 @@ config STACK_SIZE_SHIFT default 14 config OF_BOARD_FIXUP - default y if OF_SEPARATE + default y if OF_SEPARATE && RISCV_SMODE endmenu diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig index 5cb5bb51eb..327b74e20a 100644 --- a/arch/riscv/cpu/ax25/Kconfig +++ b/arch/riscv/cpu/ax25/Kconfig @@ -5,7 +5,7 @@ config RISCV_NDS imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE) - imply ANDES_PLMT if (RISCV_MMODE || SPL_RISCV_MMODE) + imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE) imply SPL_CPU_SUPPORT imply SPL_OPENSBI imply SPL_LOAD_FIT diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index a06e1b11c6..b7cd600b8c 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -62,7 +62,7 @@ &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; - reg = <0x0 0x2000000 0x0 0xc0000>; + reg = <0x0 0x2000000 0x0 0x10000>; u-boot,dm-spl; }; prci: clock-controller@10000000 { diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi index 7605c01f3c..81ef8ca4f7 100644 --- a/arch/riscv/dts/k210.dtsi +++ b/arch/riscv/dts/k210.dtsi @@ -200,8 +200,8 @@ dma-channels = <6>; snps,dma-masters = <2>; snps,data-width = <5>; - snps,block-size = <0x400000 0x400000 0x400000 - 0x400000 0x400000 0x400000>; + snps,block-size = <0x200000 0x200000 0x200000 + 0x200000 0x200000 0x200000>; snps,axi-max-burst-len = <256>; status = "disabled"; }; diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile index 10ac5b06d3..12c14f2019 100644 --- a/arch/riscv/lib/Makefile +++ b/arch/riscv/lib/Makefile @@ -13,7 +13,6 @@ obj-y += cache.o ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y) obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o obj-$(CONFIG_ANDES_PLIC) += andes_plic.o -obj-$(CONFIG_ANDES_PLMT) += andes_plmt.o else obj-$(CONFIG_SBI) += sbi.o obj-$(CONFIG_SBI_IPI) += sbi_ipi.o diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c index a5572cb825..c8079dc510 100644 --- a/arch/riscv/lib/sifive_clint.c +++ b/arch/riscv/lib/sifive_clint.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* + * Copyright (C) 2020, Sean Anderson * Copyright (C) 2018, Bin Meng * * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT). @@ -8,19 +9,13 @@ */ #include -#include #include -#include #include -#include +#include #include /* MSIP registers */ #define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4) -/* mtime compare register */ -#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8) -/* mtime register */ -#define MTIME_REG(base) ((ulong)(base) + 0xbff8) DECLARE_GLOBAL_DATA_PTR; @@ -61,35 +56,3 @@ int riscv_get_ipi(int hart, int *pending) return 0; } - -static u64 sifive_clint_get_count(struct udevice *dev) -{ - return readq((void __iomem *)MTIME_REG(dev->priv)); -} - -static const struct timer_ops sifive_clint_ops = { - .get_count = sifive_clint_get_count, -}; - -static int sifive_clint_probe(struct udevice *dev) -{ - dev->priv = dev_read_addr_ptr(dev); - if (!dev->priv) - return -EINVAL; - - return timer_timebase_fallback(dev); -} - -static const struct udevice_id sifive_clint_ids[] = { - { .compatible = "riscv,clint0" }, - { } -}; - -U_BOOT_DRIVER(sifive_clint) = { - .name = "sifive_clint", - .id = UCLASS_TIMER, - .of_match = sifive_clint_ids, - .probe = sifive_clint_probe, - .ops = &sifive_clint_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index bb196961af..4b959401a6 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -471,8 +471,7 @@ cleanup_gate: cleanup_div: free(div); cleanup_mux: - if (mux) - free(mux); + free(mux); return comp; } diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index f8fa4aa71f..80743a2551 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -53,6 +53,13 @@ config ALTERA_TIMER Select this to enable a timer for Altera devices. Please find details on the "Embedded Peripherals IP User Guide" of Altera. +config ANDES_PLMT_TIMER + bool + depends on RISCV_MMODE || SPL_RISCV_MMODE + help + The Andes PLMT block holds memory-mapped mtime register + associated with timer tick. + config ARC_TIMER bool "ARC timer support" depends on TIMER && ARC && CLK diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 3a4d74b996..eb5c48cc6c 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -5,6 +5,7 @@ obj-y += timer-uclass.o obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o +obj-$(CONFIG_ANDES_PLMT_TIMER) += andes_plmt_timer.o obj-$(CONFIG_ARC_TIMER) += arc_timer.o obj-$(CONFIG_AST_TIMER) += ast_timer.o obj-$(CONFIG_ATCPIT100_TIMER) += atcpit100_timer.o @@ -18,6 +19,7 @@ obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_STI_TIMER) += sti-timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o diff --git a/arch/riscv/lib/andes_plmt.c b/drivers/timer/andes_plmt_timer.c similarity index 100% rename from arch/riscv/lib/andes_plmt.c rename to drivers/timer/andes_plmt_timer.c diff --git a/drivers/timer/sifive_clint_timer.c b/drivers/timer/sifive_clint_timer.c new file mode 100644 index 0000000000..00ce0f08d6 --- /dev/null +++ b/drivers/timer/sifive_clint_timer.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Sean Anderson + * Copyright (C) 2018, Bin Meng + */ + +#include +#include +#include +#include +#include +#include + +/* mtime register */ +#define MTIME_REG(base) ((ulong)(base) + 0xbff8) + +static u64 sifive_clint_get_count(struct udevice *dev) +{ + return readq((void __iomem *)MTIME_REG(dev->priv)); +} + +static const struct timer_ops sifive_clint_ops = { + .get_count = sifive_clint_get_count, +}; + +static int sifive_clint_probe(struct udevice *dev) +{ + dev->priv = dev_read_addr_ptr(dev); + if (!dev->priv) + return -EINVAL; + + return timer_timebase_fallback(dev); +} + +static const struct udevice_id sifive_clint_ids[] = { + { .compatible = "riscv,clint0" }, + { } +}; + +U_BOOT_DRIVER(sifive_clint) = { + .name = "sifive_clint", + .id = UCLASS_TIMER, + .of_match = sifive_clint_ids, + .probe = sifive_clint_probe, + .ops = &sifive_clint_ops, + .flags = DM_FLAG_PRE_RELOC, +};