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https://github.com/brain-hackers/u-boot-brain
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arm: Remove mx53smd board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Tom Rini
parent
1c4bd238b5
commit
53ad2db946
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@ -68,10 +68,6 @@ config TARGET_MX53PPD
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help
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Enable support for the GE Healthcare PPD.
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config TARGET_MX53SMD
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bool "Support mx53smd"
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select MX53
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config TARGET_TS4800
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bool "Support TS4800"
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select MX51
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@ -89,7 +85,6 @@ source "board/beckhoff/mx53cx9020/Kconfig"
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source "board/freescale/mx51evk/Kconfig"
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source "board/freescale/mx53evk/Kconfig"
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source "board/freescale/mx53loco/Kconfig"
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source "board/freescale/mx53smd/Kconfig"
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source "board/ge/mx53ppd/Kconfig"
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source "board/inversepath/usbarmory/Kconfig"
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source "board/k+p/kp_imx53/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_MX53SMD
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config SYS_BOARD
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default "mx53smd"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "mx5"
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config SYS_CONFIG_NAME
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default "mx53smd"
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endif
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@ -1,6 +0,0 @@
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MX53SMD BOARD
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M: Fabio Estevam <fabio.estevam@nxp.com>
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S: Maintained
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F: board/freescale/mx53smd/
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F: include/configs/mx53smd.h
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F: configs/mx53smd_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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obj-y := mx53smd.o
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@ -1,82 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Stefano Babic DENX Software Engineering sbabic@denx.de.
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*
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* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x53fa8554 0x00300000
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DATA 4 0x53fa8558 0x00300040
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DATA 4 0x53fa8560 0x00300000
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DATA 4 0x53fa8564 0x00300040
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DATA 4 0x53fa8568 0x00300040
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DATA 4 0x53fa8570 0x00300000
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DATA 4 0x53fa8574 0x00300000
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DATA 4 0x53fa8578 0x00300000
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DATA 4 0x53fa857c 0x00300040
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DATA 4 0x53fa8580 0x00300040
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DATA 4 0x53fa8584 0x00300000
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DATA 4 0x53fa8588 0x00300000
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DATA 4 0x53fa8590 0x00300040
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DATA 4 0x53fa8594 0x00300000
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DATA 4 0x53fa86f0 0x00300000
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DATA 4 0x53fa86f4 0x00000000
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DATA 4 0x53fa86fc 0x00000000
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DATA 4 0x53fa8714 0x00000000
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DATA 4 0x53fa8718 0x00300000
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DATA 4 0x53fa871c 0x00300000
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DATA 4 0x53fa8720 0x00300000
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DATA 4 0x53fa8724 0x04000000
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DATA 4 0x53fa8728 0x00300000
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DATA 4 0x53fa872c 0x00300000
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DATA 4 0x63fd9088 0x35343535
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DATA 4 0x63fd9090 0x4d444c44
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DATA 4 0x63fd907c 0x01370138
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DATA 4 0x63fd9080 0x013b013c
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DATA 4 0x63fd9018 0x00011740
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DATA 4 0x63fd9000 0xc3190000
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DATA 4 0x63fd900c 0x9f5152e3
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DATA 4 0x63fd9010 0xb68e8a63
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DATA 4 0x63fd9014 0x01ff00db
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DATA 4 0x63fd902c 0x000026d2
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DATA 4 0x63fd9030 0x009f0e21
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DATA 4 0x63fd9008 0x12273030
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DATA 4 0x63fd9004 0x0002002d
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DATA 4 0x63fd901c 0x00008032
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DATA 4 0x63fd901c 0x00008033
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DATA 4 0x63fd901c 0x00028031
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DATA 4 0x63fd901c 0x052080b0
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DATA 4 0x63fd901c 0x04008040
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DATA 4 0x63fd901c 0x0000803a
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DATA 4 0x63fd901c 0x0000803b
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DATA 4 0x63fd901c 0x00028039
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DATA 4 0x63fd901c 0x05208138
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DATA 4 0x63fd901c 0x04008048
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DATA 4 0x63fd9020 0x00005800
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DATA 4 0x63fd9040 0x05380003
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DATA 4 0x63fd9058 0x00022227
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DATA 4 0x63fd901C 0x00000000
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@ -1,159 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <linux/errno.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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return 0;
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}
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
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NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
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PAD_CTL_HYS | PAD_CTL_PKE),
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NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
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PAD_CTL_HYS | PAD_CTL_PKE),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg esdhc_cfg[1] = {
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{MMC_SDHC1_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
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gpio_direction_input(IMX_GPIO_NR(3, 13));
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return !gpio_get_value(IMX_GPIO_NR(3, 13));
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}
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_DSE_HIGH)
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int board_mmc_init(struct bd_info *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
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MX53_PAD_EIM_DA13__GPIO3_13,
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(1)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: MX53SMD\n");
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return 0;
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}
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@ -1,25 +0,0 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX5=y
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CONFIG_SYS_TEXT_BASE=0x77800000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x60000
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CONFIG_TARGET_MX53SMD=y
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# CONFIG_CMD_BMODE is not set
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53smd/imximage.cfg"
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_FAT=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_FSL_ESDHC_IMX=y
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CONFIG_MTD=y
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CONFIG_MII=y
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CONFIG_MXC_UART=y
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CONFIG_OF_LIBFDT=y
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@ -1,111 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the MX53SMD Freescale board.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD
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#include <asm/arch/imx-regs.h>
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_REVISION_TAG
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#define CONFIG_SYS_FSL_CLK
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
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#define CONFIG_MXC_UART_BASE UART1_BASE
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_ESDHC_NUM 1
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/* Eth Configs */
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#define CONFIG_HAS_ETH1
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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/* Command definition */
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#define CONFIG_ETHPRIME "FEC0"
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#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"script=boot.scr\0" \
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"uimage=uImage\0" \
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"mmcdev=0\0" \
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"mmcpart=2\0" \
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"mmcroot=/dev/mmcblk0p3 rw\0" \
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"mmcrootfstype=ext3 rootwait\0" \
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"mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=${mmcroot} " \
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"rootfstype=${mmcrootfstype}\0" \
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"loadbootscript=" \
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"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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"bootscript=echo Running bootscript from mmc ...; " \
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"source\0" \
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"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
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"mmcboot=echo Booting from mmc ...; " \
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"run mmcargs; " \
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"bootm\0" \
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"netargs=setenv bootargs console=ttymxc0,${baudrate} " \
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"root=/dev/nfs " \
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"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
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"netboot=echo Booting from net ...; " \
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"run netargs; " \
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"dhcp ${uimage}; bootm\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc dev ${mmcdev}; if mmc rescan; then " \
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"if run loadbootscript; then " \
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"run bootscript; " \
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"else " \
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"if run loaduimage; then " \
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"run mmcboot; " \
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"else run netboot; " \
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"fi; " \
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"fi; " \
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"else run netboot; fi"
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#define CONFIG_ARP_TIMEOUT 200UL
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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/* Physical Memory Map */
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#define PHYS_SDRAM_1 CSD0_BASE_ADDR
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#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
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#define PHYS_SDRAM_2 CSD1_BASE_ADDR
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#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
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#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
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|
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#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* environment organization */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user