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arm: Remove mx53ard board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
This commit is contained in:
Tom Rini
parent
2610bf14b5
commit
1c4bd238b5
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@ -44,10 +44,6 @@ config TARGET_MX51EVK
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select BOARD_LATE_INIT
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select MX51
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config TARGET_MX53ARD
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bool "Support mx53ard"
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select MX53
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config TARGET_MX53CX9020
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bool "Support CX9020"
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select BOARD_LATE_INIT
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@ -91,7 +87,6 @@ config SYS_SOC
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source "board/beckhoff/mx53cx9020/Kconfig"
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source "board/freescale/mx51evk/Kconfig"
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source "board/freescale/mx53ard/Kconfig"
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source "board/freescale/mx53evk/Kconfig"
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source "board/freescale/mx53loco/Kconfig"
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source "board/freescale/mx53smd/Kconfig"
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@ -1,15 +0,0 @@
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if TARGET_MX53ARD
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config SYS_BOARD
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default "mx53ard"
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config SYS_VENDOR
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default "freescale"
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config SYS_SOC
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default "mx5"
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config SYS_CONFIG_NAME
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default "mx53ard"
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endif
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@ -1,6 +0,0 @@
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MX53ARD BOARD
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M: Fabio Estevam <fabio.estevam@nxp.com>
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S: Maintained
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F: board/freescale/mx53ard/
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F: include/configs/mx53ard.h
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F: configs/mx53ard_defconfig
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@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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#
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# (C) Copyright 2011 Freescale Semiconductor, Inc.
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obj-y := mx53ard.o
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@ -1,82 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2009
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* Stefano Babic DENX Software Engineering sbabic@denx.de.
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*
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* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi, sd (the board has no nand neither onenand)
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*/
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BOOT_FROM sd
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x53fa8554 0x00300000
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DATA 4 0x53fa8558 0x00300040
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DATA 4 0x53fa8560 0x00300000
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DATA 4 0x53fa8564 0x00300040
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DATA 4 0x53fa8568 0x00300040
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DATA 4 0x53fa8570 0x00300000
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DATA 4 0x53fa8574 0x00300000
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DATA 4 0x53fa8578 0x00300000
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DATA 4 0x53fa857c 0x00300040
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DATA 4 0x53fa8580 0x00300040
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DATA 4 0x53fa8584 0x00300000
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DATA 4 0x53fa8588 0x00300000
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DATA 4 0x53fa8590 0x00300040
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DATA 4 0x53fa8594 0x00300000
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DATA 4 0x53fa86f0 0x00300000
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DATA 4 0x53fa86f4 0x00000000
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DATA 4 0x53fa86fc 0x00000000
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DATA 4 0x53fa8714 0x00000000
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DATA 4 0x53fa8718 0x00300000
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DATA 4 0x53fa871c 0x00300000
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DATA 4 0x53fa8720 0x00300000
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DATA 4 0x53fa8724 0x04000000
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DATA 4 0x53fa8728 0x00300000
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DATA 4 0x53fa872c 0x00300000
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DATA 4 0x63fd9088 0x35343535
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DATA 4 0x63fd9090 0x4d444c44
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DATA 4 0x63fd907c 0x01370138
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DATA 4 0x63fd9080 0x013b013c
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DATA 4 0x63fd9018 0x00011740
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DATA 4 0x63fd9000 0xc3190000
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DATA 4 0x63fd900c 0x9f5152e3
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DATA 4 0x63fd9010 0xb68e8a63
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DATA 4 0x63fd9014 0x01ff00db
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DATA 4 0x63fd902c 0x000026d2
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DATA 4 0x63fd9030 0x009f0e21
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DATA 4 0x63fd9008 0x12273030
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DATA 4 0x63fd9004 0x0002002d
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DATA 4 0x63fd901c 0x00008032
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DATA 4 0x63fd901c 0x00008033
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DATA 4 0x63fd901c 0x00028031
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DATA 4 0x63fd901c 0x052080b0
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DATA 4 0x63fd901c 0x04008040
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DATA 4 0x63fd901c 0x0000803a
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DATA 4 0x63fd901c 0x0000803b
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DATA 4 0x63fd901c 0x00028039
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DATA 4 0x63fd901c 0x05208138
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DATA 4 0x63fd901c 0x04008048
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DATA 4 0x63fd9020 0x00005800
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DATA 4 0x63fd9040 0x05380003
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DATA 4 0x63fd9058 0x00022227
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DATA 4 0x63fd901C 0x00000000
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@ -1,319 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <linux/errno.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <fsl_esdhc_imx.h>
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#include <asm/gpio.h>
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#define ETHERNET_INT IMX_GPIO_NR(2, 31)
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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return 0;
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}
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#ifdef CONFIG_NAND_MXC
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static void setup_iomux_nand(void)
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{
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static const iomux_v3_cfg_t nand_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
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PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
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PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
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PAD_CTL_PUS_100K_UP),
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NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
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PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
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PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
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PAD_CTL_PUS_100K_UP),
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NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
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PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
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PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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};
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u32 i, reg;
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reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
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reg &= ~M4IF_GENP_WEIM_MM_MASK;
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__raw_writel(reg, M4IF_BASE_ADDR + 0xc);
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for (i = 0x4; i < 0x94; i += 0x18) {
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reg = __raw_readl(WEIM_BASE_ADDR + i);
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reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
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__raw_writel(reg, WEIM_BASE_ADDR + i);
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}
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imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
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}
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#else
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static void setup_iomux_nand(void)
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{
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}
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#endif
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#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
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static void setup_iomux_uart(void)
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{
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static const iomux_v3_cfg_t uart_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
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};
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
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gpio_direction_input(IMX_GPIO_NR(1, 1));
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imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
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gpio_direction_input(IMX_GPIO_NR(1, 4));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
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return ret;
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}
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#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
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PAD_CTL_PUS_100K_UP)
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#define SD_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
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#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
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PAD_CTL_DSE_HIGH)
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int board_mmc_init(struct bd_info *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
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};
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static const iomux_v3_cfg_t sd2_pads[] = {
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NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
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NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(sd2_pads,
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ARRAY_SIZE(sd2_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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static void weim_smc911x_iomux(void)
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{
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static const iomux_v3_cfg_t weim_smc911x_pads[] = {
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/* Data bus */
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NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
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PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
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NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
|
||||
/* Address lines */
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
|
||||
PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
|
||||
|
||||
/* other EIM signals for ethernet */
|
||||
MX53_PAD_EIM_OE__EMI_WEIM_OE,
|
||||
MX53_PAD_EIM_RW__EMI_WEIM_RW,
|
||||
MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
|
||||
};
|
||||
|
||||
/* ETHERNET_INT as GPIO2_31 */
|
||||
imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
|
||||
gpio_direction_input(ETHERNET_INT);
|
||||
|
||||
/* WEIM bus */
|
||||
imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
|
||||
ARRAY_SIZE(weim_smc911x_pads));
|
||||
}
|
||||
|
||||
static void weim_cs1_settings(void)
|
||||
{
|
||||
struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
|
||||
|
||||
writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
|
||||
writel(0x0, &weim_regs->cs1gcr2);
|
||||
writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
|
||||
writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
|
||||
writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
|
||||
writel(0x0, &weim_regs->cs1wcr2);
|
||||
writel(0x0, &weim_regs->wcr);
|
||||
|
||||
set_chipselect_size(CS0_64M_CS1_64M);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_nand();
|
||||
setup_iomux_uart();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
|
||||
weim_smc911x_iomux();
|
||||
weim_cs1_settings();
|
||||
|
||||
#ifdef CONFIG_SMC911X
|
||||
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
||||
#endif
|
||||
return rc;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: MX53ARD\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX5=y
|
||||
CONFIG_SYS_TEXT_BASE=0x77800000
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x60000
|
||||
CONFIG_TARGET_MX53ARD=y
|
||||
# CONFIG_CMD_BMODE is not set
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg"
|
||||
CONFIG_DEFAULT_FDT_FILE="imx53-ard.dtb"
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_ESDHC_IMX=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SYS_NAND_USE_FLASH_BBT=y
|
||||
CONFIG_NAND_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SMC911X=y
|
||||
CONFIG_SMC911X_BASE=0xF4000000
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,170 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Configuration settings for the MX53ARD Freescale board.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD
|
||||
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_REVISION_TAG
|
||||
|
||||
#define CONFIG_SYS_FSL_CLK
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI
|
||||
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI
|
||||
#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR
|
||||
#define CONFIG_SYS_NAND_LARGEPAGE
|
||||
#define CONFIG_MXC_NAND_HWECC
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_ESDHC_NUM 2
|
||||
|
||||
/* Eth Configs */
|
||||
#define CONFIG_HAS_ETH1
|
||||
|
||||
/* Command definition */
|
||||
|
||||
#define CONFIG_ETHPRIME "smc911x"
|
||||
|
||||
#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
|
||||
"fdt_addr=0x78000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
|
||||
"mmcpart=1\0" \
|
||||
"mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
|
||||
"update_sd_firmware_filename=u-boot.imx\0" \
|
||||
"update_sd_firmware=" \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"if mmc dev ${mmcdev}; then " \
|
||||
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
|
||||
"setexpr fw_sz ${filesize} / 0x200; " \
|
||||
"setexpr fw_sz ${fw_sz} + 1; " \
|
||||
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
|
||||
"fi; " \
|
||||
"fi\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${uimage}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loaduimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi"
|
||||
|
||||
#define CONFIG_ARP_TIMEOUT 200UL
|
||||
|
||||
/* Miscellaneous configurable options */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM_1 CSD0_BASE_ADDR
|
||||
#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024)
|
||||
#define PHYS_SDRAM_2 CSD1_BASE_ADDR
|
||||
#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024)
|
||||
#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* environment organization */
|
||||
|
||||
#define MX53ARD_CS1GCR1 (CSEN | DSZ(2))
|
||||
#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22))
|
||||
#define MX53ARD_CS1RCR2 RBEN(2)
|
||||
#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22))
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user