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Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi

Browse Source 
- Enable DM_SPI on siemens omap boards (Jagan)
- Dropped some non-dm supported omap3 boards (Jagan)
- Dropped non-dm code in omap3 spi driver (Jagan)
- Dropped non-dm code in kirkwood spi driver (Bhargav)
This commit is contained in:
Tom Rini 2020-07-11 17:40:00 -04:00
commit 497c7598c4
101 changed files with 107 additions and 7887 deletions
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3
arch/arm/Kconfig
View File

@ -1921,12 +1921,10 @@ source "board/freescale/lx2160a/Kconfig"
source "board/freescale/mx35pdk/Kconfig"
source "board/freescale/s32v234evb/Kconfig"
source "board/grinn/chiliboard/Kconfig"
source "board/gumstix/pepper/Kconfig"
source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/silica/pengwyn/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"
@ -1934,7 +1932,6 @@ source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"

1
arch/arm/mach-imx/mx3/Kconfig
View File

@ -29,6 +29,5 @@ config MX31_CLK32
Frequency in Hz of the low frequency input clock. Typically
32768 or 32000 Hz.
source "board/freescale/mx31pdk/Kconfig"
endif

29
arch/arm/mach-omap2/am33xx/Kconfig
View File

@ -103,21 +103,6 @@ config TARGET_AM335X_SL50
select DM_SERIAL
imply CMD_DM
config TARGET_BAV335X
bool "Support bav335x"
select BOARD_LATE_INIT
select DM
select DM_SERIAL
imply CMD_DM
help
The BAV335x OEM Network Processor integrates all the functions of an
embedded network computer in a small, easy to use SODIMM module which
incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
processor, with fast DDR3 512MB SDRAM, 4GB of embedded MMC and a Gigabit
ethernet with simple connection to external connectors.
For more information, visit: http://birdland.com/oem
config TARGET_BRXRE1
bool "Support BRXRE1"
select BOARD_LATE_INIT
@ -168,20 +153,6 @@ config TARGET_PCM051
select DM_SERIAL
imply CMD_DM
config TARGET_PENGWYN
bool "Support pengwyn"
select DM
select DM_GPIO
select DM_SERIAL
imply CMD_DM
config TARGET_PEPPER
bool "Support pepper"
select DM
select DM_GPIO
select DM_SERIAL
imply CMD_DM
config TARGET_PHYCORE_AM335X_R2
bool "Support phyCORE AM335X R2"
select DM

18
arch/arm/mach-omap2/omap3/Kconfig
View File

@ -86,13 +86,6 @@ config TARGET_OMAP3_OVERO
select OMAP3_GPIO_6
imply CMD_DM
config TARGET_OMAP3_ZOOM1
bool "TI Zoom1"
select DM
select DM_GPIO
select DM_SERIAL
imply CMD_DM
config TARGET_AM3517_CRANE
bool "am3517_crane"
@ -127,13 +120,6 @@ config TARGET_TAO3530
select OMAP3_GPIO_5
select OMAP3_GPIO_6
config TARGET_OMAP3_CAIRO
bool "QUIPOS CAIRO"
select DM
select DM_GPIO
select DM_SERIAL
imply CMD_DM
config TARGET_SNIPER
bool "LG Optimus Black"
select DM
@ -174,18 +160,14 @@ config SYS_SOC
source "board/logicpd/am3517evm/Kconfig"
source "board/ti/beagle/Kconfig"
source "board/compulab/cm_t35/Kconfig"
source "board/timll/devkit8000/Kconfig"
source "board/ti/evm/Kconfig"
source "board/isee/igep00x0/Kconfig"
source "board/overo/Kconfig"
source "board/logicpd/zoom1/Kconfig"
source "board/ti/am3517crane/Kconfig"
source "board/corscience/tricorder/Kconfig"
source "board/logicpd/omap3som/Kconfig"
source "board/nokia/rx51/Kconfig"
source "board/technexion/tao3530/Kconfig"
source "board/quipos/cairo/Kconfig"
source "board/lg/sniper/Kconfig"
endif

4
arch/arm/mach-omap2/omap4/Kconfig
View File

@ -4,9 +4,6 @@ choice
prompt "OMAP4 board select"
optional
config TARGET_DUOVERO
bool "OMAP4430 Gumstix Duovero"
config TARGET_OMAP4_PANDA
bool "TI OMAP4 PandaBoard"
@ -21,7 +18,6 @@ endchoice
config SYS_SOC
default "omap4"
source "board/gumstix/duovero/Kconfig"
source "board/ti/panda/Kconfig"
source "board/ti/sdp4430/Kconfig"
source "board/amazon/kc1/Kconfig"

1
arch/arm/mach-omap2/omap5/Kconfig
View File

@ -156,7 +156,6 @@ endchoice
endmenu
endif
source "board/compulab/cm_t54/Kconfig"
source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
source "board/ti/am57xx/Kconfig"

23
board/birdland/bav335x/Kconfig
View File

@ -1,23 +0,0 @@
if TARGET_BAV335X
config SYS_BOARD
default "bav335x"
config SYS_VENDOR
default "birdland"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "bav335x"
config BAV_VERSION
int "BAV335x Version (1=A, 2=B)"
range 1 2
help
The BAV335x has various version of the board. Rev.A (mostly obsolete)
used 10/100 Ethernet PHY while Rev.B uses a Gigabit Ethernet PHY.
Overwrite this if you have an older Rev.A and want ethernet support.
endif

11
board/birdland/bav335x/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Makefile
#
# Copyright (C) 2012-2014, Birdland Audio - http://birdland.com/oem
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
obj-y += board.o

31
board/birdland/bav335x/README
View File

@ -1,31 +0,0 @@
Summary
=======
This document covers various features of the 'BAV335x' board build.
For more information about this board, visit http://birdland.com/oem
Hardware
========
The binary produced supports the bav335x Rev.A with 10/100 MB PHY
and Rev.B (default) with GB ethernet PHY.
If the BAV335x EEPROM is populated and programmed, the board will
automatically detect the version and extract proper serial# and
mac address from the EE.
Customization
=============
The following blocks are required:
- I2C, to talk with the PMIC and ensure that we do not run afoul of
errata 1.0.24.
When removing options as part of customization,
CONFIG_EXTRA_ENV_SETTINGS will need additional care to update for your
needs and to remove no longer relevant options as in some cases we
define additional text blocks (such as for NAND or DFU strings). Also
note that all of the SPL options are grouped together, rather than with
the IP blocks, so both areas will need their choices updated to reflect
the custom design.

432
board/birdland/bav335x/board.c
View File

@ -1,432 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Board functions for Birdland Audio BAV335x Network Processor
*
* Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
*/
#include <common.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <net.h>
#include <serial.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <power/tps65910.h>
#include <env_internal.h>
#include <watchdog.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
/* GPIO that controls power to DDR on EVM-SK */
#define GPIO_DDR_VTT_EN 7
static __maybe_unused struct ctrl_dev *cdev =
(struct ctrl_dev *)CTRL_DEVICE_BASE;
/*
* Read header information from EEPROM into global structure.
*/
static int read_eeprom(struct board_eeconfig *header)
{
/* Check if baseboard eeprom is available */
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
return -ENODEV;
/* read the eeprom using i2c */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
sizeof(struct board_eeconfig)))
return -EIO;
if (header->magic != BOARD_MAGIC) {
/* read the i2c eeprom again using only a 1 byte address */
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
sizeof(struct board_eeconfig)))
return -EIO;
if (header->magic != BOARD_MAGIC)
return -EINVAL;
}
return 0;
}
enum board_type get_board_type(bool debug)
{
int ecode;
struct board_eeconfig header;
ecode = read_eeprom(&header);
if (ecode == 0) {
if (header.version[1] == 'A') {
if (debug)
puts("=== Detected Board model BAV335x Rev.A");
return BAV335A;
} else if (header.version[1] == 'B') {
if (debug)
puts("=== Detected Board model BAV335x Rev.B");
return BAV335B;
} else if (debug) {
puts("### Un-known board model in serial-EE\n");
}
} else if (debug) {
switch (ecode) {
case -ENODEV:
puts("### Board doesn't have a serial-EE\n");
break;
case -EINVAL:
puts("### Board serial-EE signature is incorrect.\n");
break;
default:
puts("### IO Error reading serial-EE.\n");
break;
}
}
#if (CONFIG_BAV_VERSION == 1)
if (debug)
puts("### Selecting BAV335A as per config\n");
return BAV335A;
#elif (CONFIG_BAV_VERSION == 2)
if (debug)
puts("### Selecting BAV335B as per config\n");
return BAV335B;
#endif
#if (NOT_DEFINED == 2)
#error "SHOULD NEVER DISPLAY THIS"
#endif
if (debug)
puts("### Defaulting to model BAV335x Rev.B\n");
return BAV335B;
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr3_bav335x_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_bav335x_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
#ifdef CONFIG_SPL_ENV_SUPPORT
env_init();
env_load();
if (env_get_yesno("boot_os") != 1)
return 1;
#endif
return 0;
}
#endif
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr = {
266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_evm_sk = {
303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_bone_black = {
400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
/* debug print detect status */
(void)get_board_type(true);
/* Get the frequency */
/* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
dpll_mpu_opp100.m = MPUPLL_M_1000;
if (i2c_probe(TPS65217_CHIP_PM))
return;
/* Set the USB Current Limit */
if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
TPS65217_USB_INPUT_CUR_LIMIT_MASK))
puts("! tps65217_reg_write: could not set USB limit\n");
/* Set the Core Voltage (DCDC3) to 1.125V */
if (tps65217_voltage_update(TPS65217_DEFDCDC3,
TPS65217_DCDC_VOLT_SEL_1125MV)) {
puts("! tps65217_reg_write: could not set Core Voltage\n");
return;
}
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Set the MPU Voltage (DCDC2) */
if (tps65217_voltage_update(TPS65217_DEFDCDC2,
TPS65217_DCDC_VOLT_SEL_1325MV)) {
puts("! tps65217_reg_write: could not set MPU Voltage\n");
return;
}
/*
* Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
* Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
*/
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
puts("! tps65217_reg_write: could not set LDO3\n");
if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
puts("! tps65217_reg_write: could not set LDO4\n");
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
enable_i2c0_pin_mux();
i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
return &dpll_ddr_bone_black;
}
void set_uart_mux_conf(void)
{
#if CONFIG_CONS_INDEX == 1
enable_uart0_pin_mux();
#elif CONFIG_CONS_INDEX == 2
enable_uart1_pin_mux();
#elif CONFIG_CONS_INDEX == 3
enable_uart2_pin_mux();
#elif CONFIG_CONS_INDEX == 4
enable_uart3_pin_mux();
#elif CONFIG_CONS_INDEX == 5
enable_uart4_pin_mux();
#elif CONFIG_CONS_INDEX == 6
enable_uart5_pin_mux();
#endif
}
void set_mux_conf_regs(void)
{
enum board_type board;
board = get_board_type(false);
enable_board_pin_mux(board);
}
const struct ctrl_ioregs ioregs_bonelt = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
void sdram_init(void)
{
config_ddr(400, &ioregs_bonelt,
&ddr3_bav335x_data,
&ddr3_bav335x_cmd_ctrl_data,
&ddr3_bav335x_emif_reg_data, 0);
}
#endif
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
gpmc_init();
#endif
return 0;
}
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
env_set("board_name", "BAV335xB");
env_set("board_rev", "B"); /* Fix me, but why bother.. */
#endif
return 0;
}
#endif
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif
/*
* This function will:
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
!defined(CONFIG_SPL_BUILD))
int board_eth_init(bd_t *bis)
{
int ecode, rv, n;
uint8_t mac_addr[6];
struct board_eeconfig header;
__maybe_unused enum board_type board;
/* Default manufacturing address; used when no EE or invalid */
n = 0;
mac_addr[0] = 0;
mac_addr[1] = 0x20;
mac_addr[2] = 0x18;
mac_addr[3] = 0x1C;
mac_addr[4] = 0x00;
mac_addr[5] = 0x01;
ecode = read_eeprom(&header);
/* if we have a valid EE, get mac address from there */
if ((ecode == 0) &&
is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
}
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
if (!env_get("ethaddr")) {
printf("<ethaddr> not set. Validating first E-fuse MAC\n");
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
#ifdef CONFIG_DRIVER_TI_CPSW
board = get_board_type(false);
/* Rev.A uses 10/100 PHY in mii mode */
if (board == BAV335A) {
writel(MII_MODE_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
}
/* Rev.B (default) uses GB PHY in rmii mode */
else {
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
= PHY_INTERFACE_MODE_RGMII;
}
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
#endif
return n;
}
#endif

58
board/birdland/bav335x/board.h
View File

@ -1,58 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* board.c
*
* Board functions for Birdland Audio BAV335x Network Processor
*
* Copyright (c) 2012-2014, Birdland Audio - http://birdland.com/oem
*
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/* Serial MagicE: AA 55 BA BE */
#define BOARD_MAGIC 0xBEBA55AA
enum board_type {UNKNOWN, BAV335A, BAV335B};
/*
* The BAV335x may use a built-in read-only serial EEProm.
* The Evaluation board, disables the write-protect so the Serial-EE
* Can be programmed during manufacturing to store fields such as
* a board serial number, ethernet mac address and other user fields.
* Additionally, the Serial-EE can store the specific version of the
* board it runs on, and overwrite the defaults in _defconfig
*/
#define HDR_NO_OF_MAC_ADDR 3
#define HDR_ETH_ALEN 6
#define HDR_NAME_LEN 8
struct board_eeconfig {
unsigned int magic;
char name[HDR_NAME_LEN]; /* BAV3354 */
char version[4]; /* 0B20 - Rev.B2 */
char serial[16];
char config[32];
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
};
enum board_type get_board_type(bool verbose_debug_output);
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_uart1_pin_mux(void);
void enable_uart2_pin_mux(void);
void enable_uart3_pin_mux(void);
void enable_uart4_pin_mux(void);
void enable_uart5_pin_mux(void);
void enable_i2c0_pin_mux(void);
void enable_board_pin_mux(enum board_type board);
#endif

190
board/birdland/bav335x/mux.c
View File

@ -1,190 +0,0 @@
/*
* mux.c
*
* Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux uart1_pin_mux[] = {
{OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
{-1},
};
static struct module_pin_mux uart2_pin_mux[] = {
{OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
{OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
{-1},
};
static struct module_pin_mux uart3_pin_mux[] = {
{OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
{OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
{-1},
};
static struct module_pin_mux uart4_pin_mux[] = {
{OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
{OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
{-1},
};
static struct module_pin_mux uart5_pin_mux[] = {
{OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
{OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux mmc1_pin_mux[] = {
{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux i2c1_pin_mux[] = {
{OFFSET(spi0_d1), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
{OFFSET(spi0_cs0), (MODE(2) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
{-1},
};
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_uart1_pin_mux(void)
{
configure_module_pin_mux(uart1_pin_mux);
}
void enable_uart2_pin_mux(void)
{
configure_module_pin_mux(uart2_pin_mux);
}
void enable_uart3_pin_mux(void)
{
configure_module_pin_mux(uart3_pin_mux);
}
void enable_uart4_pin_mux(void)
{
configure_module_pin_mux(uart4_pin_mux);
}
void enable_uart5_pin_mux(void)
{
configure_module_pin_mux(uart5_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
/* CPLD registers */
#define I2C_CPLD_ADDR 0x35
#define CFG_REG 0x10
void enable_board_pin_mux(enum board_type board)
{
configure_module_pin_mux(i2c1_pin_mux);
if (board == BAV335A)
configure_module_pin_mux(mii1_pin_mux); /* MII Mode: 10/100MB */
else
configure_module_pin_mux(rgmii1_pin_mux); /* RGMII Mode: GB */
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(mmc1_pin_mux);
}

115
board/birdland/bav335x/u-boot.lds
View File

@ -1,115 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
board/birdland/bav335x/built-in.o (.text*)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data*)
}
. = ALIGN(4);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.image_copy_end :
{
*(.__image_copy_end)
}
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rel.dyn : {
*(.rel*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
}
.hash : { *(.hash*) }
.end :
{
*(.__end)
}
_image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_limit = .;
}
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
.dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.gnu.hash : { *(.gnu.hash) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

12
board/compulab/cm_t35/Kconfig
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@ -1,12 +0,0 @@
if TARGET_CM_T35
config SYS_BOARD
default "cm_t35"
config SYS_VENDOR
default "compulab"
config SYS_CONFIG_NAME
default "cm_t35"
endif

6
board/compulab/cm_t35/MAINTAINERS
View File

@ -1,6 +0,0 @@
CM_T35 BOARD
M: Igor Grinberg <grinberg@compulab.co.il>
S: Maintained
F: board/compulab/cm_t35/
F: include/configs/cm_t35.h
F: configs/cm_t35_defconfig

8
board/compulab/cm_t35/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
#
# Authors: Nikita Kiryanov <nikita@compulab.co.il>
# Igor Grinberg <grinberg@compulab.co.il>
obj-y += cm_t35.o

513
board/compulab/cm_t35/cm_t35.c
View File

@ -1,513 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il>
*
* Authors: Mike Rapoport <mike@compulab.co.il>
* Igor Grinberg <grinberg@compulab.co.il>
*
* Derived from omap3evm and Beagle Board by
* Manikandan Pillai <mani.pillai@ti.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <status_led.h>
#include <netdev.h>
#include <net.h>
#include <i2c.h>
#include <usb.h>
#include <mmc.h>
#include <splash.h>
#include <twl4030.h>
#include <linux/compiler.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include <asm/ehci-omap.h>
#include <asm/gpio.h>
#include "../common/common.h"
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"CM-T3x board",
"NAND",
};
#ifdef CONFIG_SPL_BUILD
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mr = MICRON_V_MR_165;
timings->mcfg = MICRON_V_MCFG_200(256 << 20); /* raswidth 14 needed */
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
#endif
struct splash_location splash_locations[] = {
{
.name = "nand",
.storage = SPLASH_STORAGE_NAND,
.flags = SPLASH_STORAGE_RAW,
.offset = 0x100000,
},
};
int splash_screen_prepare(void)
{
return splash_source_load(splash_locations,
ARRAY_SIZE(splash_locations));
}
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
if (get_cpu_family() == CPU_OMAP34XX)
gd->bd->bi_arch_number = MACH_TYPE_CM_T35;
else
gd->bd->bi_arch_number = MACH_TYPE_CM_T3730;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
#endif
return 0;
}
/*
* Routine: get_board_rev
* Description: read system revision
*/
u32 get_board_rev(void)
{
return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
};
int misc_init_r(void)
{
cl_print_pcb_info();
omap_die_id_display();
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
static void cm_t3x_set_common_muxconf(void)
{
/* SDRC */
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)); /*SDRC_D0*/
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)); /*SDRC_D1*/
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)); /*SDRC_D2*/
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)); /*SDRC_D3*/
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)); /*SDRC_D4*/
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)); /*SDRC_D5*/
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)); /*SDRC_D6*/
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)); /*SDRC_D7*/
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)); /*SDRC_D8*/
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)); /*SDRC_D9*/
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)); /*SDRC_D10*/
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)); /*SDRC_D11*/
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)); /*SDRC_D12*/
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)); /*SDRC_D13*/
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)); /*SDRC_D14*/
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)); /*SDRC_D15*/
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)); /*SDRC_D16*/
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)); /*SDRC_D17*/
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)); /*SDRC_D18*/
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)); /*SDRC_D19*/
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)); /*SDRC_D20*/
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)); /*SDRC_D21*/
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)); /*SDRC_D22*/
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)); /*SDRC_D23*/
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)); /*SDRC_D24*/
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)); /*SDRC_D25*/
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)); /*SDRC_D26*/
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)); /*SDRC_D27*/
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)); /*SDRC_D28*/
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)); /*SDRC_D29*/
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)); /*SDRC_D30*/
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)); /*SDRC_D31*/
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)); /*SDRC_CLK*/
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)); /*SDRC_DQS0*/
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)); /*SDRC_DQS1*/
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)); /*SDRC_DQS2*/
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)); /*SDRC_DQS3*/
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)); /*SDRC_CKE1*/
/* GPMC */
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)); /*GPMC_A10*/
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)); /*GPMC_D0*/
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)); /*GPMC_D1*/
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)); /*GPMC_D2*/
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)); /*GPMC_D3*/
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)); /*GPMC_D4*/
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)); /*GPMC_D5*/
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)); /*GPMC_D6*/
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)); /*GPMC_D7*/
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)); /*GPMC_D8*/
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)); /*GPMC_D9*/
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)); /*GPMC_D10*/
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)); /*GPMC_D11*/
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)); /*GPMC_D12*/
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)); /*GPMC_D13*/
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)); /*GPMC_D14*/
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)); /*GPMC_D15*/
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)); /*GPMC_nCS0*/
/* SB-T35 Ethernet */
MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0)); /*GPMC_nCS4*/
/* DVI enable */
MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPMC_nCS3*/
/* DataImage backlight */
MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
/* CM-T3x Ethernet */
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | DIS | M0)); /*GPMC_nCS5*/
MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)); /*GPIO_59*/
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)); /*nADV_ALE*/
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)); /*nOE*/
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)); /*nWE*/
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)); /*nBE0_CLE*/
MUX_VAL(CP(GPMC_NBE1), (IDIS | PTD | DIS | M4)); /*GPIO_61*/
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)); /*nWP*/
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)); /*WAIT0*/
/* DSS */
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)); /*DSS_PCLK*/
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)); /*DSS_HSYNC*/
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)); /*DSS_VSYNC*/
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)); /*DSS_ACBIAS*/
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)); /*DSS_DATA6*/
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)); /*DSS_DATA7*/
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)); /*DSS_DATA8*/
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)); /*DSS_DATA9*/
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)); /*DSS_DATA10*/
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)); /*DSS_DATA11*/
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)); /*DSS_DATA12*/
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)); /*DSS_DATA13*/
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)); /*DSS_DATA14*/
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)); /*DSS_DATA15*/
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)); /*DSS_DATA16*/
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)); /*DSS_DATA17*/
/* serial interface */
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)); /*UART3_RX*/
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)); /*UART3_TX*/
/* mUSB */
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)); /*HSUSB0_CLK*/
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)); /*HSUSB0_STP*/
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)); /*HSUSB0_DIR*/
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)); /*HSUSB0_NXT*/
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA0*/
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA1*/
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA2*/
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA3*/
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA4*/
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA5*/
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA6*/
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)); /*HSUSB0_DATA7*/
/* USB EHCI */
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
/* SB_T35_USB_HUB_RESET_GPIO */
MUX_VAL(CP(CAM_WEN), (IDIS | PTD | DIS | M4)); /*GPIO_167*/
/* I2C1 */
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)); /*I2C1_SCL*/
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)); /*I2C1_SDA*/
/* I2C2 */
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)); /*I2C2_SCL*/
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)); /*I2C2_SDA*/
/* I2C3 */
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)); /*I2C3_SCL*/
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)); /*I2C3_SDA*/
/* control and debug */
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)); /*SYS_32K*/
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)); /*SYS_CLKREQ*/
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)); /*SYS_nIRQ*/
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)); /*OFF_MODE*/
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0)); /*CLKOUT1*/
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*green LED*/
MUX_VAL(CP(JTAG_NTRST), (IEN | PTD | DIS | M0)); /*JTAG_NTRST*/
MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)); /*JTAG_TCK*/
MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)); /*JTAG_TMS*/
MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)); /*JTAG_TDI*/
/* MMC1 */
MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)); /*MMC1_CLK*/
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)); /*MMC1_CMD*/
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)); /*MMC1_DAT0*/
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)); /*MMC1_DAT1*/
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)); /*MMC1_DAT2*/
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)); /*MMC1_DAT3*/
/* SPI */
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
/* display controls */
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
}
static void cm_t35_set_muxconf(void)
{
/* DSS */
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)); /*DSS_DATA0*/
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)); /*DSS_DATA1*/
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)); /*DSS_DATA2*/
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)); /*DSS_DATA3*/
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)); /*DSS_DATA4*/
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)); /*DSS_DATA5*/
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)); /*DSS_DATA18*/
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)); /*DSS_DATA19*/
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)); /*DSS_DATA20*/
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)); /*DSS_DATA21*/
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)); /*DSS_DATA22*/
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)); /*DSS_DATA23*/
/* MMC1 */
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)); /*MMC1_DAT4*/
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)); /*MMC1_DAT5*/
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)); /*MMC1_DAT6*/
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)); /*MMC1_DAT7*/
}
static void cm_t3730_set_muxconf(void)
{
/* DSS */
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M3)); /*DSS_DATA0*/
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M3)); /*DSS_DATA1*/
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M3)); /*DSS_DATA2*/
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M3)); /*DSS_DATA3*/
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M3)); /*DSS_DATA4*/
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M3)); /*DSS_DATA5*/
MUX_VAL(CP(SYS_BOOT0), (IDIS | PTD | DIS | M3)); /*DSS_DATA18*/
MUX_VAL(CP(SYS_BOOT1), (IDIS | PTD | DIS | M3)); /*DSS_DATA19*/
MUX_VAL(CP(SYS_BOOT3), (IDIS | PTD | DIS | M3)); /*DSS_DATA20*/
MUX_VAL(CP(SYS_BOOT4), (IDIS | PTD | DIS | M3)); /*DSS_DATA21*/
MUX_VAL(CP(SYS_BOOT5), (IDIS | PTD | DIS | M3)); /*DSS_DATA22*/
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M3)); /*DSS_DATA23*/
}
void set_muxconf_regs(void)
{
cm_t3x_set_common_muxconf();
if (get_cpu_family() == CPU_OMAP34XX)
cm_t35_set_muxconf();
else
cm_t3730_set_muxconf();
}
#if defined(CONFIG_MMC)
#define SB_T35_WP_GPIO 59
int board_mmc_getcd(struct mmc *mmc)
{
u8 val;
if (twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO, &val))
return -1;
return !(val & 1);
}
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, SB_T35_WP_GPIO);
}
#endif
#if defined(CONFIG_MMC)
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#ifdef CONFIG_SYS_I2C_OMAP24XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
*/
static int cm_t3x_reset_net_chip(int gpio)
{
/* Set GPIO1 of TPS65930 as output */
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
0x02);
/* Send a pulse on the GPIO pin */
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
0x02);
udelay(1);
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x09,
0x02);
mdelay(40);
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
0x02);
mdelay(1);
return 0;
}
#else
static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
#endif
#ifdef CONFIG_SMC911X
/*
* Routine: handle_mac_address
* Description: prepare MAC address for on-board Ethernet.
*/
static int handle_mac_address(void)
{
unsigned char enetaddr[6];
int rc;
rc = eth_env_get_enetaddr("ethaddr", enetaddr);
if (rc)
return 0;
rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (rc)
return rc;
if (!is_valid_ethaddr(enetaddr))
return -1;
return eth_env_set_enetaddr("ethaddr", enetaddr);
}
/*
* Routine: board_eth_init
* Description: initialize module and base-board Ethernet chips
*/
#define SB_T35_SMC911X_BASE (CONFIG_SMC911X_BASE + SZ_16M)
int board_eth_init(bd_t *bis)
{
int rc = 0, rc1 = 0;
rc1 = handle_mac_address();
if (rc1)
printf("No MAC address found! ");
rc1 = cl_omap3_smc911x_init(0, 5, CONFIG_SMC911X_BASE,
cm_t3x_reset_net_chip, -EINVAL);
if (rc1 > 0)
rc++;
rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
if (rc1 > 0)
rc++;
return rc;
}
#endif
#ifdef CONFIG_USB_EHCI_OMAP
struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
#define SB_T35_USB_HUB_RESET_GPIO 167
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u8 val;
int offset;
cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
/* Set GPIO6 and GPIO7 of TPS65930 as output */
val |= 0xC0;
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, val);
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_SETGPIODATAOUT1;
/* Take both PHYs out of reset */
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, offset, 0xC0);
udelay(1);
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(void)
{
cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_OMAP */

12
board/compulab/cm_t54/Kconfig
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@ -1,12 +0,0 @@
if TARGET_CM_T54
config SYS_BOARD
default "cm_t54"
config SYS_VENDOR
default "compulab"
config SYS_CONFIG_NAME
default "cm_t54"
endif

6
board/compulab/cm_t54/MAINTAINERS
View File

@ -1,6 +0,0 @@
CM_T54 BOARD
M: Dmitry Lifshitz <lifshitz@compulab.co.il>
S: Maintained
F: board/compulab/cm_t54/
F: include/configs/cm_t54.h
F: configs/cm_t54_defconfig

8
board/compulab/cm_t54/Makefile
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@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2014 Compulab Ltd - http://compulab.co.il/
#
# Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
obj-y += cm_t54.o
obj-$(CONFIG_SPL_BUILD) += mux.o spl.o

261
board/compulab/cm_t54/cm_t54.c
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@ -1,261 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board functions for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*/
#include <common.h>
#include <env.h>
#include <fdt_support.h>
#include <net.h>
#include <usb.h>
#include <mmc.h>
#include <palmas.h>
#include <spl.h>
#include <linux/delay.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/clock.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#include "../common/eeprom.h"
#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
#define DIE_ID_REG_OFFSET 0x200
DECLARE_GLOBAL_DATA_PTR;
#if !defined(CONFIG_SPL_BUILD)
inline void set_muxconf_regs(void){};
#endif
const struct omap_sysinfo sysinfo = {
"Board: CM-T54\n"
};
/*
* Routine: board_init
* Description: hardware init.
*/
int board_init(void)
{
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
return 0;
}
/*
* Routine: cm_t54_palmas_regulator_set
* Description: select voltage and turn on/off Palmas PMIC regulator.
*/
static int cm_t54_palmas_regulator_set(u8 vreg, u8 vval, u8 creg, u8 cval)
{
int err;
/* Setup voltage */
err = palmas_i2c_write_u8(TWL603X_CHIP_P1, vreg, vval);
if (err) {
printf("cm_t54: could not set regulator 0x%02x voltage : %d\n",
vreg, err);
return err;
}
/* Turn on/off regulator */
err = palmas_i2c_write_u8(TWL603X_CHIP_P1, creg, cval);
if (err) {
printf("cm_t54: could not turn on/off regulator 0x%02x : %d\n",
creg, err);
return err;
}
return 0;
}
/*
* Routine: mmc_get_env_part
* Description: setup environment storage device partition.
*/
#ifdef CONFIG_SYS_MMC_ENV_PART
uint mmc_get_env_part(struct mmc *mmc)
{
u32 bootmode = gd->arch.omap_boot_mode;
uint bootpart = CONFIG_SYS_MMC_ENV_PART;
/*
* If booted from eMMC boot partition then force eMMC
* FIRST boot partition to be env storage
*/
if (bootmode == BOOT_DEVICE_MMC2)
bootpart = 1;
return bootpart;
}
#endif
#if defined(CONFIG_MMC)
#define SB_T54_CD_GPIO 228
#define SB_T54_WP_GPIO 229
int board_mmc_init(bd_t *bis)
{
int ret0, ret1;
ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
if (ret0)
printf("cm_t54: failed to initialize mmc0\n");
ret1 = omap_mmc_init(1, 0, 0, -1, -1);
if (ret1)
printf("cm_t54: failed to initialize mmc1\n");
if (ret0 && ret1)
return -1;
return 0;
}
#endif
#ifdef CONFIG_USB_HOST_ETHER
int ft_board_setup(void *blob, bd_t *bd)
{
uint8_t enetaddr[6];
/* MAC addr */
if (eth_env_get_enetaddr("usbethaddr", enetaddr)) {
fdt_find_and_setprop(blob, "/smsc95xx@0", "mac-address",
enetaddr, 6, 1);
}
return 0;
}
static void generate_mac_addr(uint8_t *enetaddr)
{
int reg;
reg = DIE_ID_REG_BASE + DIE_ID_REG_OFFSET;
/*
* create a fake MAC address from the processor ID code.
* first byte is 0x02 to signify locally administered.
*/
enetaddr[0] = 0x02;
enetaddr[1] = readl(reg + 0x10) & 0xff;
enetaddr[2] = readl(reg + 0xC) & 0xff;
enetaddr[3] = readl(reg + 0x8) & 0xff;
enetaddr[4] = readl(reg) & 0xff;
enetaddr[5] = (readl(reg) >> 8) & 0xff;
}
/*
* Routine: handle_mac_address
* Description: prepare MAC address for on-board Ethernet.
*/
static int handle_mac_address(void)
{
uint8_t enetaddr[6];
int ret;
ret = eth_env_get_enetaddr("usbethaddr", enetaddr);
if (ret)
return 0;
ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
if (ret || !is_valid_ethaddr(enetaddr))
generate_mac_addr(enetaddr);
if (!is_valid_ethaddr(enetaddr))
return -1;
return eth_env_set_enetaddr("usbethaddr", enetaddr);
}
int board_eth_init(bd_t *bis)
{
return handle_mac_address();
}
#endif
#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_HSIC,
.port_mode[2] = OMAP_EHCI_PORT_MODE_HSIC,
};
static void setup_host_clocks(bool enable)
{
int usbhost_clk = OPTFCLKEN_HSIC60M_P3_CLK |
OPTFCLKEN_HSIC480M_P3_CLK |
OPTFCLKEN_HSIC60M_P2_CLK |
OPTFCLKEN_HSIC480M_P2_CLK |
OPTFCLKEN_UTMI_P3_CLK |
OPTFCLKEN_UTMI_P2_CLK;
int usbtll_clk = OPTFCLKEN_USB_CH1_CLK_ENABLE |
OPTFCLKEN_USB_CH2_CLK_ENABLE;
int usbhub_clk = CKOBUFFER_CLK_ENABLE_MASK;
if (enable) {
/* Enable port 2 and 3 clocks*/
setbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
/* Enable port 2 and 3 usb host ports tll clocks*/
setbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
/* Request FREF_XTAL_CLK clock for HSIC USB Hub */
setbits_le32((*ctrl)->control_ckobuffer, usbhub_clk);
} else {
clrbits_le32((*ctrl)->control_ckobuffer, usbhub_clk);
clrbits_le32((*prcm)->cm_l3init_hsusbtll_clkctrl, usbtll_clk);
clrbits_le32((*prcm)->cm_l3init_hsusbhost_clkctrl, usbhost_clk);
}
}
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
/* VCC_3V3_ETH */
cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_3V3, SMPS9_CTRL,
SMPS_MODE_SLP_AUTO | SMPS_MODE_ACT_AUTO);
setup_host_clocks(true);
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
printf("cm_t54: Failed to initialize ehci : %d\n", ret);
return ret;
}
int ehci_hcd_stop(void)
{
int ret = omap_ehci_hcd_stop();
setup_host_clocks(false);
cm_t54_palmas_regulator_set(SMPS9_VOLTAGE, SMPS_VOLT_OFF,
SMPS9_CTRL, SMPS_MODE_SLP_AUTO);
return ret;
}
void usb_hub_reset_devices(struct usb_hub_device *hub, int port)
{
/* The LAN9730 needs to be reset after the port power has been set. */
if (port == 3) {
gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 0);
udelay(10);
gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, 1);
}
}
#endif

94
board/compulab/cm_t54/mux.c
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@ -1,94 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Pinmux configuration for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*/
#ifndef _CM_T54_MUX_DATA_H
#define _CM_T54_MUX_DATA_H
#include <common.h>
#include <asm/arch/mux_omap5.h>
#include <asm/arch/sys_proto.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
/* MMC1 - SD CARD */
{SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
{SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
{SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */
{SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */
{SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */
{SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */
/* SD CARD CD and WP GPIOs*/
{TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */
{TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */
/* MMC2 - eMMC */
{EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
{EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
{EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
{EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
{EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
{EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
{EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
{EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
{EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
{EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
/* UART4 */
{I2C5_SCL, (PTU | IEN | M2)}, /* UART4_RX */
{I2C5_SDA, (M2)}, /* UART4_TX */
/* Led */
{HSI2_CAFLAG, (PTU | M6)}, /* GPIO3_80 */
/* I2C1 */
{I2C1_PMIC_SCL, (PTU | IEN | M0)}, /* I2C1_PMIC_SCL */
{I2C1_PMIC_SDA, (PTU | IEN | M0)}, /* I2C1_PMIC_SDA */
/* USBB2, USBB3 */
{USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
{USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
{USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE */
{USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
/* USB Hub and USB Eth reset GPIOs */
{HSI2_CAREADY, (PTD | M6)}, /* GPIO3_76 */
{HSI2_ACDATA, (PTD | M6)}, /* GPIO3_83 */
/* I2C4 */
{I2C4_SCL, (PTU | IEN | M0)}, /* I2C4_SCL */
{I2C4_SDA, (PTU | IEN | M0)}, /* I2C4_SDA */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
{SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
{SYS_32K, (IEN | M0)}, /* SYS_32K */
/* USB Hub clock */
{FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
};
/*
* Routine: set_muxconf_regs
* Description: setup board pinmux configuration.
*/
void set_muxconf_regs(void)
{
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
}
#endif /* _CM_T54_MUX_DATA_H */

65
board/compulab/cm_t54/spl.c
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@ -1,65 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SPL specific code for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*/
#include <asm/emif.h>
const struct emif_regs emif_regs_ddr3_532_mhz_cm_t54 = {
#if defined(CONFIG_DRAM_1G) || defined(CONFIG_DRAM_512M)
.sdram_config_init = 0x618522B2,
.sdram_config = 0x618522B2,
#elif defined(CONFIG_DRAM_2G)
.sdram_config_init = 0x618522BA,
.sdram_config = 0x618522BA,
#endif
.sdram_config2 = 0x0,
.ref_ctrl = 0x00001040,
.sdram_tim1 = 0xEEEF36F3,
.sdram_tim2 = 0x348F7FDA,
.sdram_tim3 = 0x027F88A8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x1007190B,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0030400B,
.emif_ddr_phy_ctlr_1 = 0x0034400B,
.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x40000305,
};
const struct dmm_lisa_map_regs lisa_map_cm_t54 = {
.dmm_lisa_map_0 = 0x0,
.dmm_lisa_map_1 = 0x0,
#ifdef CONFIG_DRAM_2G
.dmm_lisa_map_2 = 0x80740300,
#elif defined(CONFIG_DRAM_1G)
.dmm_lisa_map_2 = 0x80640300,
#elif defined(CONFIG_DRAM_512M)
.dmm_lisa_map_2 = 0x80500100,
#endif
.dmm_lisa_map_3 = 0x00000000,
.is_ma_present = 0x1,
};
void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
{
*regs = &emif_regs_ddr3_532_mhz_cm_t54;
}
void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
{
*dmm_lisa_regs = &lisa_map_cm_t54;
}

15
board/freescale/mx31pdk/Kconfig
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@ -1,15 +0,0 @@
if TARGET_MX31PDK
config SYS_BOARD
default "mx31pdk"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "mx31"
config SYS_CONFIG_NAME
default "mx31pdk"
endif

6
board/freescale/mx31pdk/MAINTAINERS
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@ -1,6 +0,0 @@
MX31PDK BOARD
M: Magnus Lilja <lilja.magnus@gmail.com>
S: Maintained
F: board/freescale/mx31pdk/
F: include/configs/mx31pdk.h
F: configs/mx31pdk_defconfig

11
board/freescale/mx31pdk/Makefile
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@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifdef CONFIG_SPL_BUILD
obj-y += lowlevel_init.o
endif
obj-y += mx31pdk.o

76
board/freescale/mx31pdk/lowlevel_init.S
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@ -1,76 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
*/
#include <config.h>
#include <asm/arch/imx-regs.h>
#include <asm/macro.h>
.globl lowlevel_init
lowlevel_init:
/* Also setup the Peripheral Port Remap register inside the core */
ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */
mcr p15, 0, r0, c15, c2, 4
write32 IPU_CONF, IPU_CONF_DI_EN
write32 CCM_CCMR, CCM_CCMR_SETUP
wait_timer 0x40000
write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE
write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS
/* Set up clock to 532MHz */
write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ
write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ
write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
/* Set up MX31 DDR pins */
write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0
write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0
write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0
write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000
write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0
write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0
write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0
write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0
write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0
write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0
write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0
write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0
write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0
write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0
write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0
write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0
write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0
write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0
write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0
write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0
write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0
write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0
write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0
write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0
write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0
write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0
write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0
/* Set up MX31 DDR Memory Controller */
write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP
write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP
/* Perform DDR init sequence */
write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE
write32 CSD0_BASE | 0x0f00, 0x12344321
write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH
write32 CSD0_BASE, 0x12344321
write32 CSD0_BASE, 0x12344321
write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG
write8 CSD0_BASE | 0x00000033, 0xda
write8 CSD0_BASE | 0x01000000, 0xff
write32 WEIM_ESDCTL0, ESDCTL_RW
write32 CSD0_BASE, 0xDEADBEEF
write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL
mov pc, lr

119
board/freescale/mx31pdk/mx31pdk.c
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@ -1,119 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
*
* (C) Copyright 2009 Magnus Lilja <lilja.magnus@gmail.com>
*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <watchdog.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong bootflag)
{
/*
* copy ourselves from where we are running to where we were
* linked at. Use ulong pointers as all addresses involved
* are 4-byte-aligned.
*/
ulong *start_ptr, *end_ptr, *link_ptr, *run_ptr, *dst;
asm volatile ("ldr %0, =_start" : "=r"(start_ptr));
asm volatile ("ldr %0, =_end" : "=r"(end_ptr));
asm volatile ("ldr %0, =board_init_f" : "=r"(link_ptr));
asm volatile ("adr %0, board_init_f" : "=r"(run_ptr));
for (dst = start_ptr; dst < end_ptr; dst++)
*dst = *(dst+(run_ptr-link_ptr));
/*
* branch to nand_boot's link-time address.
*/
asm volatile("ldr pc, =nand_boot");
}
#endif
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
int board_early_init_f(void)
{
/* CS5: CPLD incl. network controller */
static const struct mxc_weimcs cs5 = {
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 24, 0, 4, 3),
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
CSCR_L(2, 2, 2, 5, 2, 0, 5, 2, 0, 0, 0, 1),
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
CSCR_A(2, 2, 2, 2, 0, 0, 2, 2, 0, 0, 0, 0, 0, 0)
};
mxc_setup_weimcs(5, &cs5);
/* Setup UART1 and SPI2 pins */
mx31_uart1_hw_init();
mx31_spi2_hw_init();
return 0;
}
int board_init(void)
{
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
int board_late_init(void)
{
u32 val;
struct pmic *p;
int ret;
ret = pmic_init(CONFIG_FSL_PMIC_BUS);
if (ret)
return ret;
p = pmic_get("FSL_PMIC");
if (!p)
return -ENODEV;
/* Enable RTC battery */
pmic_reg_read(p, REG_POWER_CTL0, &val);
pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
hw_watchdog_init();
#endif
return 0;
}
int checkboard(void)
{
printf("Board: MX31PDK\n");
return 0;
}
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}

12
board/gumstix/duovero/Kconfig
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@ -1,12 +0,0 @@
if TARGET_DUOVERO
config SYS_BOARD
default "duovero"
config SYS_VENDOR
default "gumstix"
config SYS_CONFIG_NAME
default "duovero"
endif

6
board/gumstix/duovero/MAINTAINERS
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@ -1,6 +0,0 @@
DUOVERO BOARD
M: Ash Charles <ash@gumstix.com>
S: Maintained
F: board/gumstix/duovero/
F: include/configs/duovero.h
F: configs/duovero_defconfig

6
board/gumstix/duovero/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := duovero.o

273
board/gumstix/duovero/duovero.c
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@ -1,273 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013
* Gumstix Inc. <www.gumstix.com>
* Maintainer: Ash Charles <ash@gumstix.com>
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mmc_host_def.h>
#include <twl6030.h>
#include <asm/emif.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include <linux/delay.h>
#include "duovero_mux_data.h"
#define WIFI_EN 43
#if defined(CONFIG_CMD_NET)
#define SMSC_NRESET 45
static void setup_net_chip(void);
#endif
#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
const struct omap_sysinfo sysinfo = {
"Board: duovero\n"
};
struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
/**
* @brief board_init
*
* @return 0
*/
int board_init(void)
{
gpmc_init();
gd->bd->bi_arch_number = MACH_TYPE_DUOVERO;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
/**
* @brief misc_init_r - Configure board specific configurations
* such as power configurations, ethernet initialization as phase2 of
* boot sequence
*
* @return 0
*/
int misc_init_r(void)
{
int ret = 0;
u8 val;
/* wifi setup: first enable 32Khz clock from 6030 pmic */
val = 0xe1;
ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1);
if (ret)
printf("Failed to enable 32Khz clock to wifi module\n");
/* then setup WIFI_EN as an output pin and send reset pulse */
if (!gpio_request(WIFI_EN, "")) {
gpio_direction_output(WIFI_EN, 0);
gpio_set_value(WIFI_EN, 1);
udelay(1);
gpio_set_value(WIFI_EN, 0);
udelay(1);
gpio_set_value(WIFI_EN, 1);
}
#if defined(CONFIG_CMD_NET)
setup_net_chip();
#endif
return 0;
}
void set_muxconf_regs(void)
{
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_essential,
sizeof(core_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_essential,
sizeof(wkup_padconf_array_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_core_base,
core_padconf_array_non_essential,
sizeof(core_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
do_set_mux((*ctrl)->control_padconf_wkup_base,
wkup_padconf_array_non_essential,
sizeof(wkup_padconf_array_non_essential) /
sizeof(struct pad_conf_entry));
}
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#if !defined(CONFIG_SPL_BUILD)
void board_mmc_power_init(void)
{
twl6030_power_mmc_init(0);
}
#endif
#endif
#if defined(CONFIG_CMD_NET)
#define GPMC_SIZE_16M 0xF
#define GPMC_BASEADDR_MASK 0x3F
#define GPMC_CS_ENABLE 0x1
static void enable_gpmc_net_config(const u32 *gpmc_config, const struct gpmc_cs *cs,
u32 base, u32 size)
{
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/*
* Enable the config. size is the CS size and goes in
* bits 11:8. We set bit 6 to enable this CS and the base
* address goes into bits 5:0.
*/
writel((size << 8) | (GPMC_CS_ENABLE << 6) |
((base >> 24) & GPMC_BASEADDR_MASK),
&cs->config7);
sdelay(2000);
}
/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */
#define NET_LAN9221_GPMC_CONFIG1 0x2a001203
#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02
#define NET_LAN9221_GPMC_CONFIG3 0x00020200
#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03
#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a
#define NET_LAN9221_GPMC_CONFIG6 0x8a070707
#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c
/* GPMC definitions for LAN9221 chips on expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
* Ethernet hardware.
*/
static void setup_net_chip(void)
{
enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
GPMC_SIZE_16M);
/* Make GPIO SMSC_NRESET as output pin and send reset pulse */
if (!gpio_request(SMSC_NRESET, "")) {
gpio_direction_output(SMSC_NRESET, 0);
gpio_set_value(SMSC_NRESET, 1);
udelay(1);
gpio_set_value(SMSC_NRESET, 0);
udelay(1);
gpio_set_value(SMSC_NRESET, 1);
}
}
#endif
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
return rc;
}
#ifdef CONFIG_USB_EHCI_HCD
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int utmi_clk;
u32 auxclk, altclksrc;
/* Now we can enable our port clocks */
utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
auxclk = readl(&scrm->auxclk3);
/* Select sys_clk */
auxclk &= ~AUXCLK_SRCSELECT_MASK;
auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
/* Set the divisor to 2 */
auxclk &= ~AUXCLK_CLKDIV_MASK;
auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
/* Request auxilary clock #3 */
auxclk |= AUXCLK_ENABLE_MASK;
writel(auxclk, &scrm->auxclk3);
altclksrc = readl(&scrm->altclksrc);
/* Activate alternate system clock supplier */
altclksrc &= ~ALTCLKSRC_MODE_MASK;
altclksrc |= ALTCLKSRC_MODE_ACTIVE;
/* enable clocks */
altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
writel(altclksrc, &scrm->altclksrc);
ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
if (ret < 0)
return ret;
return 0;
}
int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
#endif
/*
* get_board_rev() - get board revision
*/
u32 get_board_rev(void)
{
return 0x20;
}

198
board/gumstix/duovero/duovero_mux_data.h
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@ -1,198 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012
* Gumstix Incorporated, <www.gumstix.com>
* Maintainer: Ash Charles <ash@gumstix.com>
*/
#ifndef _DUOVERO_MUX_DATA_H_
#define _DUOVERO_MUX_DATA_H_
#include <asm/arch/mux_omap4.h>
const struct pad_conf_entry core_padconf_array_essential[] = {
{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */
{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */
{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */
{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */
{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */
{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */
{UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */
{UART3_TX_IRTX, (M0)} /* uart3_tx */
};
const struct pad_conf_entry wkup_padconf_array_essential[] = {
{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */
{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */
{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */
};
const struct pad_conf_entry core_padconf_array_non_essential[] = {
{GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */
{GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */
{GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */
{GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */
{GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */
{GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */
{GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */
{GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */
{GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */
{GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */
{GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */
{GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */
{GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */
{GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */
{GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */
{GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */
{GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */
{GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */
{GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */
{GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */
{GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */
{GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */
{GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */
{GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */
{GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */
{GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */
{GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */
{GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */
{GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */
{GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */
{C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */
{C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */
{GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */
{GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */
{GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */
{GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */
{GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */
{GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */
{GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */
{GPMC_NOE, (PTU | M0)}, /* gpmc_noe */
{GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */
{HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */
{HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */
{HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */
{HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */
{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */
{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */
{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */
{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */
{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */
{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */
{CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */
{CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */
{CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */
{CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */
{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */
{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */
{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */
{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */
{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
{USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */
{USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */
{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */
{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */
{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */
{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */
{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */
{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */
{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */
{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */
{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */
{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */
{ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */
{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */
{UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */
{UART2_RTS, (M0)}, /* uart2_rts */
{UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */
{UART2_TX, (M0)}, /* uart2_tx */
{HDQ_SIO, (M0)}, /* hdq-sio */
{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */
{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */
{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */
{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */
{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */
{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */
{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */
{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */
{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */
{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */
{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */
{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */
{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */
{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */
{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */
{UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */
{UART4_TX, (M0)}, /* uart4_tx */
{USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */
{USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */
{USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */
{USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/
{USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */
{USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */
{USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */
{USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */
{USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */
{USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/
{USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */
{USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */
{USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */
{USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */
{UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */
{SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */
{SYS_BOOT0, (M0)}, /* sys_boot0 */
{SYS_BOOT1, (M0)}, /* sys_boot1 */
{SYS_BOOT2, (M0)}, /* sys_boot2 */
{SYS_BOOT3, (M0)}, /* sys_boot3 */
{SYS_BOOT4, (M0)}, /* sys_boot4 */
{SYS_BOOT5, (M0)}, /* sys_boot5 */
{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */
{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */
{DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */
{DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */
{DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */
{DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */
};
const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
{PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */
{PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */
{PAD1_FREF_CLK3_REQ, M7}, /* safe mode */
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */
{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */
{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */
{PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */
{PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */
};
#endif /* _DUOVERO_MUX_DATA_H_ */

15
board/gumstix/pepper/Kconfig
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@ -1,15 +0,0 @@
if TARGET_PEPPER
config SYS_BOARD
default "pepper"
config SYS_VENDOR
default "gumstix"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "pepper"
endif

6
board/gumstix/pepper/MAINTAINERS
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@ -1,6 +0,0 @@
PEPPER BOARD
M: Ash Charles <ash@gumstix.com>
S: Maintained
F: board/gumstix/pepper/
F: include/configs/pepper.h
F: configs/pepper_defconfig

11
board/gumstix/pepper/Makefile
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@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Makefile
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
ifdef CONFIG_SPL_BUILD
obj-y += mux.o
endif
obj-y += board.o

288
board/gumstix/pepper/board.c
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@ -1,288 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Board functions for Gumstix Pepper and AM335x-based boards
*
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
* Based on board/ti/am335x/board.c from Texas Instruments, Inc.
*/
#include <common.h>
#include <env.h>
#include <errno.h>
#include <init.h>
#include <net.h>
#include <serial.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <miiphy.h>
#include <cpsw.h>
#include <power/tps65217.h>
#include <watchdog.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SPL_BUILD
#define OSC (V_OSCK/1000000)
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,
.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
const struct ctrl_ioregs ioregs_ddr3 = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
.datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
};
static const struct cmd_control ddr2_cmd_ctrl_data = {
.cmd0csratio = MT47H128M16RT25E_RATIO,
.cmd1csratio = MT47H128M16RT25E_RATIO,
.cmd2csratio = MT47H128M16RT25E_RATIO,
};
static const struct emif_regs ddr2_emif_reg_data = {
.sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
.ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
.sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
.sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
.sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
};
const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
const struct ctrl_ioregs ioregs_ddr2 = {
.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
};
static int read_eeprom(struct pepper_board_id *header)
{
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
return -ENODEV;
}
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
sizeof(struct pepper_board_id))) {
return -EIO;
}
return 0;
}
const struct dpll_params *get_dpll_ddr_params(void)
{
struct pepper_board_id header;
enable_i2c0_pin_mux();
i2c_set_bus_num(0);
if (read_eeprom(&header) < 0)
return &dpll_ddr3;
switch (header.device_vendor) {
case GUMSTIX_PEPPER:
return &dpll_ddr2;
case GUMSTIX_PEPPER_DVI:
return &dpll_ddr3;
default:
return &dpll_ddr3;
}
}
void sdram_init(void)
{
const struct dpll_params *dpll = get_dpll_ddr_params();
/*
* Here we are assuming PLL clock reveals the type of RAM.
* DDR2 = 266
* DDR3 = 400
* Note that DDR3 is the default.
*/
if (dpll->m == 266) {
config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
else if (dpll->m == 400) {
config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
}
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
return serial_tstc() && serial_getc() == 'c';
}
#endif
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
#endif
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;
}
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
.phy_if = PHY_INTERFACE_MODE_RGMII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
const char *devname;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
}
writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
/*
*
* CPSW RGMII Internal Delay Mode is not supported in all PVT
* operating points. So we must set the TX clock delay feature
* in the KSZ9021 PHY. Since we only support a single ethernet
* device in U-Boot, we only do this for the current instance.
*/
devname = miiphy_get_current_dev();
/* max rx/tx clock delay, min rx/tx control delay */
miiphy_write(devname, 0x0, 0x0b, 0x8104);
miiphy_write(devname, 0x0, 0xc, 0xa0a0);
/* min rx data delay */
miiphy_write(devname, 0x0, 0x0b, 0x8105);
miiphy_write(devname, 0x0, 0x0c, 0x0000);
/* min tx data delay */
miiphy_write(devname, 0x0, 0x0b, 0x8106);
miiphy_write(devname, 0x0, 0x0c, 0x0000);
return n;
}
#endif

31
board/gumstix/pepper/board.h
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@ -1,31 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Gumstix Pepper and AM335x-based boards information header
*
* Copyright (C) 2014, Gumstix, Inc. - http://www.gumstix.com/
*/
#ifndef _BOARD_H_
#define _BOARD_H_
#define GUMSTIX_PEPPER 0x30000200
#define GUMSTIX_PEPPER_DVI 0x31000200
struct pepper_board_id {
unsigned int device_vendor;
unsigned char revision;
unsigned char content;
char fab_revision[8];
char env_var[16];
char en_setting[64];
};
/*
* We must be able to enable uart0, for initial output. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
void enable_i2c0_pin_mux(void);
#endif

82
board/gumstix/pepper/mux.c
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@ -1,82 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Muxing for Gumstix Pepper and AM335x-based boards
*
* Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>
#include "board.h"
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
static struct module_pin_mux i2c0_pin_mux[] = {
/* I2C_DATA */
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
/* I2C_SCLK */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
{-1},
};
static struct module_pin_mux rgmii1_pin_mux[] = {
{OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
{OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
{OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
{OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
{OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
{OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
{OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
{OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
{OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
{OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
{OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
{OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{OFFSET(rmii1_refclk), MODE(7) | RXACTIVE}, /* ETH_INT */
{OFFSET(mii1_col), MODE(7) | PULLUP_EN}, /* PHY_NRESET */
{OFFSET(xdma_event_intr1), MODE(3)},
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_i2c0_pin_mux(void)
{
configure_module_pin_mux(i2c0_pin_mux);
}
/*
* Do board-specific muxes.
*/
void enable_board_pin_mux(void)
{
/* I2C0 */
configure_module_pin_mux(i2c0_pin_mux);
/* SD Card */
configure_module_pin_mux(mmc0_pin_mux);
/* Ethernet pinmux. */
configure_module_pin_mux(rgmii1_pin_mux);
}

12
board/logicpd/zoom1/Kconfig
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@ -1,12 +0,0 @@
if TARGET_OMAP3_ZOOM1
config SYS_BOARD
default "zoom1"
config SYS_VENDOR
default "logicpd"
config SYS_CONFIG_NAME
default "omap3_zoom1"
endif

6
board/logicpd/zoom1/MAINTAINERS
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@ -1,6 +0,0 @@
ZOOM1 BOARD
M: Nishanth Menon <nm@ti.com>
S: Maintained
F: board/logicpd/zoom1/
F: include/configs/omap3_zoom1.h
F: configs/omap3_zoom1_defconfig

6
board/logicpd/zoom1/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y := zoom1.o

14
board/logicpd/zoom1/config.mk
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@ -1,14 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2006-2008
# Texas Instruments, <www.ti.com>
#
# Zoom MDK uses OMAP3 (ARM-CortexA8) cpu
# see http://www.ti.com/ for more information on Texas Instruments
# Physical Address:
# 8000'0000 (bank0)
# A000/0000 (bank1)
# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
# (mem base + reserved)
# For use with external or internal boots.

148
board/logicpd/zoom1/zoom1.c
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@ -1,148 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*
* Author :
* Nishanth Menon <nm@ti.com>
*
* Derived from Beagle Board and 3430 SDP code by
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
*/
#include <common.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <net.h>
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
#include <linux/mtd/omap_gpmc.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-types.h>
#include "zoom1.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* gpmc_cfg is initialized by gpmc_init and we use it here.
* GPMC definitions for Ethenet Controller LAN9211
*/
static const u32 gpmc_lab_enet[] = {
ZOOM1_ENET_GPMC_CONF1,
ZOOM1_ENET_GPMC_CONF2,
ZOOM1_ENET_GPMC_CONF3,
ZOOM1_ENET_GPMC_CONF4,
ZOOM1_ENET_GPMC_CONF5,
ZOOM1_ENET_GPMC_CONF6,
/*CONF7- computed as params */
};
static const struct ns16550_platdata zoom1_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(zoom1_uart) = {
"ns16550_serial",
&zoom1_serial
};
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* CS1 is Ethernet LAN9211 */
enable_gpmc_cs_config(gpmc_lab_enet, &gpmc_cfg->cs[1],
DEBUG_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_LDP;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
/*
* Routine: misc_init_r
* Description: Configure zoom board specific configurations
*/
int misc_init_r(void)
{
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
omap_die_id_display();
/*
* Board Reset
* The board is reset by holding the red button on the
* top right front face for eight seconds.
*/
twl4030_power_reset_init();
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
/* platform specific muxes */
MUX_ZOOM1_MDK();
}
#ifdef CONFIG_MMC
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
int rc = 0;
#ifdef CONFIG_SMC911X
#define STR_ENV_ETHADDR "ethaddr"
struct eth_device *dev;
uchar eth_addr[6];
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
if (!eth_env_get_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
dev = eth_get_dev_by_index(0);
if (dev) {
eth_env_set_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
} else {
printf("zoom1: Couldn't get eth device\n");
rc = -1;
}
}
#endif
return rc;
}
#endif

122
board/logicpd/zoom1/zoom1.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008
* Texas Instruments
* Nishanth Menon <nm@ti.com>
*
* Derived from: board/omap3/beagle/beagle.h
* Dirk Behme <dirk.behme@gmail.com>
*/
#ifndef _BOARD_ZOOM1_H_
#define _BOARD_ZOOM1_H_
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"OMAP3 Zoom MDK Rev 1",
"NAND",
};
#define ZOOM1_ENET_GPMC_CONF1 0x00611000
#define ZOOM1_ENET_GPMC_CONF2 0x001F1F01
#define ZOOM1_ENET_GPMC_CONF3 0x00080803
#define ZOOM1_ENET_GPMC_CONF4 0x1D091D09
#define ZOOM1_ENET_GPMC_CONF5 0x041D1F1F
#define ZOOM1_ENET_GPMC_CONF6 0x1D0904C4
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_ZOOM1_MDK() \
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
/*GPMC*/\
MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | DIS | M7)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | DIS | M4)) /*GPMC_nCS3 -> GPIO54*/\
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | DIS | M4)) /*GPMC_nCS4 -> GPIO 55*/\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M4)) /*GPMC_nCS5 -> GPIO 56*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*GPMC_nCS7 -> GPMC_IO_DIR*/\
MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /*GPMC_WAIT0*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/
#endif /* _BOARD_ZOOM_H_ */

9
board/overo/Kconfig
View File

@ -1,9 +0,0 @@
if TARGET_OMAP3_OVERO
config SYS_BOARD
default "overo"
config SYS_CONFIG_NAME
default "omap3_overo"
endif

6
board/overo/MAINTAINERS
View File

@ -1,6 +0,0 @@
OVERO BOARD
M: Steve Sakoman <sakoman@gmail.com>
S: Maintained
F: board/overo/
F: include/configs/omap3_overo.h
F: configs/omap3_overo_defconfig

10
board/overo/Makefile
View File

@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000, 2001, 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifdef CONFIG_SPL_BUILD
obj-y := spl.o common.o
else
obj-y := overo.o common.o
endif

368
board/overo/common.c
View File

@ -1,368 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Maintainer : Steve Sakoman <steve@sakoman.com>
*
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*/
#include <serial.h>
#include <twl4030.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/omap_mmc.h>
#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
#define TWL4030_I2C_BUS 0
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OVERO;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#if defined(CONFIG_MMC)
void board_mmc_power_init(void)
{
twl4030_power_mmc_init(0);
}
#endif
#if defined(CONFIG_SPL_OS_BOOT)
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
if (serial_tstc() && serial_getc() == 'c')
return 1;
return 0;
}
#endif /* CONFIG_SPL_OS_BOOT */
#define MUX_OVERO() \
/*SDRC*/\
MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
/*GPMC*/\
MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) /*GPMC_D0*/\
MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) /*GPMC_D1*/\
MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) /*GPMC_D2*/\
MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) /*GPMC_D3*/\
MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) /*GPMC_D4*/\
MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) /*GPMC_D5*/\
MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) /*GPMC_D6*/\
MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) /*GPMC_D7*/\
MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) /*GPMC_D8*/\
MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) /*GPMC_D9*/\
MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) /*GPMC_D10*/\
MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) /*GPMC_D11*/\
MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) /*GPMC_D12*/\
MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) /*GPMC_D13*/\
MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) /*GPMC_D14*/\
MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) /*GPMC_D15*/\
MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
/* - MMC1_WP*/\
MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M0)) /*GPMC_nCS7*/\
MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nCS3*/\
MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M0)) /*GPMC_CLK*/\
MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
/*CAMERA*/\
MUX_VAL(CP(CAM_HS), (IEN | PTU | DIS | M0)) /*CAM_HS */\
MUX_VAL(CP(CAM_VS), (IEN | PTU | DIS | M0)) /*CAM_VS */\
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | DIS | M0)) /*CAM_PCLK*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) /*CAM_D0*/\
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) /*CAM_D1*/\
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) /*CAM_D2*/\
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) /*CAM_D3*/\
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) /*CAM_D4*/\
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) /*CAM_D5*/\
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) /*CAM_D6*/\
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) /*CAM_D7*/\
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) /*CAM_D8*/\
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) /*CAM_D9*/\
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) /*CAM_D10*/\
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) /*CAM_D11*/\
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
/*Audio Interface */\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) /*McBSP2_CLKX*/\
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) /*McBSP2_DR*/\
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
/*Expansion card */\
MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) /*MMC1_CLK*/\
MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\
MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M0)) /*MMC1_DAT4*/\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M0)) /*MMC1_DAT5*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M0)) /*MMC1_DAT6*/\
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M0)) /*MMC1_DAT7*/\
/*Wireless LAN */\
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
/*Bluetooth*/\
MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M0)) /*McBSP4_CLKX*/\
MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M0)) /*McBSP4_DR*/\
MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M0)) /*McBSP4_DX*/\
MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M0)) /*McBSP4_FSX*/\
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*McBSP1_CLKR*/\
MUX_VAL(CP(MCBSP1_FSR), (IEN | PTD | DIS | M0)) /*McBSP1_FSR*/\
MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M0)) /*McBSP1_DX*/\
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) /*McBSP1_DR*/\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) /*McBSP_CLKS*/\
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) /*McBSP1_FSX*/\
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) /*McBSP1_CLKX*/\
/*Serial Interface*/\
MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
/* BT_NRESET*/\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTU | EN | M0)) /*UART3_RX_IRRX*/\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /*I2C1_SCL*/\
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) /*I2C1_SDA*/\
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
/* - USBH_CPEN*/\
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
/* - USBH_RESET*/\
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) /*I2C3_SCL*/\
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) /*I2C3_SDA*/\
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) /*I2C4_SCL*/\
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) /*I2C4_SDA*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA2*/\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA7*/\
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA4*/\
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA5*/\
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA6*/\
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA3*/\
/*Control and debug */\
MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) /*SYS_CLKREQ*/\
MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) /*SYS_nIRQ*/\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 - MMC1_WP*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\
MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\
/* - W2W_NRESET*/\
MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\
MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\
MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\
MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_NXT*/\
MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA0*/\
MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DATA1*/\
/* die to die */\
MUX_VAL(CP(D2D_MCAD1), (IEN | PTD | EN | M0)) /*d2d_mcad1*/\
MUX_VAL(CP(D2D_MCAD2), (IEN | PTD | EN | M0)) /*d2d_mcad2*/\
MUX_VAL(CP(D2D_MCAD3), (IEN | PTD | EN | M0)) /*d2d_mcad3*/\
MUX_VAL(CP(D2D_MCAD4), (IEN | PTD | EN | M0)) /*d2d_mcad4*/\
MUX_VAL(CP(D2D_MCAD5), (IEN | PTD | EN | M0)) /*d2d_mcad5*/\
MUX_VAL(CP(D2D_MCAD6), (IEN | PTD | EN | M0)) /*d2d_mcad6*/\
MUX_VAL(CP(D2D_MCAD7), (IEN | PTD | EN | M0)) /*d2d_mcad7*/\
MUX_VAL(CP(D2D_MCAD8), (IEN | PTD | EN | M0)) /*d2d_mcad8*/\
MUX_VAL(CP(D2D_MCAD9), (IEN | PTD | EN | M0)) /*d2d_mcad9*/\
MUX_VAL(CP(D2D_MCAD10), (IEN | PTD | EN | M0)) /*d2d_mcad10*/\
MUX_VAL(CP(D2D_MCAD11), (IEN | PTD | EN | M0)) /*d2d_mcad11*/\
MUX_VAL(CP(D2D_MCAD12), (IEN | PTD | EN | M0)) /*d2d_mcad12*/\
MUX_VAL(CP(D2D_MCAD13), (IEN | PTD | EN | M0)) /*d2d_mcad13*/\
MUX_VAL(CP(D2D_MCAD14), (IEN | PTD | EN | M0)) /*d2d_mcad14*/\
MUX_VAL(CP(D2D_MCAD15), (IEN | PTD | EN | M0)) /*d2d_mcad15*/\
MUX_VAL(CP(D2D_MCAD16), (IEN | PTD | EN | M0)) /*d2d_mcad16*/\
MUX_VAL(CP(D2D_MCAD17), (IEN | PTD | EN | M0)) /*d2d_mcad17*/\
MUX_VAL(CP(D2D_MCAD18), (IEN | PTD | EN | M0)) /*d2d_mcad18*/\
MUX_VAL(CP(D2D_MCAD19), (IEN | PTD | EN | M0)) /*d2d_mcad19*/\
MUX_VAL(CP(D2D_MCAD20), (IEN | PTD | EN | M0)) /*d2d_mcad20*/\
MUX_VAL(CP(D2D_MCAD21), (IEN | PTD | EN | M0)) /*d2d_mcad21*/\
MUX_VAL(CP(D2D_MCAD22), (IEN | PTD | EN | M0)) /*d2d_mcad22*/\
MUX_VAL(CP(D2D_MCAD23), (IEN | PTD | EN | M0)) /*d2d_mcad23*/\
MUX_VAL(CP(D2D_MCAD24), (IEN | PTD | EN | M0)) /*d2d_mcad24*/\
MUX_VAL(CP(D2D_MCAD25), (IEN | PTD | EN | M0)) /*d2d_mcad25*/\
MUX_VAL(CP(D2D_MCAD26), (IEN | PTD | EN | M0)) /*d2d_mcad26*/\
MUX_VAL(CP(D2D_MCAD27), (IEN | PTD | EN | M0)) /*d2d_mcad27*/\
MUX_VAL(CP(D2D_MCAD28), (IEN | PTD | EN | M0)) /*d2d_mcad28*/\
MUX_VAL(CP(D2D_MCAD29), (IEN | PTD | EN | M0)) /*d2d_mcad29*/\
MUX_VAL(CP(D2D_MCAD30), (IEN | PTD | EN | M0)) /*d2d_mcad30*/\
MUX_VAL(CP(D2D_MCAD31), (IEN | PTD | EN | M0)) /*d2d_mcad31*/\
MUX_VAL(CP(D2D_MCAD32), (IEN | PTD | EN | M0)) /*d2d_mcad32*/\
MUX_VAL(CP(D2D_MCAD33), (IEN | PTD | EN | M0)) /*d2d_mcad33*/\
MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) /*d2d_mcad34*/\
MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) /*d2d_mcad35*/\
MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) /*d2d_mcad36*/\
MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) /*d2d_clk26mi*/\
MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) /*d2d_nrespwron*/\
MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) /*d2d_nreswarm */\
MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) /*d2d_arm9nirq */\
MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) /*d2d_spint*/\
MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) /*d2d_frint*/\
MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) /*d2d_dmareq0*/\
MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) /*d2d_dmareq1*/\
MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) /*d2d_dmareq2*/\
MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) /*d2d_dmareq3*/\
MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) /*d2d_n3gtrst*/\
MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) /*d2d_n3gtdi*/\
MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) /*d2d_n3gtdo*/\
MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) /*d2d_n3gtms*/\
MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) /*d2d_n3gtck*/\
MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) /*d2d_n3grtck*/\
MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) /*d2d_mstdby*/\
MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) /*d2d_swakeup*/\
MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) /*d2d_idlereq*/\
MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) /*d2d_idleack*/\
MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) /*d2d_mwrite*/\
MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) /*d2d_swrite*/\
MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) /*d2d_mread*/\
MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) /*d2d_sread*/\
MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_mbusflag*/\
MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) /*d2d_sbusflag*/\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/
/*
* Routine: get_board_revision
* Description: Returns the board revision
*/
int get_board_revision(void)
{
int revision;
if (!gpio_request(112, "") &&
!gpio_request(113, "") &&
!gpio_request(115, "")) {
gpio_direction_input(112);
gpio_direction_input(113);
gpio_direction_input(115);
revision = gpio_get_value(115) << 2 |
gpio_get_value(113) << 1 |
gpio_get_value(112);
} else {
puts("Error: unable to acquire board revision GPIOs\n");
revision = -1;
}
return revision;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_OVERO();
}

411
board/overo/overo.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Maintainer : Steve Sakoman <steve@sakoman.com>
*
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*/
#include <common.h>
#include <dm.h>
#include <env.h>
#include <init.h>
#include <malloc.h>
#include <net.h>
#include <ns16550.h>
#include <netdev.h>
#include <twl4030.h>
#include <linux/delay.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-types.h>
#include "overo.h"
#ifdef CONFIG_USB_EHCI_HCD
#include <usb.h>
#include <asm/ehci-omap.h>
#endif
#define TWL4030_I2C_BUS 0
#define EXPANSION_EEPROM_I2C_BUS 2
#define EXPANSION_EEPROM_I2C_ADDRESS 0x51
#define GUMSTIX_EMPTY_EEPROM 0x0
#define GUMSTIX_SUMMIT 0x01000200
#define GUMSTIX_TOBI 0x02000200
#define GUMSTIX_TOBI_DUO 0x03000200
#define GUMSTIX_PALO35 0x04000200
#define GUMSTIX_PALO43 0x05000200
#define GUMSTIX_CHESTNUT43 0x06000200
#define GUMSTIX_PINTO 0x07000200
#define GUMSTIX_GALLOP43 0x08000200
#define GUMSTIX_ALTO35 0x09000200
#define GUMSTIX_STAGECOACH 0x0A000200
#define GUMSTIX_THUMBO 0x0B000200
#define GUMSTIX_TURTLECORE 0x0C000200
#define GUMSTIX_ARBOR43C 0x0D000200
#define ETTUS_USRP_E 0x01000300
#define GUMSTIX_NO_EEPROM 0xffffffff
static struct {
unsigned int device_vendor;
unsigned char revision;
unsigned char content;
char fab_revision[8];
char env_var[16];
char env_setting[64];
} expansion_config = {0x0};
static const struct ns16550_platdata overo_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(overo_uart) = {
"ns16550_serial",
&overo_serial
};
/*
* Routine: get_sdio2_config
* Description: Return information about the wifi module connection
* Returns 0 if the module connects though a level translator
* Returns 1 if the module connects directly
*/
int get_sdio2_config(void)
{
int sdio_direct;
if (!gpio_request(130, "") && !gpio_request(139, "")) {
gpio_direction_output(130, 0);
gpio_direction_input(139);
sdio_direct = 1;
gpio_set_value(130, 0);
if (gpio_get_value(139) == 0) {
gpio_set_value(130, 1);
if (gpio_get_value(139) == 1)
sdio_direct = 0;
}
gpio_direction_input(130);
} else {
puts("Error: unable to acquire sdio2 clk GPIOs\n");
sdio_direct = -1;
}
return sdio_direct;
}
/*
* Routine: get_expansion_id
* Description: This function checks for expansion board by checking I2C
* bus 2 for the availability of an AT24C01B serial EEPROM.
* returns the device_vendor field from the EEPROM
*/
unsigned int get_expansion_id(void)
{
if (expansion_config.device_vendor != 0x0)
return expansion_config.device_vendor;
i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
/* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
i2c_set_bus_num(TWL4030_I2C_BUS);
return GUMSTIX_NO_EEPROM;
}
/* read configuration data */
i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
sizeof(expansion_config));
i2c_set_bus_num(TWL4030_I2C_BUS);
return expansion_config.device_vendor;
}
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
unsigned int expansion_id;
twl4030_power_init();
twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
printf("Board revision: %d\n", get_board_revision());
switch (get_sdio2_config()) {
case 0:
puts("Tranceiver detected on mmc2\n");
MUX_OVERO_SDIO2_TRANSCEIVER();
break;
case 1:
puts("Direct connection on mmc2\n");
MUX_OVERO_SDIO2_DIRECT();
break;
default:
puts("Unable to detect mmc2 connection type\n");
}
expansion_id = get_expansion_id();
switch (expansion_id) {
case GUMSTIX_SUMMIT:
printf("Recognized Summit expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("defaultdisplay", "dvi");
env_set("expansionname", "summit");
break;
case GUMSTIX_TOBI:
printf("Recognized Tobi expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("defaultdisplay", "dvi");
env_set("expansionname", "tobi");
break;
case GUMSTIX_TOBI_DUO:
printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("expansionname", "tobiduo");
break;
case GUMSTIX_PALO35:
printf("Recognized Palo35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("defaultdisplay", "lcd35");
env_set("expansionname", "palo35");
break;
case GUMSTIX_PALO43:
printf("Recognized Palo43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("defaultdisplay", "lcd43");
env_set("expansionname", "palo43");
break;
case GUMSTIX_CHESTNUT43:
printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("defaultdisplay", "lcd43");
env_set("expansionname", "chestnut43");
break;
case GUMSTIX_PINTO:
printf("Recognized Pinto expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_GALLOP43:
printf("Recognized Gallop43 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
env_set("defaultdisplay", "lcd43");
env_set("expansionname", "gallop43");
break;
case GUMSTIX_ALTO35:
printf("Recognized Alto35 expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_ALTO35();
env_set("defaultdisplay", "lcd35");
env_set("expansionname", "alto35");
break;
case GUMSTIX_STAGECOACH:
printf("Recognized Stagecoach expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_THUMBO:
printf("Recognized Thumbo expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_TURTLECORE:
printf("Recognized Turtlecore expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
break;
case GUMSTIX_ARBOR43C:
printf("Recognized Arbor43C expansion board (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_ARBOR43C();
env_set("defaultdisplay", "lcd43");
env_set("expansionname", "arbor43c");
break;
case ETTUS_USRP_E:
printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
expansion_config.revision,
expansion_config.fab_revision);
MUX_GUMSTIX();
MUX_USRP_E();
env_set("defaultdisplay", "dvi");
break;
case GUMSTIX_NO_EEPROM:
case GUMSTIX_EMPTY_EEPROM:
puts("No or empty EEPROM on expansion board\n");
MUX_GUMSTIX();
env_set("expansionname", "tobi");
break;
default:
printf("Unrecognized expansion board 0x%08x\n", expansion_id);
break;
}
if (expansion_config.content == 1)
env_set(expansion_config.env_var, expansion_config.env_setting);
omap_die_id_display();
if (get_cpu_family() == CPU_OMAP34XX)
env_set("boardname", "overo");
else
env_set("boardname", "overo-storm");
return 0;
}
#if defined(CONFIG_CMD_NET)
/* GPMC definitions for LAN9221 chips on Tobi expansion boards */
static const u32 gpmc_lan_config[] = {
NET_LAN9221_GPMC_CONFIG1,
NET_LAN9221_GPMC_CONFIG2,
NET_LAN9221_GPMC_CONFIG3,
NET_LAN9221_GPMC_CONFIG4,
NET_LAN9221_GPMC_CONFIG5,
NET_LAN9221_GPMC_CONFIG6,
/*CONFIG7- computed as params */
};
/*
* Routine: setup_net_chip
* Description: Setting up the configuration GPMC registers specific to the
* Ethernet hardware.
*/
static void setup_net_chip(void)
{
struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
&ctrl_base->gpmc_nadv_ale);
}
/*
* Routine: reset_net_chip
* Description: Reset the Ethernet hardware.
*/
static void reset_net_chip(void)
{
/* Make GPIO 64 as output pin and send a magic pulse through it */
if (!gpio_request(64, "")) {
gpio_direction_output(64, 0);
gpio_set_value(64, 1);
udelay(1);
gpio_set_value(64, 0);
udelay(1);
gpio_set_value(64, 1);
}
}
int board_eth_init(bd_t *bis)
{
unsigned int expansion_id;
int rc = 0;
#ifdef CONFIG_SMC911X
expansion_id = get_expansion_id();
switch (expansion_id) {
case GUMSTIX_TOBI_DUO:
/* second lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
0x2B000000, GPMC_SIZE_16M);
/* no break */
case GUMSTIX_TOBI:
case GUMSTIX_CHESTNUT43:
case GUMSTIX_STAGECOACH:
case GUMSTIX_NO_EEPROM:
case GUMSTIX_EMPTY_EEPROM:
/* first lan chip */
enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5],
0x2C000000, GPMC_SIZE_16M);
setup_net_chip();
reset_net_chip();
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
break;
default:
break;
}
#endif
return rc;
}
#endif
#if defined(CONFIG_USB_EHCI_HCD)
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};
#define GUMSTIX_GPIO_USBH_CPEN 168
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
/* Enable USB power */
if (!gpio_request(GUMSTIX_GPIO_USBH_CPEN, "usbh_cpen"))
gpio_direction_output(GUMSTIX_GPIO_USBH_CPEN, 1);
return omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
}
int ehci_hcd_stop(void)
{
/* Disable USB power */
gpio_set_value(GUMSTIX_GPIO_USBH_CPEN, 0);
gpio_free(GUMSTIX_GPIO_USBH_CPEN);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_HCD */

169
board/overo/overo.h
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@ -1,169 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008
* Steve Sakoman <steve@sakoman.com>
*/
#ifndef _OVERO_H_
#define _OVERO_H_
const omap3_sysinfo sysinfo = {
DDR_STACKED,
"Gumstix Overo board",
#if defined(CONFIG_ENV_IS_IN_ONENAND)
"OneNAND",
#else
"NAND",
#endif
};
int get_board_revision(void);
/* overo revisions */
#define REVISION_0 0x0
#define REVISION_1 0x1
#define REVISION_2 0x2
#define REVISION_3 0x3
#define REVISION_4 0x4
/*
* IEN - Input Enable
* IDIS - Input Disable
* PTD - Pull type Down
* PTU - Pull type Up
* DIS - Pull type selection is inactive
* EN - Pull type selection is active
* M0 - Mode 0
* The commented string gives the final mux configuration for that pin
*/
#define MUX_GUMSTIX() \
/*GPMC*/\
MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M0)) /*GPMC_nCS6*/\
MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
/* - CAM_IRQ*/\
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
/* - SMSC911X_NRES*/\
MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
/*DSS*/\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) /*DSS_ACBIAS*/\
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
/*CAMERA*/\
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M0)) /*CAM_WEN*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
/* - PEN_DOWN*/\
/*Bluetooth*/\
MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
/*Serial Interface*/\
MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTD | EN | M0)) /*UART3_CTS_RCTX*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) /*McSPI1_CLK*/\
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) /*McSPI1_SIMO */\
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) /*McSPI1_SOMI */\
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) /*McSPI1_CS0*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M0)) /*McSPI1_CS1*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
/* - LAN_INTR */\
/*Control and debug */\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
MUX_VAL(CP(ETK_CLK_ES2), (IEN | PTU | EN | M2)) /*MMC3_CLK*/\
MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT3*/\
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\
#define MUX_OVERO_SDIO2_DIRECT() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M0)) /*MMC2_DAT4*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M0)) /*MMC2_DAT5*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M0)) /*MMC2_DAT6*/\
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M0)) /*MMC2_DAT7*/\
MUX_VAL(CP(MMC1_DAT4), (IEN | PTD | EN | M4)) /*GPIO_126*/\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
#define MUX_OVERO_SDIO2_TRANSCEIVER() \
MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M0)) /*MMC2_CLK*/\
MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M0)) /*MMC2_CMD*/\
MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M0)) /*MMC2_DAT0*/\
MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M0)) /*MMC2_DAT1*/\
MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M0)) /*MMC2_DAT2*/\
MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M0)) /*MMC2_DAT3*/\
MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT0*/\
MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M1)) /*MMC2_DIR_DAT1*/\
MUX_VAL(CP(MMC2_DAT6), (IEN | PTU | EN | M1)) /*MMC2_DIR_CMD*/\
MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M1)) /*MMC2_CLKIN*/\
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) /*GPIO_126*/\
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*GPIO_127*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) /*GPIO_128*/\
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) /*GPIO_129*/
#define MUX_USRP_E() \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M4)) /*GPIO_173 */\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175 */\
#define MUX_ALTO35() \
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-BTN*/\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M4)) /*GPIO_148-RED LED*/\
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
MUX_VAL(CP(UART1_RX), (IDIS | PTD | DIS | M4)) /*GPIO_151-BLUE LED*/\
MUX_VAL(CP(HDQ_SIO), (IDIS | PTD | DIS | M4)) /*GPIO_170-GREEN LED*/\
MUX_VAL(CP(MCSPI1_CS1), (IDIS | PTD | EN | M4)) /*GPIO_175*/\
#define MUX_ARBOR43C() \
MUX_VAL(CP(CSI2_DX1), (IDIS | PTD | DIS | M4)) /*GPIO_114-RED LED*/\
MUX_VAL(CP(UART1_CTS), (IDIS | PTD | DIS | M4)) /*GPIO_150-YELLOW LED*/\
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M4)) /*GPIO_170-BUTTON */\
MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTD | DIS | M4)) /*GPIO_186-BLUE LED*/\
MUX_VAL(CP(JTAG_EMU1), (IDIS | PTD | DIS | M4)) /*GPIO_31-CAP WAKE*/\
MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10-CAP IRQ*/\
#endif

61
board/overo/spl.c
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@ -1,61 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Maintainer : Steve Sakoman <steve@sakoman.com>
*
* Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
* Sunil Kumar <sunilsaini05@gmail.com>
* Shashi Ranjan <shashiranjanmca05@gmail.com>
*
* (C) Copyright 2004-2008
* Texas Instruments, <www.ti.com>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/sys_proto.h>
#include "overo.h"
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on both banks.
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->mr = MICRON_V_MR_165;
switch (get_board_revision()) {
case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
timings->mcfg = MICRON_V_MCFG_165(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
break;
case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
case REVISION_4:
timings->mcfg = MICRON_V_MCFG_200(256 << 20);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
timings->ctrla = HYNIX_V_ACTIMA_200;
timings->ctrlb = HYNIX_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
timings->mcfg = MCFG(512 << 20, 15);
timings->ctrla = MICRON_V_ACTIMA_200;
timings->ctrlb = MICRON_V_ACTIMB_200;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
break;
default:
timings->mcfg = MICRON_V_MCFG_165(128 << 20);
timings->ctrla = MICRON_V_ACTIMA_165;
timings->ctrlb = MICRON_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
}
}

12
board/quipos/cairo/Kconfig
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@ -1,12 +0,0 @@
if TARGET_OMAP3_CAIRO
config SYS_BOARD
default "cairo"
config SYS_VENDOR
default "quipos"
config SYS_CONFIG_NAME
default "omap3_cairo"
endif

6
board/quipos/cairo/MAINTAINERS
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@ -1,6 +0,0 @@
CAIRO BOARD
M: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
S: Maintained
F: board/quipos/cairo/
F: include/configs/omap3_cairo.h
F: configs/cairo_defconfig

6
board/quipos/cairo/Makefile
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@ -1,6 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2014 DENX Software Engineering
# Written-By: Albert ARIBAUD <albert.aribaud@3adev.fr>
obj-y := cairo.o

98
board/quipos/cairo/cairo.c
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@ -1,98 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2014 DENX
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
*
* Derived from code written by Robert Aigner (ra@spiid.net)
*
* Itself derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*/
#include <common.h>
#include <dm.h>
#include <netdev.h>
#include <ns16550.h>
#include <asm/io.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <asm/mach-types.h>
#include <asm/omap_mmc.h>
#include "cairo.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* Routine: board_init
* Description: Early hardware init.
*/
int board_init(void)
{
gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
/* board id for Linux */
gd->bd->bi_arch_number = CONFIG_MACH_TYPE;
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
return 0;
}
/*
* Routine: set_muxconf_regs
* Description: Setting up the configuration Mux registers specific to the
* hardware. Many pins need to be moved from protect to primary
* mode.
*/
void set_muxconf_regs(void)
{
MUX_CAIRO();
}
#if defined(CONFIG_MMC)
int board_mmc_init(bd_t *bis)
{
return omap_mmc_init(0, 0, 0, -1, -1);
}
#endif
#ifdef CONFIG_SPL_BUILD
/*
* Routine: get_board_mem_timings
* Description: If we use SPL then there is no x-loader nor config header
* so we have to setup the DDR timings ourself on the first bank. This
* provides the timing values back to the function that configures
* the memory.
*
* The Cairo board uses SAMSUNG DDR - K4X51163PG-FGC6
*/
void get_board_mem_timings(struct board_sdrc_timings *timings)
{
timings->sharing = SAMSUNG_SHARING;
timings->mcfg = SAMSUNG_V_MCFG_165(128 << 20);
timings->ctrla = SAMSUNG_V_ACTIMA_165;
timings->ctrlb = SAMSUNG_V_ACTIMB_165;
timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
timings->mr = SAMSUNG_V_MR_165;
}
#endif
static const struct ns16550_platdata cairo_serial = {
.base = OMAP34XX_UART2,
.reg_shift = 2,
.clock = V_NS16550_CLK,
.fcr = UART_FCR_DEFVAL,
};
U_BOOT_DEVICE(cairo_uart) = {
"ns16550_serial",
&cairo_serial
};
/* force SPL booting into U-Boot, not Linux */
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
return 1;
}
#endif

318
board/quipos/cairo/cairo.h
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@ -1,318 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) DENX
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
*
* Original code (C) Copyright 2010
* Robert Aigner (ra@spiid.net)
*/
#ifndef _EVM_H_
#define _EVM_H_
const omap3_sysinfo sysinfo = {
DDR_DISCRETE,
"OMAP3 Cairo board",
"NAND",
};
/*
* OMAP3 Cairo handheld hardware revision
*/
enum {
OMAP3_CAIRO_BOARD_GEN_1 = 0, /* Cairo handheld V01 */
OMAP3_CAIRO_BOARD_GEN_2,
};
#define MUX_CAIRO() \
MUX_VAL(CONTROL_PADCONF_GPIO112, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO113, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO114, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO115, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO126, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO127, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO128, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPIO129, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_D2, (IEN | DIS | SB_HIZ | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_D5, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D6, (IEN | PTD | EN | SB_HIZ | SB_PD | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D7, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D8, (IEN | DIS | SB_HIZ | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_D10, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_VS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_WEN, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_XCLKA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_CAM_XCLKB, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
MUX_VAL(CONTROL_PADCONF_DSS_ACBIAS, (IDIS | PTD | EN | SB_HIZ | SB_PD | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA0, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA1, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA2, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA3, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA4, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA5, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA6, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA7, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA8, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA9, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA10, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA11, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA12, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA13, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA14, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA15, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA16, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA17, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA18, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA19, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA21, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA22, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_DATA23, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D3_ES2, (IEN | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D4_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D5_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D6_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D7_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D8_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D9_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D10_ES2, (IDIS | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D11_ES2, (IDIS | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D12_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D13_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D14_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_ETK_D15_ES2, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A1, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A2, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A3, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A4, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A5, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A6, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A7, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A8, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A9, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A10, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_A11, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_CLK, (IEN | DIS | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D0, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D1, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D2, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D3, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D4, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D5, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D6, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D7, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D8, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D9, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D10, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D11, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D12, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D13, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D14, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_D15, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NADV_ALE, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NBE0_CLE, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NBE1, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS0, (IDIS | DIS | SB_HIZ | SB_PD | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS1, (IEN | DIS | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS2, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS3, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS4, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS5, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS6, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NCS7, (IDIS | DIS | SB_HIZ | SB_PD | M3)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NOE, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NWE, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_NWP, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT0, (IEN | DIS | SB_HIZ | M0)) \
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT1, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT2, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_GPMC_WAIT3, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_HDQ_SIO, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_CLK, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA0, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA1, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA2, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA3, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA4, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA5, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA6, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DATA7, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_DIR, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_NXT, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_HSUSB0_STP, (IDIS | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_I2C1_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_I2C1_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_I2C2_SCL, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_I2C2_SDA, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_I2C3_SCL, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_I2C3_SDA, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_I2C4_SCL, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_I2C4_SDA, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_JTAG_EMU0, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_EMU1, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_NTRST, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_RTCK, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_TCK, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_TDI, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_TDO, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_JTAG_TMS, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_MCBSP_CLKS, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_MCBSP1_CLKX, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_MCBSP1_DR, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_MCBSP1_DX, (IEN | DIS | SB_HIZ | SB_PD | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP1_FSR, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP1_FSX, (IEN | DIS | SB_HIZ | M4)) \
MUX_VAL(CONTROL_PADCONF_MCBSP2_CLKX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP2_DR, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP2_DX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP2_FSX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP3_CLKX, (IDIS | DIS | SB_HIZ | SB_PU | M1)) \
MUX_VAL(CONTROL_PADCONF_MCBSP3_DR, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
MUX_VAL(CONTROL_PADCONF_MCBSP3_DX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP3_FSX, (IEN | PTU | EN | SB_HIZ | SB_PU | M1)) \
MUX_VAL(CONTROL_PADCONF_MCBSP4_CLKX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP4_DR, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP4_DX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCBSP4_FSX, (IEN | PTD | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_CLK, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_CS0, (IEN | PTU | EN | SB_HIZ | SB_PD | M0)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_CS1, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_CS2, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_CS3, (IEN | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_SIMO, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_MCSPI1_SOMI, (IEN | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_MCSPI2_CLK, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_MCSPI2_CS0, (IEN | PTU | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_MCSPI2_CS1, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_MCSPI2_SIMO, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_MCSPI2_SOMI, (IEN | PTD | EN | M3)) \
MUX_VAL(CONTROL_PADCONF_MMC1_CLK, (IDIS | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC1_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC1_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC1_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC1_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC1_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_CLK, (IEN | PTD | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_CMD, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT0, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT1, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT2, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT3, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT4, (IDIS | DIS | SB_HIZ | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT5, (IDIS | DIS | SB_HIZ | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT6, (IDIS | DIS | SB_HIZ | M0)) \
MUX_VAL(CONTROL_PADCONF_MMC2_DAT7, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A0, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A1, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A2, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A3, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A4, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A5, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A6, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A7, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A8, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A9, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A10, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A11, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A12, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A13, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_A14, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_BA0, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_BA1, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_CKE0, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_CKE1, (IDIS | DIS | M7)) \
MUX_VAL(CONTROL_PADCONF_SDRC_CLK, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D0, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D1, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D2, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D3, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D4, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D5, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D6, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D7, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D8, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D9, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D10, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D11, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D12, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D13, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D14, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D15, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D16, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D17, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D18, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D19, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D20, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D21, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D22, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D23, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D24, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D25, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D26, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D27, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D28, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D29, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D30, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_D31, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DM0, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DM1, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DM2, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DM3, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DQS0, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DQS1, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DQS2, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_DQS3, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_NCAS, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_NCLK, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_NCS0, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_NCS1, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_NRAS, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SDRC_NWE, (IDIS | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_32K, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT0, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT1, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT2, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT3, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT4, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT5, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_BOOT6, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT1, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_CLKOUT2, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_CLKREQ, (IEN | DIS | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_NIRQ, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_NRESWARM, (IEN | PTU | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_SYS_OFF_MODE, (IDIS | PTD | EN | M0)) \
MUX_VAL(CONTROL_PADCONF_UART1_CTS, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART1_RTS, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART1_RX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART1_TX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART2_CTS, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_UART2_RTS, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_UART2_RX, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_UART2_TX, (IEN | PTU | EN | M7)) \
MUX_VAL(CONTROL_PADCONF_UART3_CTS_RCTX, \
(IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART3_RTS_SD, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART3_RX_IRRX, (IEN | PTU | EN | SB_HIZ | SB_PU | M0)) \
MUX_VAL(CONTROL_PADCONF_UART3_TX_IRTX, (IDIS | DIS | SB_HIZ | SB_PU | M0)) \
#endif

15
board/silica/pengwyn/Kconfig
View File

@ -1,15 +0,0 @@
if TARGET_PENGWYN
config SYS_BOARD
default "pengwyn"
config SYS_VENDOR
default "silica"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "pengwyn"
endif

6
board/silica/pengwyn/MAINTAINERS
View File

@ -1,6 +0,0 @@
PENGWYN BOARD
M: Lothar Felten <lothar.felten@gmail.com>
S: Maintained
F: board/silica/pengwyn/
F: include/configs/pengwyn.h
F: configs/pengwyn_defconfig

11
board/silica/pengwyn/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Makefile
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
obj-y += board.o

204
board/silica/pengwyn/board.c
View File

@ -1,204 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* board.c
*
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
*/
#include <common.h>
#include <env.h>
#include <init.h>
#include <net.h>
#include <serial.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <phy.h>
#include <cpsw.h>
#include "board.h"
DECLARE_GLOBAL_DATA_PTR;
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#if defined(CONFIG_SPL_BUILD)
/* DDR3 RAM timings */
static const struct ddr_data ddr3_data = {
.datardsratio0 = MT41K128MJT187E_RD_DQS,
.datawdsratio0 = MT41K128MJT187E_WR_DQS,
.datafwsratio0 = MT41K128MJT187E_PHY_FIFO_WE,
.datawrsratio0 = MT41K128MJT187E_PHY_WR_DATA,
};
static const struct cmd_control ddr3_cmd_ctrl_data = {
.cmd0csratio = MT41K128MJT187E_RATIO,
.cmd0iclkout = MT41K128MJT187E_INVERT_CLKOUT,
.cmd1csratio = MT41K128MJT187E_RATIO,
.cmd1iclkout = MT41K128MJT187E_INVERT_CLKOUT,
.cmd2csratio = MT41K128MJT187E_RATIO,
.cmd2iclkout = MT41K128MJT187E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K128MJT187E_EMIF_SDCFG,
.ref_ctrl = MT41K128MJT187E_EMIF_SDREF,
.sdram_tim1 = MT41K128MJT187E_EMIF_TIM1,
.sdram_tim2 = MT41K128MJT187E_EMIF_TIM2,
.sdram_tim3 = MT41K128MJT187E_EMIF_TIM3,
.zq_config = MT41K128MJT187E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K128MJT187E_EMIF_READ_LATENCY |
PHY_EN_DYN_PWRDN,
};
const struct ctrl_ioregs ddr3_ioregs = {
.cm0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
.cm1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
.cm2ioctl = MT41K128MJT187E_IOCTRL_VALUE,
.dt0ioctl = MT41K128MJT187E_IOCTRL_VALUE,
.dt1ioctl = MT41K128MJT187E_IOCTRL_VALUE,
};
#ifdef CONFIG_SPL_OS_BOOT
int spl_start_uboot(void)
{
/* break into full u-boot on 'c' */
return serial_tstc() && serial_getc() == 'c';
}
#endif
#define OSC (V_OSCK/1000000)
const struct dpll_params dpll_ddr_266 = {
266, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_303 = {
303, OSC-1, 1, -1, -1, -1, -1};
const struct dpll_params dpll_ddr_400 = {
400, OSC-1, 1, -1, -1, -1, -1};
void am33xx_spl_board_init(void)
{
/*
* The pengwyn board uses the TPS650250 PMIC without I2C
* interface and will output the following fixed voltages:
* DCDC1=3V3 (IO) DCDC2=1V5 (DDR) DCDC3=1V26 (Vmpu)
* VLDO1=1V8 (IO) VLDO2=1V8(IO)
* Vcore=1V1 is fixed, generated by TPS62231
*/
/* Get the frequency */
dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
/* Set CORE Frequencies to OPP100 */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* 720MHz cpu, this might change on newer board revisions */
dpll_mpu_opp100.m = MPUPLL_M_720;
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
}
const struct dpll_params *get_dpll_ddr_params(void)
{
/* future configs can return other clock settings */
return &dpll_ddr_303;
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
void sdram_init(void)
{
config_ddr(303, &ddr3_ioregs, &ddr3_data,
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
}
#endif /* if CONFIG_SPL_BUILD */
/*
* Basic board specific setup. Pinmux has been handled already.
*/
int board_init(void)
{
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
gpmc_init();
return 0;
}
#ifdef CONFIG_DRIVER_TI_CPSW
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 1,
.phy_if = PHY_INTERFACE_MODE_MII,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr[6];
uint32_t mac_hi, mac_lo;
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
printf("<ethaddr> not set. Reading from E-fuse\n");
/* try reading mac address from efuse */
mac_lo = readl(&cdev->macid0l);
mac_hi = readl(&cdev->macid0h);
mac_addr[0] = mac_hi & 0xFF;
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
mac_addr[4] = mac_lo & 0xFF;
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
if (is_valid_ethaddr(mac_addr))
eth_env_set_enetaddr("ethaddr", mac_addr);
else
return n;
}
writel(MII_MODE_ENABLE, &cdev->miisel);
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
return n;
}
#endif /* if CONFIG_DRIVER_TI_CPSW */

14
board/silica/pengwyn/board.h
View File

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* board.h
*
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
*/
#ifndef _BOARD_H_
#define _BOARD_H_
void enable_uart0_pin_mux(void);
void enable_board_pin_mux(void);
#endif

97
board/silica/pengwyn/mux.c
View File

@ -1,97 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* mux.c
*
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include "board.h"
/* UART0 pins E15(rx),E16(tx) [E17(rts),E18(cts)] */
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
{-1},
};
/* unused: UART1 pins D15(tx),D16(rx),D17(cts),D18(rts) */
/* I2C pins C16(scl)/C17(sda) */
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C0_DATA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
PULLUDEN | SLEWCTRL)}, /* I2C0_SCLK */
{-1},
};
/* MMC0 pins */
static struct module_pin_mux mmc0_pin_mux[] = {
{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
{-1},
};
/* MII pins */
static struct module_pin_mux mii1_pin_mux[] = {
{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
{-1},
};
/* NAND pins */
static struct module_pin_mux nand_pin_mux[] = {
{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
{-1},
};
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_board_pin_mux()
{
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(mii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
configure_module_pin_mux(nand_pin_mux);
}

1
configs/am335x_igep003x_defconfig
View File

@ -72,6 +72,7 @@ CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_FDT_FIXUP_PARTITIONS=y

69
configs/birdland_bav335a_defconfig
View File

@ -1,69 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_AM33XX=y
CONFIG_TARGET_BAV335X=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_BAV_VERSION=1
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_OF_LIBFDT=y

69
configs/birdland_bav335b_defconfig
View File

@ -1,69 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_AM33XX=y
CONFIG_TARGET_BAV335X=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_BAV_VERSION=2
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MUSB_NEW_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82000000
CONFIG_MMC_OMAP_HS=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=24000000
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_PHY_SMSC=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
CONFIG_FAT_WRITE=y
CONFIG_LZO=y
CONFIG_OF_LIBFDT=y

40
configs/cairo_defconfig
View File

@ -1,40 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_SPL_TEXT_BASE=0x40200800
CONFIG_TARGET_OMAP3_CAIRO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=-2
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Cairo # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_NET is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_CONS_INDEX=2
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

65
configs/cm_t35_defconfig
View File

@ -1,65 +0,0 @@
CONFIG_ARM=y
# CONFIG_SYS_THUMB_BUILD is not set
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_TEXT_BASE=0x80008000
CONFIG_ENV_SIZE=0x4000
CONFIG_SPL_TEXT_BASE=0x40200800
CONFIG_TARGET_CM_T35=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_BOOTDELAY=3
# CONFIG_CONSOLE_MUX is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_SPL_FS_EXT4 is not set
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="CM-T3x # "
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v1, v2, v3"
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),256k(u-boot-env),4m(kernel),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y
CONFIG_LED_STATUS_BIT=186
CONFIG_LED_STATUS_STATE=2
CONFIG_LED_STATUS_BOOT_ENABLE=y
CONFIG_LED_STATUS_BOOT=0
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_TWL4030_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_VIDEO_OMAP3=y
CONFIG_LCD=y
CONFIG_OF_LIBFDT=y

53
configs/cm_t54_defconfig
View File

@ -1,53 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP54XX=y
CONFIG_TARGET_CM_T54=y
CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0xC4000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_MISC_INIT_R is not set
CONFIG_VERSION_VARIABLE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x200
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_SATA_SUPPORT=y
CONFIG_SYS_PROMPT="CM-T54 # "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_EEPROM_LAYOUT=y
CONFIG_EEPROM_LAYOUT_HELP_STRING="v2, v3"
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SCSI_AHCI=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=4
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

4
configs/db-88f6281-bp-nand_defconfig
View File

@ -20,7 +20,6 @@ CONFIG_CMD_DM=y
CONFIG_CMD_IDE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -43,7 +42,7 @@ CONFIG_DM=y
CONFIG_MVSATA_IDE=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
@ -53,6 +52,7 @@ CONFIG_DM_RTC=y
CONFIG_RTC_MV=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_KIRKWOOD_SPI=y
CONFIG_USB=y
CONFIG_DM_USB=y

8
configs/draco_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_DRACO=y
@ -27,6 +28,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -43,7 +45,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -59,24 +60,27 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(
CONFIG_CMD_UBI=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y

42
configs/duovero_defconfig
View File

@ -1,42 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_TEXT_BASE=0x40300000
CONFIG_OMAP44XX=y
CONFIG_TARGET_DUOVERO=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then run update_to_fit; fi; run findfdt; run init_console; run envboot; run distro_bootcmd"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_SPL_I2C_SUPPORT is not set
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SYS_PROMPT="duovero # "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_PARTITION_UUIDS=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

8
configs/etamin_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x980000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_ETAMIN=y
@ -28,6 +29,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -44,7 +46,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -60,24 +61,27 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand_concat:512k(spl),512k(spl.backup1),
CONFIG_CMD_UBI=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y

40
configs/mx31pdk_defconfig
View File

@ -1,40 +0,0 @@
CONFIG_ARM=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_MX31=y
CONFIG_SPL_LDSCRIPT="arch/arm/cpu/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x87e00000
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0x40000
CONFIG_TARGET_MX31PDK=y
CONFIG_SPL_TEXT_BASE=0x87dc0000
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x60000
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_SPL_NAND_SUPPORT=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_CMD_BOOTZ=y
CONFIG_CMD_SPI=y
CONFIG_DEFAULT_SPI_BUS=1
CONFIG_DEFAULT_SPI_MODE=4
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_MXC_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXC=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0xB6000000
CONFIG_SMC911X_32_BIT=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y

53
configs/omap3_overo_defconfig
View File

@ -1,53 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_OFFSET=0x240000
CONFIG_SPL_TEXT_BASE=0x40200000
CONFIG_TARGET_OMAP3_OVERO=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SYS_PROMPT="Overo # "
# CONFIG_CMD_IMI is not set
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(xloader),1792k(u-boot),256k(environ),8m(linux),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPL_NAND_SIMPLE=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x2C000000
CONFIG_SMC911X_32_BIT=y
CONFIG_CONS_INDEX=3
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_FAT_WRITE=y
CONFIG_BCH=y
CONFIG_OF_LIBFDT=y

41
configs/omap3_zoom1_defconfig
View File

@ -1,41 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_ZOOM1=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
# CONFIG_CMD_IMI is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_NAND_LOCK_UNLOCK=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand:512k(x-loader),1920k(u-boot),128k(u-boot-env),4m(kernel),-(fs)"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_TWL4030_LED=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SMC911X=y
CONFIG_SMC911X_BASE=0x08000000
CONFIG_SMC911X_32_BIT=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_UDC=y
CONFIG_USB_OMAP3=y
CONFIG_TWL4030_USB=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

68
configs/pengwyn_defconfig
View File

@ -1,68 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_AM33XX=y
CONFIG_TARGET_PENGWYN=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM335x U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x240000
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_WOL=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:512k(SPL),512k(SPL.backup1),512k(SPL.backup2),512k(SPL.backup3),1536k(u-boot),512k(u-boot-spl-os),512k(u-boot-env),5m(kernel),-(rootfs)"
CONFIG_CMD_DIAG=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y
CONFIG_USB_MUSB_GADGET=y
CONFIG_USB_MUSB_DSPS=y
CONFIG_USB_GADGET=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

43
configs/pepper_defconfig
View File

@ -1,43 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_AM33XX=y
CONFIG_TARGET_PEPPER=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SYS_PROMPT="pepper# "
CONFIG_CMD_ASKENV=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_BOOTP_DNS2=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_MMC_OMAP_HS=y
CONFIG_PHY_ADDR_ENABLE=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_FAT_WRITE=y
CONFIG_OF_LIBFDT=y

8
configs/pxm2_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=720
CONFIG_TARGET_PXM2=y
@ -28,6 +29,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -43,7 +45,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -60,17 +61,19 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),128k(uboot.env),5120k(kernel_a),5120k(kernel_b),8192k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-pxm50"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
@ -78,6 +81,7 @@ CONFIG_PHY_ATHEROS=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y

8
configs/rastaban_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_RASTABAN=y
@ -27,6 +28,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -43,7 +45,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -59,24 +60,27 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(
CONFIG_CMD_UBI=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y

8
configs/rut_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=600
CONFIG_TARGET_RUT=y
@ -29,6 +30,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_ARCH_EARLY_INIT_R=y
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -44,7 +46,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -61,17 +62,19 @@ CONFIG_MTDIDS_DEFAULT="nand0=omap2-nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(spl.backup2),128k(spl.backup3),1920k(u-boot),128k(uboot.env),5120k(kernel_a),5120k(kernel_b),8192k(mtdoops),-(rootfs)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-rut"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
@ -79,6 +82,7 @@ CONFIG_PHY_NATSEMI=y
CONFIG_MII=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y

8
configs/thuban_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
CONFIG_SPL_DM_SPI=y
CONFIG_AM33XX=y
CONFIG_SYS_MPUCLK=300
CONFIG_TARGET_THUBAN=y
@ -27,6 +28,7 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_SPL_I2C_SUPPORT=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
@ -43,7 +45,6 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND=y
CONFIG_CMD_SF=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
@ -59,24 +60,27 @@ CONFIG_MTDPARTS_DEFAULT="mtdparts=omap2-nand.0:128k(spl),128k(spl.backup1),128k(
CONFIG_CMD_UBI=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_EMBED=y
CONFIG_DEFAULT_DEVICE_TREE="am335x-draco"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DFU_NAND=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHY_SMSC=y
CONFIG_DRIVER_TI_CPSW=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_OMAP3_SPI=y
CONFIG_USB=y
CONFIG_USB_MUSB_HOST=y

5
doc/README.omap3
View File

@ -41,11 +41,6 @@ make
make omap3_evm_config
make
* Zoom MDK:
make omap3_zoom1_config
make
* Zoom 2:
make omap3_zoom2_config

15
doc/driver-model/migration.rst
View File

@ -66,28 +66,15 @@ CONFIG_DM_SPI / CONFIG_DM_SPI_FLASH
Board Maintainers should submit the patches for enabling DM_SPI and DM_SPI_FLASH
to move the migration with in the deadline.
No dm conversion yet::
drivers/spi/fsl_espi.c
drivers/spi/soft_spi_legacy.c
* Status: In progress
* Deadline: 2019.04
Partially converted::
drivers/spi/davinci_spi.c
drivers/spi/fsl_dspi.c
drivers/spi/kirkwood_spi.c
drivers/spi/fsl_espi.c
drivers/spi/mxc_spi.c
drivers/spi/mxs_spi.c
drivers/spi/omap3_spi.c
drivers/spi/sh_qspi.c
* Status: In progress
* Deadline: 2019.07
CONFIG_DM_PCI
-------------
Deadline: 2019.07

7
drivers/mtd/spi/spi-nor-core.c
View File

@ -1291,7 +1291,7 @@ write_err:
return ret;
}
#ifdef CONFIG_SPI_FLASH_MACRONIX
#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@ -1969,7 +1969,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
params->quad_enable = spansion_no_read_cr_quad_enable;
break;
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX
#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
case BFPT_DWORD15_QER_SR1_BIT6:
params->quad_enable = macronix_quad_enable;
break;
@ -2206,8 +2206,9 @@ static int spi_nor_init_params(struct spi_nor *nor,
if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
#ifdef CONFIG_SPI_FLASH_MACRONIX
#if defined(CONFIG_SPI_FLASH_MACRONIX) || defined(CONFIG_SPI_FLASH_ISSI)
case SNOR_MFR_MACRONIX:
case SNOR_MFR_ISSI:
params->quad_enable = macronix_quad_enable;
break;
#endif

26
drivers/spi/Kconfig
View File

@ -162,6 +162,12 @@ config ICH_SPI
access the SPI NOR flash on platforms embedding this Intel
ICH IP core.
config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver"
help
Enable support for SPI on various Marvell SoCs, such as
Kirkwood and Armada 375.
config MESON_SPIFC
bool "Amlogic Meson SPI Flash Controller driver"
depends on ARCH_MESON
@ -226,6 +232,13 @@ config NXP_FSPI
Enable the NXP FlexSPI (FSPI) driver. This driver can be used to
access the SPI NOR flash on platforms embedding this NXP IP core.
config OMAP3_SPI
bool "McSPI driver for OMAP"
help
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI). This driver be used to access SPI chips on platforms
embedding this OMAP3 McSPI IP core.
config PIC32_SPI
bool "Microchip PIC32 SPI driver"
depends on MACH_PIC32
@ -417,23 +430,10 @@ config SH_QSPI
Enable the Renesas Quad SPI controller driver. This driver can be
used on Renesas SoCs.
config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver"
help
Enable support for SPI on various Marvell SoCs, such as
Kirkwood and Armada 375.
config MXC_SPI
bool "MXC SPI Driver"
help
Enable the MXC SPI controller driver. This driver can be used
on various i.MX SoCs such as i.MX31/35/51/6/7.
config OMAP3_SPI
bool "McSPI driver for OMAP"
help
SPI master controller for OMAP24XX and later Multichannel SPI
(McSPI). This driver be used to access SPI chips on platforms
embedding this OMAP3 McSPI IP core.
endif # menu "SPI Support"

136
drivers/spi/kirkwood_spi.c
View File

@ -19,6 +19,19 @@
#endif
#include <asm/arch-mvebu/spi.h>
struct mvebu_spi_dev {
bool is_errata_50mhz_ac;
};
struct mvebu_spi_platdata {
struct kwspi_registers *spireg;
bool is_errata_50mhz_ac;
};
struct mvebu_spi_priv {
struct kwspi_registers *spireg;
};
static void _spi_cs_activate(struct kwspi_registers *reg)
{
setbits_le32(&reg->ctrl, KWSPI_CSN_ACT);
@ -94,128 +107,6 @@ static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen,
return 0;
}
#if !CONFIG_IS_ENABLED(DM_SPI)
static struct kwspi_registers *spireg =
(struct kwspi_registers *)MVEBU_SPI_BASE;
#ifdef CONFIG_ARCH_KIRKWOOD
static u32 cs_spi_mpp_back[2];
#endif
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
u32 data;
#ifdef CONFIG_ARCH_KIRKWOOD
static const u32 kwspi_mpp_config[2][2] = {
{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
};
#endif
if (!spi_cs_is_valid(bus, cs))
return NULL;
slave = spi_alloc_slave_base(bus, cs);
if (!slave)
return NULL;
writel(KWSPI_SMEMRDY, &spireg->ctrl);
/* calculate spi clock prescaller using max_hz */
data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
data = data < KWSPI_CLKPRESCL_MIN ? KWSPI_CLKPRESCL_MIN : data;
data = data > KWSPI_CLKPRESCL_MASK ? KWSPI_CLKPRESCL_MASK : data;
/* program spi clock prescaller using max_hz */
writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg);
debug("data = 0x%08x\n", data);
writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause);
writel(KWSPI_IRQMASK, &spireg->irq_mask);
#ifdef CONFIG_ARCH_KIRKWOOD
/* program mpp registers to select SPI_CSn */
kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
#endif
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
#ifdef CONFIG_ARCH_KIRKWOOD
kirkwood_mpp_conf(cs_spi_mpp_back, NULL);
#endif
free(slave);
}
__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
{
return 0;
}
int spi_claim_bus(struct spi_slave *slave)
{
return board_spi_claim_bus(slave);
}
__attribute__((weak)) void board_spi_release_bus(struct spi_slave *slave)
{
}
void spi_release_bus(struct spi_slave *slave)
{
board_spi_release_bus(slave);
}
#ifndef CONFIG_SPI_CS_IS_VALID
/*
* you can define this function board specific
* define above CONFIG in board specific config file and
* provide the function in board specific src file
*/
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && (cs == 0 || cs == 1);
}
#endif
void spi_cs_activate(struct spi_slave *slave)
{
_spi_cs_activate(spireg);
}
void spi_cs_deactivate(struct spi_slave *slave)
{
_spi_cs_deactivate(spireg);
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
return _spi_xfer(spireg, bitlen, dout, din, flags);
}
#else
/* Here now the DM part */
struct mvebu_spi_dev {
bool is_errata_50mhz_ac;
};
struct mvebu_spi_platdata {
struct kwspi_registers *spireg;
bool is_errata_50mhz_ac;
};
struct mvebu_spi_priv {
struct kwspi_registers *spireg;
};
static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
{
struct mvebu_spi_platdata *plat = dev_get_platdata(bus);
@ -409,4 +300,3 @@ U_BOOT_DRIVER(mvebu_spi) = {
.priv_auto_alloc_size = sizeof(struct mvebu_spi_priv),
.probe = mvebu_spi_probe,
};
#endif

136
drivers/spi/omap3_spi.c
View File

@ -25,16 +25,6 @@
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_AM33XX) || defined(CONFIG_AM43XX)
#define OMAP3_MCSPI1_BASE 0x48030100
#define OMAP3_MCSPI2_BASE 0x481A0100
#else
#define OMAP3_MCSPI1_BASE 0x48098000
#define OMAP3_MCSPI2_BASE 0x4809A000
#define OMAP3_MCSPI3_BASE 0x480B8000
#define OMAP3_MCSPI4_BASE 0x480BA000
#endif
#define OMAP4_MCSPI_REG_OFFSET 0x100
struct omap2_mcspi_platform_config {
@ -109,9 +99,6 @@ struct mcspi {
};
struct omap3_spi_priv {
#if !CONFIG_IS_ENABLED(DM_SPI)
struct spi_slave slave;
#endif
struct mcspi *regs;
unsigned int cs;
unsigned int freq;
@ -455,128 +442,6 @@ static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv)
writel(conf, &priv->regs->modulctrl);
}
#if !CONFIG_IS_ENABLED(DM_SPI)
static inline struct omap3_spi_priv *to_omap3_spi(struct spi_slave *slave)
{
return container_of(slave, struct omap3_spi_priv, slave);
}
void spi_free_slave(struct spi_slave *slave)
{
struct omap3_spi_priv *priv = to_omap3_spi(slave);
free(priv);
}
int spi_claim_bus(struct spi_slave *slave)
{
struct omap3_spi_priv *priv = to_omap3_spi(slave);
spi_reset(priv->regs);
_omap3_spi_claim_bus(priv);
_omap3_spi_set_wordlen(priv);
_omap3_spi_set_mode(priv);
_omap3_spi_set_speed(priv);
return 0;
}
void spi_release_bus(struct spi_slave *slave)
{
struct omap3_spi_priv *priv = to_omap3_spi(slave);
writel(OMAP3_MCSPI_MODULCTRL_MS, &priv->regs->modulctrl);
}
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct omap3_spi_priv *priv;
struct mcspi *regs;
/*
* OMAP3 McSPI (MultiChannel SPI) has 4 busses (modules)
* with different number of chip selects (CS, channels):
* McSPI1 has 4 CS (bus 0, cs 0 - 3)
* McSPI2 has 2 CS (bus 1, cs 0 - 1)
* McSPI3 has 2 CS (bus 2, cs 0 - 1)
* McSPI4 has 1 CS (bus 3, cs 0)
*/
switch (bus) {
case 0:
regs = (struct mcspi *)OMAP3_MCSPI1_BASE;
break;
#ifdef OMAP3_MCSPI2_BASE
case 1:
regs = (struct mcspi *)OMAP3_MCSPI2_BASE;
break;
#endif
#ifdef OMAP3_MCSPI3_BASE
case 2:
regs = (struct mcspi *)OMAP3_MCSPI3_BASE;
break;
#endif
#ifdef OMAP3_MCSPI4_BASE
case 3:
regs = (struct mcspi *)OMAP3_MCSPI4_BASE;
break;
#endif
default:
printf("SPI error: unsupported bus %i. Supported busses 0 - 3\n", bus);
return NULL;
}
if (((bus == 0) && (cs > 3)) ||
((bus == 1) && (cs > 1)) ||
((bus == 2) && (cs > 1)) ||
((bus == 3) && (cs > 0))) {
printf("SPI error: unsupported chip select %i on bus %i\n", cs, bus);
return NULL;
}
if (max_hz > OMAP3_MCSPI_MAX_FREQ) {
printf("SPI error: unsupported frequency %i Hz. Max frequency is 48 MHz\n",
max_hz);
return NULL;
}
if (mode > SPI_MODE_3) {
printf("SPI error: unsupported SPI mode %i\n", mode);
return NULL;
}
priv = spi_alloc_slave(struct omap3_spi_priv, bus, cs);
if (!priv) {
printf("SPI error: malloc of SPI structure failed\n");
return NULL;
}
priv->regs = regs;
priv->cs = cs;
priv->freq = max_hz;
priv->mode = mode;
priv->wordlen = priv->slave.wordlen;
#if 0
/* Please migrate to DM_SPI support for this feature. */
priv->pin_dir = MCSPI_PINDIR_D0_OUT_D1_IN;
#endif
return &priv->slave;
}
int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)
{
struct omap3_spi_priv *priv = to_omap3_spi(slave);
return _spi_xfer(priv, bitlen, dout, din, flags);
}
#else
static int omap3_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev->parent;
@ -701,4 +566,3 @@ U_BOOT_DRIVER(omap3_spi) = {
.ops = &omap3_spi_ops,
.priv_auto_alloc_size = sizeof(struct omap3_spi_priv),
};
#endif

48
drivers/spi/soft_spi.c
View File

@ -61,10 +61,12 @@ static int soft_spi_sda(struct udevice *dev, int bit)
static int soft_spi_cs_activate(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
struct soft_spi_priv *priv = dev_get_priv(bus);
struct soft_spi_platdata *plat = dev_get_platdata(bus);
int cidle = !!(priv->mode & SPI_CPOL);
dm_gpio_set_value(&plat->cs, 0);
dm_gpio_set_value(&plat->sclk, 0);
dm_gpio_set_value(&plat->sclk, cidle); /* to idle */
dm_gpio_set_value(&plat->cs, 1);
return 0;
@ -82,11 +84,14 @@ static int soft_spi_cs_deactivate(struct udevice *dev)
static int soft_spi_claim_bus(struct udevice *dev)
{
struct udevice *bus = dev_get_parent(dev);
struct soft_spi_priv *priv = dev_get_priv(bus);
int cidle = !!(priv->mode & SPI_CPOL);
/*
* Make sure the SPI clock is in idle state as defined for
* this slave.
*/
return soft_spi_scl(dev, 0);
return soft_spi_scl(dev, cidle);
}
static int soft_spi_release_bus(struct udevice *dev)
@ -117,7 +122,8 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
uchar tmpdout = 0;
const u8 *txd = dout;
u8 *rxd = din;
int cpha = priv->mode & SPI_CPHA;
int cpha = !!(priv->mode & SPI_CPHA);
int cidle = !!(priv->mode & SPI_CPOL);
unsigned int j;
debug("spi_xfer: slave %s:%s dout %08X din %08X bitlen %u\n",
@ -143,22 +149,42 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
tmpdin = 0;
}
if (!cpha)
soft_spi_scl(dev, 0);
/*
* CPOL 0: idle is low (0), active is high (1)
* CPOL 1: idle is high (1), active is low (0)
*/
/*
* drive bit
* CPHA 1: CLK from idle to active
*/
if (cpha)
soft_spi_scl(dev, !cidle);
if ((plat->flags & SPI_MASTER_NO_TX) == 0)
soft_spi_sda(dev, !!(tmpdout & 0x80));
udelay(plat->spi_delay_us);
if (cpha)
soft_spi_scl(dev, 0);
/*
* sample bit
* CPHA 0: CLK from idle to active
* CPHA 1: CLK from active to idle
*/
if (!cpha)
soft_spi_scl(dev, !cidle);
else
soft_spi_scl(dev, 1);
soft_spi_scl(dev, cidle);
tmpdin <<= 1;
if ((plat->flags & SPI_MASTER_NO_RX) == 0)
tmpdin |= dm_gpio_get_value(&plat->miso);
tmpdout <<= 1;
udelay(plat->spi_delay_us);
if (cpha)
soft_spi_scl(dev, 1);
/*
* drive bit
* CPHA 0: CLK from active to idle
*/
if (!cpha)
soft_spi_scl(dev, cidle);
}
/*
* If the number of bits isn't a multiple of 8, shift the last
@ -179,7 +205,7 @@ static int soft_spi_xfer(struct udevice *dev, unsigned int bitlen,
static int soft_spi_set_speed(struct udevice *dev, unsigned int speed)
{
/* Accept any speed */
/* Ignore any speed settings. Speed is implemented via "spi-delay-us" */
return 0;
}

475
include/configs/bav335x.h
View File

@ -1,475 +0,0 @@
/*
* bav335x.h
*
* Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __CONFIG_BAV335X_H
#define __CONFIG_BAV335X_H
#include <configs/ti_am335x_common.h>
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM
/* Clock Defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#ifdef CONFIG_MTD_RAW_NAND
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${fdtaddr} u-boot-spl-os; " \
"nand read ${loadaddr} kernel; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
#else
#define NANDARGS ""
#endif
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"boot_fdt=try\0" \
"bootpart=0:2\0" \
"bootdir=\0" \
"fdtdir=/dtbs\0" \
"bootfile=zImage\0" \
"fdtfile=undefined\0" \
"console=ttyO0,115200n8\0" \
"loadaddr=0x82000000\0" \
"fdtaddr=0x88000000\0" \
"rdaddr=0x88080000\0" \
"initrd_high=0xffffffff\0" \
"fdt_high=0xffffffff\0" \
"partitions=" \
"uuid_disk=${uuid_gpt_disk};" \
"name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
"optargs=\0" \
"cmdline=\0" \
"mmcdev=0\0" \
"mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
"mmcrootfstype=ext4 rootwait fixrtc\0" \
"rootpath=/export/rootfs\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \
"ramroot=/dev/ram0 rw\0" \
"ramrootfstype=ext2\0" \
"mmcargs=setenv bootargs console=${console} ${optargs} " \
"root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \
"server_ip=192.168.1.100\0" \
"gw_ip=192.168.1.1\0" \
"netmask=255.255.255.0\0" \
"hostname=\0" \
"device=eth0\0" \
"autoconf=off\0" \
"root_dir=/home/userid/targetNFS\0" \
"nfs_options=,vers=3\0" \
"nfsrootfstype=ext4 rootwait fixrtc\0" \
"nfsargs=setenv bootargs console=${console} ${optargs} " \
"root=/dev/nfs rw rootfstype=${nfsrootfstype} " \
"nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \
"netargs=setenv bootargs console=${console} " \
"${optargs} root=/dev/nfs " \
"nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \
"bootenv=uEnv.txt\0" \
"script=boot.scr\0" \
"scriptfile=${script}\0" \
"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \
"bootscript=echo Running bootscript from mmc${bootpart} ...; " \
"source ${loadaddr}\0" \
"loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t -r $loadaddr $filesize\0" \
"ramargs=setenv bootargs console=${console} " \
"${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \
"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadrd=load mmc ${bootpart} ${rdaddr} " \
"${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \
"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \
"load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"gpio set 54;" \
"setenv bootpart ${mmcdev}:1; " \
"if test -e mmc ${bootpart} /etc/fstab; then " \
"setenv mmcpart 1;" \
"fi; " \
"echo Checking for: /uEnv.txt ...;" \
"if test -e mmc ${bootpart} /uEnv.txt; then " \
"if run loadbootenv; then " \
"gpio set 55;" \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"echo Checking if uenvcmd is set ...;" \
"if test -n ${uenvcmd}; then " \
"gpio set 56; " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"echo Checking if client_ip is set ...;" \
"if test -n ${client_ip}; then " \
"if test -n ${dtb}; then " \
"setenv fdtfile ${dtb};" \
"echo using ${fdtfile} ...;" \
"fi;" \
"gpio set 56; " \
"if test -n ${uname_r}; then " \
"echo Running nfsboot_uname_r ...;" \
"run nfsboot_uname_r;" \
"fi;" \
"echo Running nfsboot ...;" \
"run nfsboot;" \
"fi;" \
"fi; " \
"echo Checking for: /${script} ...;" \
"if test -e mmc ${bootpart} /${script}; then " \
"gpio set 55;" \
"setenv scriptfile ${script};" \
"run loadbootscript;" \
"echo Loaded script from ${scriptfile};" \
"gpio set 56; " \
"run bootscript;" \
"fi; " \
"echo Checking for: /boot/${script} ...;" \
"if test -e mmc ${bootpart} /boot/${script}; then " \
"gpio set 55;" \
"setenv scriptfile /boot/${script};" \
"run loadbootscript;" \
"echo Loaded script from ${scriptfile};" \
"gpio set 56; " \
"run bootscript;" \
"fi; " \
"echo Checking for: /boot/uEnv.txt ...;" \
"for i in 1 2 3 4 5 6 7 ; do " \
"setenv mmcpart ${i};" \
"setenv bootpart ${mmcdev}:${mmcpart};" \
"if test -e mmc ${bootpart} /boot/uEnv.txt; then " \
"gpio set 55;" \
"load mmc ${bootpart} ${loadaddr} " \
"/boot/uEnv.txt;" \
"env import -t ${loadaddr} ${filesize};" \
"echo Loaded environment from /boot/uEnv.txt;" \
"if test -n ${dtb}; then " \
"setenv fdtfile ${dtb};" \
"echo Using: dtb=${fdtfile} ...;" \
"fi;" \
"echo Checking if uname_r is set in " \
"/boot/uEnv.txt...;" \
"if test -n ${uname_r}; then " \
"gpio set 56; " \
"echo Running uname_boot ...;" \
"setenv mmcroot /dev/mmcblk${mmcdev}" \
"p${mmcpart} ro;" \
"run uname_boot;" \
"fi;" \
"fi;" \
"done;" \
"fi;\0" \
"netboot=echo Booting from network ...; " \
"setenv autoload no; " \
"dhcp; " \
"tftp ${loadaddr} ${bootfile}; " \
"tftp ${fdtaddr} ${fdtfile}; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nfsboot=echo Booting from ${server_ip} ...; " \
"setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
"setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
":${device}:${autoconf}; " \
"setenv autoload no; " \
"setenv serverip ${server_ip}; " \
"setenv ipaddr ${client_ip}; " \
"tftp ${loadaddr} ${bootfile}; " \
"tftp ${fdtaddr} dtbs/${fdtfile}; " \
"run nfsargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \
"setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \
"setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \
":${device}:${autoconf}; " \
"setenv autoload no; " \
"setenv serverip ${server_ip}; " \
"setenv ipaddr ${client_ip}; " \
"tftp ${loadaddr} vmlinuz-${uname_r}; " \
"tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \
"run nfsargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"ramboot=echo Booting from ramdisk ...; " \
"run ramargs; " \
"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
"findfdt="\
"if test $board_rev = B; then " \
"setenv fdtfile birdland_bav335b.dtb; " \
"setenv fdtbase am335x-boneblack; fi; " \
"if test $board_rev = A; then " \
"setenv fdtfile birdland_bav335a.dtb; " \
"setenv fdtbase am335x-boneblack; fi; " \
"if test $fdtfile = undefined; then " \
"echo WARNING: Could not determine device tree to use; fi; \0" \
"uname_boot="\
"setenv bootdir /boot; " \
"setenv bootfile vmlinuz-${uname_r}; " \
"if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \
"echo loading ${bootdir}/${bootfile} ...; "\
"run loadimage;" \
"setenv fdtdir /boot/dtbs/${uname_r}; " \
"if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \
"run loadfdt;" \
"else " \
"setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \
"if test -e mmc ${bootpart} ${fdtdir}/" \
"${fdtfile}; then " \
"run loadfdt;" \
"else " \
"setenv fdtdir /boot/dtb-${uname_r}; " \
"if test -e mmc ${bootpart} ${fdtdir}" \
"/${fdtfile}; then " \
"run loadfdt;" \
"else " \
"setenv fdtdir /boot/dtbs; " \
"if test -e mmc ${bootpart} ${fdtdir}" \
"/${fdtfile}; then " \
"run loadfdt;" \
"else " \
"echo; echo unable to find " \
"[${fdtfile}] " \
"did you name it correctly?" \
"echo booting fallback " \
"[/boot/dtbs/" \
"${uname_r}" \
"/${fdtbase}.dtb]...;" \
"setenv fdtdir /boot/dtbs/" \
"${uname_r}; " \
"setenv fdtfile " \
"${fdtbase}.dtb; " \
"run loadfdt;" \
"fi;" \
"fi;" \
"fi;" \
"fi;" \
"fi; " \
"setenv rdfile initrd.img-${uname_r}; " \
"if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \
"echo loading ${bootdir}/${rdfile} ...; "\
"run loadrd;" \
"if test -n ${uuid}; then " \
"setenv mmcroot UUID=${uuid} ro;" \
"fi;" \
"run mmcargs;" \
"echo debug: [${bootargs}] ... ;" \
"echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \
"${fdtaddr}] ... ;" \
"bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \
"else " \
"run mmcargs;" \
"echo debug: [${bootargs}] ... ;" \
"echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \
"bootz ${loadaddr} - ${fdtaddr}; " \
"fi;" \
"fi;\0" \
NANDARGS \
DFUARGS
#endif
#define CONFIG_BOOTCOMMAND \
"gpio set 53; " \
"i2c mw 0x24 1 0x3e; " \
"run findfdt; " \
"setenv mmcdev 0; " \
"setenv bootpart 0:1; " \
"run mmcboot;" \
"gpio clear 56; " \
"gpio clear 55; " \
"gpio clear 54; " \
"setenv mmcdev 1; " \
"setenv bootpart 1:1; " \
"run mmcboot;"
/* NS16550 Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* PMIC support */
#define CONFIG_POWER_TPS65217
#define CONFIG_POWER_TPS65910
/* SPL */
#ifndef CONFIG_NOR_BOOT
/* Bootcount using the RTC block */
#define CONFIG_SYS_BOOTCOUNT_BE
/* USB gadget RNDIS */
#endif
#ifdef CONFIG_MTD_RAW_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { \
2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000
#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
/* NAND: SPL related configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */
#endif
#endif /* !CONFIG_MTD_RAW_NAND */
/*
* For NOR boot, we must set this to the start of where NOR is mapped
* in memory.
*/
/*
* USB configuration. We enable MUSB support, both for host and for
* gadget. We set USB0 as peripheral and USB1 as host, based on the
* board schematic and physical port wired to each. Then for host we
* add mass storage support and for gadget we add both RNDIS ethernet
* and DFU.
*/
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER)
/* disable host part of MUSB in SPL */
/* disable EFI partitions and partition UUID support */
#endif
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
#define DFU_ALT_INFO_MMC \
"dfu_alt_info_mmc=" \
"boot part 0 1;" \
"rootfs part 0 2;" \
"MLO fat 0 1;" \
"MLO.raw raw 0x100 0x100;" \
"u-boot.img.raw raw 0x300 0x400;" \
"spl-os-args.raw raw 0x80 0x80;" \
"spl-os-image.raw raw 0x900 0x2000;" \
"spl-os-args fat 0 1;" \
"spl-os-image fat 0 1;" \
"u-boot.img fat 0 1;" \
"uEnv.txt fat 0 1\0"
#ifdef CONFIG_MTD_RAW_NAND
#define DFU_ALT_INFO_NAND \
"dfu_alt_info_nand=" \
"SPL part 0 1;" \
"SPL.backup1 part 0 2;" \
"SPL.backup2 part 0 3;" \
"SPL.backup3 part 0 4;" \
"u-boot part 0 5;" \
"u-boot-spl-os part 0 6;" \
"kernel part 0 8;" \
"rootfs part 0 9\0"
#else
#define DFU_ALT_INFO_NAND ""
#endif
#define DFU_ALT_INFO_RAM \
"dfu_alt_info_ram=" \
"kernel ram 0x80200000 0xD80000;" \
"fdt ram 0x80F80000 0x80000;" \
"ramdisk ram 0x81000000 0x4000000\0"
#define DFUARGS \
"dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \
DFU_ALT_INFO_MMC \
DFU_ALT_INFO_RAM \
DFU_ALT_INFO_NAND
#endif
/*
* Default to using SPI for environment, etc.
* 0x000000 - 0x020000 : SPL (128KiB)
* 0x020000 - 0x0A0000 : U-Boot (512KiB)
* 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
* 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
* 0x0E0000 - 0x442000 : Linux Kernel
* 0x442000 - 0x800000 : Userland
*/
#if defined(CONFIG_SPI_BOOT)
/* SPL related */
#elif defined(CONFIG_EMMC_BOOT)
#define CONFIG_SYS_MMC_ENV_DEV 1
#define CONFIG_SYS_MMC_ENV_PART 2
#endif
/* SPI flash. */
/* Network. */
/*
* NOR Size = 16 MiB
* Number of Sectors/Blocks = 128
* Sector Size = 128 KiB
* Word length = 16 bits
* Default layout:
* 0x000000 - 0x07FFFF : U-Boot (512 KiB)
* 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
* 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
* 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
* 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
*/
#if defined(CONFIG_NOR)
#define CONFIG_SYS_MAX_FLASH_SECT 128
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BASE (0x08000000)
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_SYS_FLASH_SIZE 0x01000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/* Reduce SPL size by removing unlikey targets */
#endif /* NOR support */
#endif /* ! __CONFIG_AM335X_EVM_H */

249
include/configs/cm_t35.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011 CompuLab, Ltd.
* Mike Rapoport <mike@compulab.co.il>
* Igor Grinberg <grinberg@compulab.co.il>
*
* Based on omap3_beagle.h
* (C) Copyright 2006-2008
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
*
* Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_CACHELINE_SIZE 64
/*
* High Level Configuration Options
*/
#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
/* Clock Defines */
#define V_OSCK 26000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK >> 1)
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SERIAL_TAG
/*
* Size of malloc() pool
*/
/* Sector */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/*
* Hardware drivers
*/
/*
* NS16550 Configuration
*/
#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
/*
* select serial console configuration
*/
#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
115200}
/* USB device configuration */
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
/* commands to include */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
#define CONFIG_I2C_MULTI_BUS
/*
* TWL4030
*/
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"usbtty=cdc_acm\0" \
"console=ttyO2,115200n8\0" \
"mpurate=500\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"nandroot=/dev/mtdblock4 rw\0" \
"nandrootfstype=ubifs\0" \
"mmcargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 2a0000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else run nandboot; " \
"fi; " \
"fi; " \
"else run nandboot; fi"
/*
* Miscellaneous configurable options
*/
#define CONFIG_TIMESTAMP
#define CONFIG_SYS_AUTOLOAD "no"
/* works on */
#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
/* load address */
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
/* Status LED */
#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */
#define CONFIG_SPLASHIMAGE_GUARD
/* Display Configuration */
#define LCD_BPP LCD_COLOR16
#define CONFIG_SPLASH_SCREEN
#define CONFIG_SPLASH_SOURCE
#define CONFIG_BMP_16BPP
#define CONFIG_SCF0403_LCD
/* Defines for SPL */
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
/*
* Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
* SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
*/
#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12 }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
CONFIG_SPL_TEXT_BASE)
/*
* Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
* older x-loader implementations. And move the BSS area so that it
* doesn't overlap with TEXT_BASE.
*/
#define CONFIG_SPL_BSS_START_ADDR 0x80100000
#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
#endif /* __CONFIG_H */

120
include/configs/cm_t54.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Config file for Compulab CM-T54 board
*
* Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
*
* Author: Dmitry Lifshitz <lifshitz@compulab.co.il>
*/
#ifndef __CONFIG_CM_T54_H
#define __CONFIG_CM_T54_H
#define CONFIG_CM_T54
#define CONFIG_DRAM_2G
#define PARTS_DEFAULT
#include <configs/ti_omap5_common.h>
/* EEPROM related defines */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_BUS 0
/* Enable SD/MMC CD and WP GPIOs */
#define OMAP_HSMMC_USE_GPIO
/* UART setup */
#define CONFIG_SYS_NS16550_COM4 UART4_BASE
/* MMC ENV related defines */
#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */
#define CONFIG_SYS_MMC_ENV_PART 0
/* Enhance our eMMC support / experience. */
#define CONFIG_HSMMC2_8BIT
/* SATA Boot related defines */
#define CONFIG_SPL_SATA_BOOT_DEVICE 0
#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
/* USB UHH support options */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */
#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 83 /* HSIC3 ETH #RESET */
/* Enabled commands */
/* EEPROM */
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 256
/* USB Networking options */
/*
* Miscellaneous configurable options
*/
#undef CONFIG_SYS_AUTOLOAD
#undef CONFIG_EXTRA_ENV_SETTINGS
#undef CONFIG_BOOTCOMMAND
#define CONFIG_SYS_AUTOLOAD "no"
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"baudrate=115200\0" \
"bootdelay=3\0" \
"autoload=no\0" \
"bootscr=bootscr.img\0" \
"fdtfile=omap5-sbc-t54.dtb\0" \
"kernel=zImage-cm-t54\0" \
"ramdisk=ramdisk-cm-t54.img\0" \
"console=ttyO3\0" \
"ramdisksize=16384\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk1p2\0" \
"mmcargs=setenv bootargs console=${console} " \
"root=${mmcroot} rw rootwait\0" \
"ramroot=/dev/ram0\0" \
"ramargs=setenv bootargs console=${console} " \
"root=${ramroot} ramdisk_size=${ramdisksize} rw\0" \
"mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \
"mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \
"mmcloadramdisk=load mmc ${mmcdev} ${rdaddr} ${ramdisk}\0" \
"mmcloadbootscript=load mmc ${mmcdev} ${loadaddr} ${bootsrc}\0" \
"mmcbootscript=echo Running bootscript from mmc${mmcdev}...; " \
"source ${loadaddr}\0" \
"mmcbootlinux=echo Booting from mmc${mmcdev} ...; " \
"bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
"mmcboot=if mmc dev ${mmcdev} && mmc rescan; then " \
"if run mmcloadbootscript; " \
"then run mmcbootscript; " \
"fi; " \
"if run mmcloadkernel; then " \
"if run mmcloadfdt; then " \
"if run mmcloadramdisk; then " \
"run ramargs; " \
"run mmcbootlinux; " \
"fi; " \
"run mmcargs; " \
"setenv rdaddr - ; " \
"run mmcbootlinux; " \
"fi; " \
"fi; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"bootcmd=run mmcboot || setenv mmcdev 1; setenv mmcroot /dev/mmcblk0p2; run mmcboot;"
#endif /* __CONFIG_CM_T54_H */

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include/configs/duovero.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright: 2013
* Gumstix, Inc - http://www.gumstix.com
* Maintainer: Ash Charles <ash@gumstix.com>
*
* Configuration settings for the Gumstix DuoVero board.
* See omap4_common.h for OMAP4 common part
*/
#ifndef __CONFIG_DUOVERO_H
#define __CONFIG_DUOVERO_H
/*
* High Level Configuration Options
*/
#define CONFIG_DUOVERO
#define CONFIG_MACH_TYPE MACH_TYPE_DUOVERO
#include <configs/ti_omap4_common.h>
#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
/* USB UHH support options */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62
#define CONFIG_SYS_ENABLE_PADS_ALL
/* GPIO */
/* ENV related config options */
#endif /* __CONFIG_DUOVERO_H */

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include/configs/mx31pdk.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
*
* (C) Copyright 2004
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Kshitij Gupta <kshitij@ti.com>
*
* Configuration settings for the Freescale i.MX31 PDK board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
#define CONFIG_SPL_MAX_SIZE 2048
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
/* PMIC Controller */
#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 2
#define CONFIG_FSL_PMIC_CLK 1000000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
#define CONFIG_RTC_MC13XXX
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootargs_base=setenv bootargs console=ttymxc0,115200\0" \
"bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
"bootcmd=run bootcmd_net\0" \
"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \
"tftpboot 0x81000000 uImage-mx31; bootm\0" \
"prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \
"nand erase 0x0 0x40000; " \
"nand write 0x81000000 0x0 0x40000\0"
/*
* Miscellaneous configurable options
*/
/* memtest works on */
/* default load address */
#define CONFIG_SYS_LOAD_ADDR 0x81000000
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE)
/*
* environment organization
*/
/*
* NAND driver
*/
#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
/* NAND configuration for the NAND_SPL */
/* Start copying real U-Boot from the second page */
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800
/* Load U-Boot to this address */
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP 0x074B0BF5
#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
PLL_MFN(12))
#define ESDMISC_MDDR_SETUP 0x00000004
#define ESDMISC_MDDR_RESET_DL 0x0000000c
#define ESDCFG0_MDDR_SETUP 0x006ac73a
#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
ESDCTL_DSIZ(2) | ESDCTL_BL(1))
#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
#define ESDCTL_RW ESDCTL_SETTINGS
#endif /* __CONFIG_H */

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include/configs/omap3_cairo.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the QUIPOS Cairo board.
*
* Copyright (C) DENX GmbH
*
* Author :
* Albert ARIBAUD <albert.aribaud@3adev.fr>
*
* Derived from EVM code by
* Manikandan Pillai <mani.pillai@ti.com>
* Itself derived from Beagle Board and 3430 SDP code by
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* Also derived from include/configs/omap3_beagle.h
*/
#ifndef __OMAP3_CAIRO_CONFIG_H
#define __OMAP3_CAIRO_CONFIG_H
/*
* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
* 64 bytes before this address should be set aside for u-boot.img's
* header. That is 0x800FFFC0--0x80100000 should not be used for any
* other needs. We use this rather than the inherited defines from
* ti_armv7_common.h for backwards compatibility.
*/
#define CONFIG_SPL_BSS_START_ADDR 0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */
#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#include <configs/ti_omap3_common.h>
#define CONFIG_REVISION_TAG 1
#define CONFIG_ENV_OVERWRITE
/* Enable Multi Bus support for I2C */
#define CONFIG_I2C_MULTI_BUS 1
/* Probe all devices */
#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} }
/*
* TWL4030
*/
/*
* Board NAND Info.
*/
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
/* devices */
#define CONFIG_EXTRA_ENV_SETTINGS \
"machid=ffffffff\0" \
"fdt_high=0x87000000\0" \
"baudrate=115200\0" \
"fec_addr=00:50:C2:7E:90:F0\0" \
"netmask=255.255.255.0\0" \
"ipaddr=192.168.2.9\0" \
"gateway=192.168.2.1\0" \
"serverip=192.168.2.10\0" \
"nfshost=192.168.2.10\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"bootargs_mmc_ramdisk=mem=128M " \
"console=ttyO1,115200n8 " \
"root=/dev/ram0 rw " \
"initrd=0x81600000,16M " \
"mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \
"omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \
"mmcboot=mmc init; " \
"fatload mmc 0 0x80000000 uImage; " \
"fatload mmc 0 0x81600000 ramdisk.gz; " \
"setenv bootargs ${bootargs_mmc_ramdisk}; " \
"bootm 0x80000000\0" \
"bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \
"root=/dev/nfs " \
"nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \
"mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \
"omap_vout.vid1_static_vrfb_alloc=y\0" \
"boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \
"bootm 0x80000000\0" \
"bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \
"root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \
"omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \
"omapfb.rotate_type=1\0" \
"boot_nand=nand read.i 0x80000000 280000 300000; setenv " \
"bootargs ${bootargs_nand}; bootm 0x80000000\0" \
"ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
"i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \
"ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \
"mw 60 09 00 1; i2c mw 60 06 10 1\0" \
"ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
"i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \
"ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \
"i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \
"i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \
"flash_xloader=mw.b 0x81600000 0xff 0x20000; " \
"nand erase 0 20000; " \
"fatload mmc 0 0x81600000 MLO; " \
"nandecc hw; " \
"nand write.i 0x81600000 0 20000;\0" \
"flash_uboot=mw.b 0x81600000 0xff 0x40000; " \
"nand erase 80000 40000; " \
"fatload mmc 0 0x81600000 u-boot.bin; " \
"nandecc sw; " \
"nand write.i 0x81600000 80000 40000;\0" \
"flash_kernel=mw.b 0x81600000 0xff 0x300000; " \
"nand erase 280000 300000; " \
"fatload mmc 0 0x81600000 uImage; " \
"nandecc sw; " \
"nand write.i 0x81600000 280000 300000;\0" \
"flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \
"nandecc sw; " \
"nand write.jffs2 0x680000 0xFF ${filesize}; " \
"nand erase 680000 ${filesize}; " \
"nand write.jffs2 81600000 680000 ${filesize};\0" \
"flash_scrub=nand scrub; " \
"run flash_xloader; " \
"run flash_uboot; " \
"run flash_kernel; " \
"run flash_rootfs;\0" \
"flash_all=run ledred; " \
"nand erase.chip; " \
"run ledorange; " \
"run flash_xloader; " \
"run flash_uboot; " \
"run flash_kernel; " \
"run flash_rootfs; " \
"run ledgreen; " \
"run boot_nand; \0" \
#define CONFIG_BOOTCOMMAND \
"if fatload mmc 0 0x81600000 MLO; then run flash_all; " \
"else run boot_nand; fi"
/*
* OMAP3 has 12 GP timers, they can be driven by the system clock
* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
* This rate is divided by a local divisor.
*/
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/* Defines for SPL */
/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 3
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#endif
/* env defaults */
#define CONFIG_BOOTFILE "uImage"
/* Provide the MACH_TYPE value the vendor kernel requires */
#define CONFIG_MACH_TYPE 3063
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#endif /* __OMAP3_CAIRO_CONFIG_H */

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include/configs/omap3_overo.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuration settings for the Gumstix Overo board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <configs/ti_omap3_common.h>
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
* area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
*/
/* call misc_init_r */
/* pass the revision tag */
#define CONFIG_REVISION_TAG
/* override size of malloc() pool */
#undef CONFIG_SYS_MALLOC_LEN
/* Shift 128 << 15 provides 4 MiB heap to support UBI commands.
* Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15))
/* I2C Support */
/* TWL4030 LED */
/* USB EHCI */
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183
/* commands to include */
#ifdef CONFIG_MTD_RAW_NAND
/* NAND block size is 128 KiB. Synchronize these values with
* overo_nand_partitions in mach-omap2/board-overo.c in Linux:
* xloader 4 * NAND_BLOCK_SIZE = 512 KiB
* uboot 14 * NAND_BLOCK_SIZE = 1792 KiB
* uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB
* linux 64 * NAND_BLOCK_SIZE = 8 MiB
* rootfs remainder
*/
#endif /* CONFIG_MTD_RAW_NAND */
/* Board NAND Info. */
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"usbtty=cdc_acm\0" \
"console=ttyO2,115200n8\0" \
"mpurate=auto\0" \
"optargs=\0" \
"vram=12M\0" \
"dvimode=1024x768MR-16@60\0" \
"defaultdisplay=dvi\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"nandroot=ubi0:rootfs ubi.mtd=4\0" \
"nandrootfstype=ubifs\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
"mpurate=${mpurate} " \
"vram=${vram} " \
"omapfb.mode=dvi:${dvimode} " \
"omapdss.def_disp=${defaultdisplay} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running boot script from mmc ...; " \
"source ${loadaddr}\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \
"mmcboot=echo Booting from mmc...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcbootfdt=echo Booting with DT from mmc ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"if nand read ${loadaddr} linux; then " \
"bootm ${loadaddr};" \
"fi;\0" \
"nanddtsboot=echo Booting from nand with DTS...; " \
"run nandargs; " \
"ubi part rootfs; "\
"ubifsmount ubi0:rootfs; "\
"run loadubifdt; "\
"run loadubizimage; "\
"bootz ${loadaddr} - ${fdtaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"fi;" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run loaduimage; then " \
"run mmcboot;" \
"fi;" \
"if run loadzimage; then " \
"if test -z \"${fdtfile}\"; then " \
"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
"fi;" \
"if run loadfdt; then " \
"run mmcbootfdt;" \
"fi;" \
"fi;" \
"fi;" \
"run nandboot; " \
"if test -z \"${fdtfile}\"; then "\
"setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \
"fi;" \
"run nanddtsboot; " \
/* memtest works on */
/* FLASH and environment organization */
#if defined(CONFIG_MTD_RAW_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/* Initial RAM setup */
#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE 0x800
/* NAND boot config */
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT 64
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
13, 14, 16, 17, 18, 19, 20, 21, 22, \
23, 24, 25, 26, 27, 28, 30, 31, 32, \
33, 34, 35, 36, 37, 38, 39, 40, 41, \
42, 44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 13
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#endif
#endif /* __CONFIG_H */

131
include/configs/omap3_zoom1.h
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@ -1,131 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006-2008
* Texas Instruments.
* Richard Woodruff <r-woodruff2@ti.com>
* Syed Mohammed Khasim <x0khasim@ti.com>
* Nishanth Menon <nm@ti.com>
*
* Configuration settings for the TI OMAP3430 Zoom MDK board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/cpu.h> /* get chip and board defs */
#include <asm/arch/omap.h>
#include <configs/ti_omap3_common.h>
/* Remove SPL boot option - we do not support that on LDP yet */
/* Generic NAND definition conflicts with debug_base */
#undef CONFIG_SYS_NAND_BASE
#define CONFIG_REVISION_TAG 1
/*
* Hardware drivers
*/
/* USB device configuration */
#define CONFIG_USB_DEVICE 1
#define CONFIG_USB_TTY 1
/* Change these to suit your needs */
#define CONFIG_USBD_VENDORID 0x0451
#define CONFIG_USBD_PRODUCTID 0x5678
#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
#define CONFIG_USBD_PRODUCT_NAME "Zoom1"
#if defined(CONFIG_CMD_NAND)
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#endif
#endif
/*
* TWL4030
*/
/*
* Board NAND Info.
*/
#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
/* to access nand at */
/* CS0 */
/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x82000000\0" \
"fdtaddr=0x80f80000\0" \
"bootfile=uImage\0" \
"fdtfile=omap3-ldp.dtb\0" \
"bootdir=/\0" \
"bootpart=0:1\0" \
"usbtty=cdc_acm\0" \
"console=ttyO2,115200n8\0" \
"mmcdev=0\0" \
"videomode=1024x768@60,vxres=1024,vyres=768\0" \
"videospec=omapfb:vram:2M,vram:4M\0" \
"mmcargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mmcblk0p2 rw " \
"rootfstype=ext3 rootwait\0" \
"nandargs=setenv bootargs console=${console} " \
"video=${videospec},mode:${videomode} " \
"root=/dev/mtdblock4 rw " \
"rootfstype=jffs2\0" \
"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source ${loadaddr}\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"mmczboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${loadaddr} 280000 400000; " \
"bootm ${loadaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else if run loadzimage; then " \
"run mmczboot; " \
"else run nandboot; " \
"fi; fi;" \
"fi; " \
"else run nandboot; fi"
/*
* Miscellaneous configurable options
*/
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
/* **** PISMO SUPPORT *** */
#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE NAND_BASE
#endif
/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
#endif /* __CONFIG_H */

166
include/configs/pengwyn.h
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@ -1,166 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* pengwyn.h
*
* Copyright (C) 2013 Lothar Felten <lothar.felten@gmail.com>
*
* based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc.
*/
#ifndef __CONFIG_PENGWYN_H
#define __CONFIG_PENGWYN_H
#include <configs/ti_am335x_common.h>
/* Clock Defines */
#define V_OSCK 24000000
#define V_SCLK V_OSCK
/* set env size */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80200000\0" \
"fdtaddr=0x80F80000\0" \
"bootpart=0:2\0" \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"fdtfile=am335x-pengwyn.dtb\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 ro\0" \
"mmcrootfstype=ext4 rootwait\0" \
"rootpath=/export/rootfs\0" \
"nfsopts=nolock\0" \
"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
"::off\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"netargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=/dev/nfs " \
"nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
"ip=dhcp\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t $loadaddr $filesize\0" \
"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
"loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"mmcloados=run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr};\0" \
"mmcboot=mmc dev ${mmcdev}; " \
"if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run loadimage; then " \
"run loadfdt;" \
"run mmcloados;" \
"fi;" \
"fi;\0" \
"netboot=echo Booting from network ...; " \
"setenv autoload no; " \
"dhcp; " \
"tftp ${loadaddr} ${bootfile}; " \
"tftp ${fdtaddr} ${fdtfile}; " \
"run netargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${fdtaddr} u-boot-spl-os; " \
"nand read ${loadaddr} kernel; " \
"bootz ${loadaddr} - ${fdtaddr}\0"
#endif
#define CONFIG_BOOTCOMMAND \
"run mmcboot;" \
"run nandboot;"
/* NS16550 Configuration: primary UART via FTDI */
#define CONFIG_SYS_NS16550_COM1 0x44e09000
/* I2C Configuration */
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_ENV_EEPROM_IS_ON_I2C
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
/* SPL */
/* NAND support */
/* NAND Configuration. */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_PAGE_SIZE 4096
#define CONFIG_SYS_NAND_OOBSIZE 224
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\
34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\
66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\
82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\
98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\
114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\
134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\
154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\
174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\
194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define CONFIG_SYS_NAND_ECCSTEPS 8
#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
/* END NAND Configuration. */
#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
/* Size must be a multiple of Nand erase size (524288 b) */
#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
#endif
/*
* USB configuration. We enable MUSB support, both for host and for
* gadget. We set USB0 as peripheral and USB1 as host, based on the
* board schematic and physical port wired to each. Then for host we
* add mass storage support.
*/
#define CONFIG_AM335X_USB0
#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
#define CONFIG_AM335X_USB1
#define CONFIG_AM335X_USB1_MODE MUSB_HOST
/* Network */
#define CONFIG_PHY_RESET 1
#endif /* ! __CONFIG_PENGWYN_H */

78
include/configs/pepper.h
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@ -1,78 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/
*/
#ifndef __CONFIG_PEPPER_H
#define __CONFIG_PEPPER_H
#include <configs/ti_am335x_common.h>
/* Clock defines */
#define V_OSCK 24000000 /* Clock output from T2 */
#define V_SCLK (V_OSCK)
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
/* Mach type */
#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER
#define CONFIG_EXTRA_ENV_SETTINGS \
DEFAULT_LINUX_BOOT_ENV \
"bootdir=/boot\0" \
"bootfile=zImage\0" \
"fdtfile=am335x-pepper.dtb\0" \
"console=ttyO0,115200n8\0" \
"optargs=\0" \
"mmcdev=0\0" \
"mmcroot=/dev/mmcblk0p2 rw\0" \
"mmcrootfstype=ext4 rootwait\0" \
"mmcargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"bootenv=uEnv.txt\0" \
"loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
"importbootenv=echo Importing environment from mmc ...; " \
"env import -t ${loadaddr} ${filesize}\0" \
"mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \
"load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \
"loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \
"uimageboot=echo Booting from mmc${mmcdev} ...; " \
"run mmcargs; " \
"bootm ${loadaddr}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
"ubiboot=echo Booting from nand (ubifs) ...; " \
"run ubiargs; run ubiload; " \
"bootz ${loadaddr} - ${fdtaddr}\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"echo SD/MMC found on device ${mmcdev};" \
"if run loadbootenv; then " \
"echo Loaded environment from ${bootenv};" \
"run importbootenv;" \
"fi;" \
"if test -n $uenvcmd; then " \
"echo Running uenvcmd ...;" \
"run uenvcmd;" \
"fi;" \
"if run mmcload; then " \
"run mmcboot;" \
"fi;" \
"if run loaduimage; then " \
"run uimageboot;" \
"fi;" \
"fi;" \
/* Serial console configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000
/* Ethernet support */
#define CONFIG_PHY_RESET_DELAY 1000
/* SPL */
#endif /* __CONFIG_PEPPER_H */

3
include/configs/siemens-am33x-common.h
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@ -68,10 +68,7 @@
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/* NS16550 Configuration */
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#endif
#define CONFIG_SYS_NS16550_CLK (48000000)
#define CONFIG_SYS_NS16550_COM1 0x44e09000
#define CONFIG_SYS_NS16550_COM4 0x481a6000

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