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Merge branch 'master' of git://git.denx.de/u-boot-socfpga

Browse Source 
- Assorted fixes
This commit is contained in:
Tom Rini 2019-11-22 10:41:46 -05:00
commit 47b48fe186
15 changed files with 54 additions and 16 deletions
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5
arch/arm/dts/socfpga_stratix10_socdk.dts
View File

@ -9,6 +9,7 @@
model = "SoCFPGA Stratix 10 SoCDK";
aliases {
ethernet0 = &gmac0;
i2c0 = &i2c1;
serial0 = &uart0;
};
@ -36,6 +37,8 @@
};
memory {
#address-cells = <2>;
#size-cells = <2>;
device_type = "memory";
/* 4GB */
reg = <0 0x00000000 0 0x80000000>,
@ -71,7 +74,7 @@
rxd2-skew-ps = <420>; /* 0ps */
rxd3-skew-ps = <420>; /* 0ps */
txen-skew-ps = <0>; /* -420ps */
txc-skew-ps = <1860>; /* 960ps */
txc-skew-ps = <900>; /* 0ps */
rxdv-skew-ps = <420>; /* 0ps */
rxc-skew-ps = <1680>; /* 780ps */
};

6
arch/arm/mach-socfpga/include/mach/misc.h
View File

@ -3,8 +3,8 @@
* Copyright (C) 2016-2017 Intel Corporation
*/
#ifndef _MISC_H_
#define _MISC_H_
#ifndef _SOCFPGA_MISC_H_
#define _SOCFPGA_MISC_H_
#include <asm/sections.h>
@ -42,4 +42,4 @@ void socfpga_sdram_remap_zero(void);
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
#endif /* _MISC_H_ */
#endif /* _SOCFPGA_MISC_H_ */

2
configs/socfpga_arria5_defconfig
View File

@ -29,7 +29,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_cyclone5_defconfig
View File

@ -29,7 +29,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_de0_nano_soc_defconfig
View File

@ -30,7 +30,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_is1_defconfig
View File

@ -29,7 +29,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_mcvevk_defconfig
View File

@ -30,7 +30,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_sockit_defconfig
View File

@ -29,7 +29,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_socrates_defconfig
View File

@ -30,7 +30,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

2
configs/socfpga_sr1500_defconfig
View File

@ -32,7 +32,7 @@ CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set

1
configs/socfpga_stratix10_defconfig
View File

@ -57,3 +57,4 @@ CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
CONFIG_USB_STORAGE=y
# CONFIG_SPL_USE_TINY_PRINTF is not set

2
drivers/ddr/altera/sdram_gen5.c
View File

@ -626,7 +626,7 @@ static int altera_gen5_sdram_get_info(struct udevice *dev,
return 0;
}
static struct ram_ops altera_gen5_sdram_ops = {
static const struct ram_ops altera_gen5_sdram_ops = {
.get_info = altera_gen5_sdram_get_info,
};

21
drivers/spi/cadence_qspi.c
View File

@ -5,6 +5,7 @@
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
struct cadence_spi_priv *priv = dev_get_priv(bus);
cadence_qspi_apb_config_baudrate_div(priv->regbase,
CONFIG_CQSPI_REF_CLK, hz);
plat->ref_clk_hz, hz);
/* Reconfigure delay timing if speed is changed. */
cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz,
cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz,
plat->tshsl_ns, plat->tsd2d_ns,
plat->tchsh_ns, plat->tslch_ns);
@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
{
struct cadence_spi_platdata *plat = bus->platdata;
ofnode subnode;
struct clk clk;
int ret;
plat->regbase = (void *)devfdt_get_addr_index(bus, 0);
plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1);
@ -325,6 +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus)
plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20);
plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20);
ret = clk_get_by_index(bus, 0, &clk);
if (ret) {
#ifdef CONFIG_CQSPI_REF_CLK
plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK;
#else
return ret;
#endif
} else {
plat->ref_clk_hz = clk_get_rate(&clk);
clk_free(&clk);
if (IS_ERR_VALUE(plat->ref_clk_hz))
return plat->ref_clk_hz;
}
debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n",
__func__, plat->regbase, plat->ahbbase, plat->max_hz,
plat->page_size);

1
drivers/spi/cadence_qspi.h
View File

@ -16,6 +16,7 @@
#define CQSPI_READ_CAPTURE_MAX_DELAY 16
struct cadence_spi_platdata {
unsigned int ref_clk_hz;
unsigned int max_hz;
void *regbase;
void *ahbbase;

18
drivers/timer/dw-apb-timer.c
View File

@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <clk.h>
#include <reset.h>
#include <timer.h>
#include <asm/io.h>
@ -18,7 +19,8 @@
#define DW_APB_CTRL 0x8
struct dw_apb_timer_priv {
fdt_addr_t regs;
fdt_addr_t regs;
struct reset_ctl_bulk resets;
};
static int dw_apb_timer_get_count(struct udevice *dev, u64 *count)
@ -42,6 +44,12 @@ static int dw_apb_timer_probe(struct udevice *dev)
struct clk clk;
int ret;
ret = reset_get_bulk(dev, &priv->resets);
if (ret)
dev_warn(dev, "Can't get reset: %d\n", ret);
else
reset_deassert_bulk(&priv->resets);
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
@ -67,6 +75,13 @@ static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev)
return 0;
}
static int dw_apb_timer_remove(struct udevice *dev)
{
struct dw_apb_timer_priv *priv = dev_get_priv(dev);
return reset_release_bulk(&priv->resets);
}
static const struct timer_ops dw_apb_timer_ops = {
.get_count = dw_apb_timer_get_count,
};
@ -83,5 +98,6 @@ U_BOOT_DRIVER(dw_apb_timer) = {
.probe = dw_apb_timer_probe,
.of_match = dw_apb_timer_ids,
.ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata,
.remove = dw_apb_timer_remove,
.priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv),
};