From 9184590d9ab9fe92ad2f80d767f58f76d67d87a0 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 8 Nov 2019 10:56:26 +0800 Subject: [PATCH 1/9] arm: dts: Stratix10: Fix memory node address and size cells Add #address-cells and #size-cells to memory node to fix incorrect memory size decoding in recent Uboot version. Signed-off-by: Ley Foon Tan --- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c5409df026..ce07659602 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -36,6 +36,8 @@ }; memory { + #address-cells = <2>; + #size-cells = <2>; device_type = "memory"; /* 4GB */ reg = <0 0x00000000 0 0x80000000>, From 086269e17dda1b5000ef7b09bb5dc71b2421cc74 Mon Sep 17 00:00:00 2001 From: Ley Foon Tan Date: Fri, 8 Nov 2019 10:58:12 +0800 Subject: [PATCH 2/9] configs: Stratix10: Disable CONFIG_SPL_USE_TINY_PRINTF Commit 2a51e16bd57a ("configs: Make USE_TINY_PRINTF depend on SPL||TPL and be default") enable USE_TINY_PRINTF by default, disable it for Stratix10. Resync with savedefconfig. Signed-off-by: Ley Foon Tan --- configs/socfpga_stratix10_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index c7e8bf6aca..c2b94a30a3 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -55,3 +55,4 @@ CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_DWC2=y CONFIG_USB_STORAGE=y +# CONFIG_SPL_USE_TINY_PRINTF is not set From aacd7b922f052a53c34e3b2d2c92bac27e16dad5 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 23 Oct 2019 22:19:37 +0200 Subject: [PATCH 3/9] ddr: socfpga: gen5: constify altera_gen5_sdram_ops Make the function pointer struct const, as it does not need to be writable. This doesn't really change anything other than moving this variable to a different section. No functional change. Signed-off-by: Simon Goldschmidt Reviewed-by: Ley Foon Tan --- drivers/ddr/altera/sdram_gen5.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/ddr/altera/sdram_gen5.c b/drivers/ddr/altera/sdram_gen5.c index fcd89b619d..8c8ea19eb9 100644 --- a/drivers/ddr/altera/sdram_gen5.c +++ b/drivers/ddr/altera/sdram_gen5.c @@ -626,7 +626,7 @@ static int altera_gen5_sdram_get_info(struct udevice *dev, return 0; } -static struct ram_ops altera_gen5_sdram_ops = { +static const struct ram_ops altera_gen5_sdram_ops = { .get_info = altera_gen5_sdram_get_info, }; From 26fb85f4ab73cd57099d9058531f25b9cdf1c9a1 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 23 Oct 2019 22:32:30 +0200 Subject: [PATCH 4/9] socfpga: fix include guard in misc.h (arch vs. global) The file arch/arm/mach-socfpga/include/mach/misc.h used the same include guard as the global include/misc.h. Fix this by giving the arch file an arch prefix. Signed-off-by: Simon Goldschmidt Reviewed-by: Ley Foon Tan --- arch/arm/mach-socfpga/include/mach/misc.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 27d0b6a370..f11f907e1c 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -3,8 +3,8 @@ * Copyright (C) 2016-2017 Intel Corporation */ -#ifndef _MISC_H_ -#define _MISC_H_ +#ifndef _SOCFPGA_MISC_H_ +#define _SOCFPGA_MISC_H_ #include @@ -42,4 +42,4 @@ void socfpga_sdram_remap_zero(void); void do_bridge_reset(int enable, unsigned int mask); void socfpga_pl310_clear(void); -#endif /* _MISC_H_ */ +#endif /* _SOCFPGA_MISC_H_ */ From caaaf62ac89fc9b794d75cbb8c198b1684e736e1 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 23 Oct 2019 22:23:12 +0200 Subject: [PATCH 5/9] timer: dw-apb: add reset handling To use this DM timer on socfpga as system tick, it needs to take itself out of reset. Signed-off-by: Simon Goldschmidt --- drivers/timer/dw-apb-timer.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/timer/dw-apb-timer.c b/drivers/timer/dw-apb-timer.c index 86312b8dc7..fad22be8c9 100644 --- a/drivers/timer/dw-apb-timer.c +++ b/drivers/timer/dw-apb-timer.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -18,7 +19,8 @@ #define DW_APB_CTRL 0x8 struct dw_apb_timer_priv { - fdt_addr_t regs; + fdt_addr_t regs; + struct reset_ctl_bulk resets; }; static int dw_apb_timer_get_count(struct udevice *dev, u64 *count) @@ -42,6 +44,12 @@ static int dw_apb_timer_probe(struct udevice *dev) struct clk clk; int ret; + ret = reset_get_bulk(dev, &priv->resets); + if (ret) + dev_warn(dev, "Can't get reset: %d\n", ret); + else + reset_deassert_bulk(&priv->resets); + ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; @@ -67,6 +75,13 @@ static int dw_apb_timer_ofdata_to_platdata(struct udevice *dev) return 0; } +static int dw_apb_timer_remove(struct udevice *dev) +{ + struct dw_apb_timer_priv *priv = dev_get_priv(dev); + + return reset_release_bulk(&priv->resets); +} + static const struct timer_ops dw_apb_timer_ops = { .get_count = dw_apb_timer_get_count, }; @@ -83,5 +98,6 @@ U_BOOT_DRIVER(dw_apb_timer) = { .probe = dw_apb_timer_probe, .of_match = dw_apb_timer_ids, .ofdata_to_platdata = dw_apb_timer_ofdata_to_platdata, + .remove = dw_apb_timer_remove, .priv_auto_alloc_size = sizeof(struct dw_apb_timer_priv), }; From 64c7c8c91cc945a4e8ebb87ec33fbfed8d2b6a23 Mon Sep 17 00:00:00 2001 From: Simon Goldschmidt Date: Wed, 20 Nov 2019 22:27:31 +0100 Subject: [PATCH 6/9] spi: cadence_qspi: support DM_CLK Support loading clk speed via DM instead of requiring ad-hoc code. Signed-off-by: Simon Goldschmidt --- drivers/spi/cadence_qspi.c | 21 +++++++++++++++++++-- drivers/spi/cadence_qspi.h | 1 + 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c index e2e54cd277..8fd23a7702 100644 --- a/drivers/spi/cadence_qspi.c +++ b/drivers/spi/cadence_qspi.c @@ -5,6 +5,7 @@ */ #include +#include #include #include #include @@ -24,10 +25,10 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz) struct cadence_spi_priv *priv = dev_get_priv(bus); cadence_qspi_apb_config_baudrate_div(priv->regbase, - CONFIG_CQSPI_REF_CLK, hz); + plat->ref_clk_hz, hz); /* Reconfigure delay timing if speed is changed. */ - cadence_qspi_apb_delay(priv->regbase, CONFIG_CQSPI_REF_CLK, hz, + cadence_qspi_apb_delay(priv->regbase, plat->ref_clk_hz, hz, plat->tshsl_ns, plat->tsd2d_ns, plat->tchsh_ns, plat->tslch_ns); @@ -294,6 +295,8 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) { struct cadence_spi_platdata *plat = bus->platdata; ofnode subnode; + struct clk clk; + int ret; plat->regbase = (void *)devfdt_get_addr_index(bus, 0); plat->ahbbase = (void *)devfdt_get_addr_index(bus, 1); @@ -325,6 +328,20 @@ static int cadence_spi_ofdata_to_platdata(struct udevice *bus) plat->tchsh_ns = ofnode_read_u32_default(subnode, "cdns,tchsh-ns", 20); plat->tslch_ns = ofnode_read_u32_default(subnode, "cdns,tslch-ns", 20); + ret = clk_get_by_index(bus, 0, &clk); + if (ret) { +#ifdef CONFIG_CQSPI_REF_CLK + plat->ref_clk_hz = CONFIG_CQSPI_REF_CLK; +#else + return ret; +#endif + } else { + plat->ref_clk_hz = clk_get_rate(&clk); + clk_free(&clk); + if (IS_ERR_VALUE(plat->ref_clk_hz)) + return plat->ref_clk_hz; + } + debug("%s: regbase=%p ahbbase=%p max-frequency=%d page-size=%d\n", __func__, plat->regbase, plat->ahbbase, plat->max_hz, plat->page_size); diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h index 20cceca239..99dee75bbd 100644 --- a/drivers/spi/cadence_qspi.h +++ b/drivers/spi/cadence_qspi.h @@ -16,6 +16,7 @@ #define CQSPI_READ_CAPTURE_MAX_DELAY 16 struct cadence_spi_platdata { + unsigned int ref_clk_hz; unsigned int max_hz; void *regbase; void *ahbbase; From 48f23dd6a410d84499c9de1ae16dde9d10cb5fc7 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 2 Oct 2019 18:54:45 +0200 Subject: [PATCH 7/9] ARM: socfpga: Fix default mtdparts The default mtdparts value grew a trailing zero during the Kconfig conversion. This is because the mtdparts value in the header file had a \0 at the end, which got misconverted into plain 0 instead of being dropped. Signed-off-by: Marek Vasut Fixes: 43ede0bca7fc ("Kconfig: Migrate MTDIDS_DEFAULT / MTDPARTS_DEFAULT") Reviewed-by: Tom Rini --- configs/socfpga_arria5_defconfig | 2 +- configs/socfpga_cyclone5_defconfig | 2 +- configs/socfpga_de0_nano_soc_defconfig | 2 +- configs/socfpga_is1_defconfig | 2 +- configs/socfpga_mcvevk_defconfig | 2 +- configs/socfpga_sockit_defconfig | 2 +- configs/socfpga_socrates_defconfig | 2 +- configs/socfpga_sr1500_defconfig | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index c4c71177b9..491d54ddc3 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 6bf7172c2c..caa6027982 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index ebb34f5b73..ec87a6f1c6 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig index 30d3b2a2a2..ae30250bbc 100644 --- a/configs/socfpga_is1_defconfig +++ b/configs/socfpga_is1_defconfig @@ -26,7 +26,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 1eb57a60d3..081d8903bc 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index f9b5ee2d00..d70f1ed8b6 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -27,7 +27,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index e24723673c..8ac2bf5159 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -28,7 +28,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 08b829ddb8..107a13197d 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -29,7 +29,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" CONFIG_CMD_UBI=y # CONFIG_ISO_PARTITION is not set # CONFIG_EFI_PARTITION is not set From 7dad444c765ab94bf70592c502df9d1e1f72d436 Mon Sep 17 00:00:00 2001 From: "Ooi, Joyce" Date: Thu, 21 Nov 2019 06:48:56 -0800 Subject: [PATCH 8/9] arm: dts: Stratix10: change pad skew values for EMAC0 PHY driver The HPS EMAC0 drive strength is changed to 4mA because the initial 8mA drive strength has caused CE test to fail. This requires changes on the pad skew for EMAC0 PHY driver. Based on several measurements done, Tx clock does not require the extra 0.96ns delay which was needed in Arria10. Signed-off-by: Ooi, Joyce Reviewed-by: Ley Foon Tan --- arch/arm/dts/socfpga_stratix10_socdk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index ce07659602..58baa710d4 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -73,7 +73,7 @@ rxd2-skew-ps = <420>; /* 0ps */ rxd3-skew-ps = <420>; /* 0ps */ txen-skew-ps = <0>; /* -420ps */ - txc-skew-ps = <1860>; /* 960ps */ + txc-skew-ps = <900>; /* 0ps */ rxdv-skew-ps = <420>; /* 0ps */ rxc-skew-ps = <1680>; /* 780ps */ }; From 0c14bb5ad3311de2c26e66e88f8a6886773b8e0a Mon Sep 17 00:00:00 2001 From: "Ooi, Joyce" Date: Thu, 21 Nov 2019 06:06:12 -0800 Subject: [PATCH 9/9] arm: socfpga: stratix10: Add alias for gmac0 in S10 dts Add 'ethernet0' as alias for 'gmac0' in S10 device tree. Signed-off-by: Chee Hong Ang Signed-off-by: Ooi, Joyce Reviewed-by: Ley Foon Tan --- arch/arm/dts/socfpga_stratix10_socdk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index 58baa710d4..b7b48a5d31 100755 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -9,6 +9,7 @@ model = "SoCFPGA Stratix 10 SoCDK"; aliases { + ethernet0 = &gmac0; i2c0 = &i2c1; serial0 = &uart0; };