brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

Merge branch '2018-12-06-master-imports'

Browse Source 
- Various FAT fixes
- Hardware spinlock uclass
- DMA uclass
- Various am335x fixes
- DT resyncs for a number of TI platforms
- stm32 updates
This commit is contained in:
Tom Rini 2018-12-07 10:55:12 -05:00
commit 3589025867
73 changed files with 3287 additions and 878 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
.travis.yml
View File

@ -42,7 +42,7 @@ install:
- ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
# prepare buildman environment
- echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- echo -e "arc = /tmp/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- echo -e "arc = /tmp/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install" >> ~/.buildman
- echo -e "\n[toolchain-alias]\nsh = sh2\n" >> ~/.buildman
- cat ~/.buildman
- virtualenv /tmp/venv
@ -75,8 +75,8 @@ before_script:
echo -e "\n[toolchain-alias]\nx86 = i386" >> ~/.buildman;
fi
- if [[ "${TOOLCHAIN}" == arc ]]; then
wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2017.09-release/arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
tar -C /tmp -xf arc_gnu_2017.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
wget https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases/download/arc-2018.09-release/arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz &&
tar -C /tmp -xf arc_gnu_2018.09_prebuilt_uclibc_le_archs_linux_install.tar.gz;
fi
- if [[ "${TOOLCHAIN}" == *xtensa* ]]; then
wget https://github.com/foss-xtensa/toolchain/releases/download/2018.02/x86_64-2018.02-${TOOLCHAIN}.tar.gz &&

6
arch/arm/dts/am335x-evm.dts
View File

@ -80,8 +80,6 @@
gpio_keys: volume_keys@0 {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
switch@9 {
@ -723,8 +721,8 @@
&mmc3 {
/* these are on the crossbar and are outlined in the
xbar-event-map element */
dmas = <&edma 12
&edma 13>;
dmas = <&edma 12 0
&edma 13 0>;
dma-names = "tx", "rx";
status = "okay";
vmmc-supply = <&wlan_en_reg>;

2
arch/arm/dts/am335x-evmsk.dts
View File

@ -109,8 +109,6 @@
gpio_buttons: gpio_buttons@0 {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
switch@1 {
label = "button0";

8
arch/arm/dts/am335x-pdu001-u-boot.dtsi
View File

@ -29,10 +29,18 @@
u-boot,dm-pre-reloc;
};
&mmc1 {
u-boot,dm-pre-reloc;
};
&mmc1_pins {
u-boot,dm-pre-reloc;
};
&mmc2 {
u-boot,dm-pre-reloc;
};
&mmc2_pins {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/am335x-pdu001.dts
View File

@ -576,7 +576,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
};
&sham {

2
arch/arm/dts/am335x-pxm2.dtsi
View File

@ -50,8 +50,6 @@
gpio_keys: restart-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
restart0 {

10
arch/arm/dts/am335x-rut.dts
View File

@ -36,8 +36,6 @@
gpio_keys: powerfail-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pwr-fail0 {
@ -190,12 +188,8 @@
&epwmss1 {
status = "okay";
ehrpwm1: ehrpwm@48302200 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&epwmss1_pins>;
};
pinctrl-names = "default";
pinctrl-0 = <&epwmss1_pins>;
};
&gpmc {

271
arch/arm/dts/am33xx-clocks.dtsi
View File

@ -8,7 +8,7 @@
* published by the Free Software Foundation.
*/
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
sys_clkin_ck: sys_clkin_ck@40 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
@ -163,7 +163,7 @@
clock-frequency = <12000000>;
};
dpll_core_ck: dpll_core_ck {
dpll_core_ck: dpll_core_ck@490 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-core-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
@ -176,7 +176,7 @@
clocks = <&dpll_core_ck>;
};
dpll_core_m4_ck: dpll_core_m4_ck {
dpll_core_m4_ck: dpll_core_m4_ck@480 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@ -185,7 +185,7 @@
ti,index-starts-at-one;
};
dpll_core_m5_ck: dpll_core_m5_ck {
dpll_core_m5_ck: dpll_core_m5_ck@484 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@ -194,7 +194,7 @@
ti,index-starts-at-one;
};
dpll_core_m6_ck: dpll_core_m6_ck {
dpll_core_m6_ck: dpll_core_m6_ck@4d8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_core_x2_ck>;
@ -203,14 +203,14 @@
ti,index-starts-at-one;
};
dpll_mpu_ck: dpll_mpu_ck {
dpll_mpu_ck: dpll_mpu_ck@488 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0488>, <0x0420>, <0x042c>;
};
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
dpll_mpu_m2_ck: dpll_mpu_m2_ck@4a8 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_mpu_ck>;
@ -219,14 +219,14 @@
ti,index-starts-at-one;
};
dpll_ddr_ck: dpll_ddr_ck {
dpll_ddr_ck: dpll_ddr_ck@494 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0494>, <0x0434>, <0x0440>;
};
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
dpll_ddr_m2_ck: dpll_ddr_m2_ck@4a0 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_ddr_ck>;
@ -243,14 +243,14 @@
clock-div = <2>;
};
dpll_disp_ck: dpll_disp_ck {
dpll_disp_ck: dpll_disp_ck@498 {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x0498>, <0x0448>, <0x0454>;
};
dpll_disp_m2_ck: dpll_disp_m2_ck {
dpll_disp_m2_ck: dpll_disp_m2_ck@4a4 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_disp_ck>;
@ -260,14 +260,14 @@
ti,set-rate-parent;
};
dpll_per_ck: dpll_per_ck {
dpll_per_ck: dpll_per_ck@48c {
#clock-cells = <0>;
compatible = "ti,am3-dpll-no-gate-j-type-clock";
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
reg = <0x048c>, <0x0470>, <0x049c>;
};
dpll_per_m2_ck: dpll_per_m2_ck {
dpll_per_m2_ck: dpll_per_m2_ck@4ac {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&dpll_per_ck>;
@ -292,14 +292,6 @@
clock-div = <4>;
};
cefuse_fck: cefuse_fck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <1>;
reg = <0x0a20>;
};
clk_24mhz: clk_24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -316,14 +308,6 @@
clock-div = <732>;
};
clkdiv32k_ick: clkdiv32k_ick {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ck>;
ti,bit-shift = <1>;
reg = <0x014c>;
};
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@ -332,14 +316,14 @@
clock-div = <1>;
};
pruss_ocp_gclk: pruss_ocp_gclk {
pruss_ocp_gclk: pruss_ocp_gclk@530 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
reg = <0x0530>;
};
mmu_fck: mmu_fck {
mmu_fck: mmu_fck@914 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
@ -347,56 +331,56 @@
reg = <0x0914>;
};
timer1_fck: timer1_fck {
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck {
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck {
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck {
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck {
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck {
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck {
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
usbotg_fck: usbotg_fck {
usbotg_fck: usbotg_fck@47c {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_per_ck>;
@ -412,7 +396,7 @@
clock-div = <2>;
};
ieee5000_fck: ieee5000_fck {
ieee5000_fck: ieee5000_fck@e4 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_div2_ck>;
@ -420,10 +404,10 @@
reg = <0x00e4>;
};
wdt1_fck: wdt1_fck {
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@ -483,53 +467,21 @@
clock-div = <2>;
};
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk@520 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
reg = <0x0520>;
};
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
gpio0_dbclk: gpio0_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&gpio0_dbclk_mux_ck>;
ti,bit-shift = <18>;
reg = <0x0408>;
};
gpio1_dbclk: gpio1_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00ac>;
};
gpio2_dbclk: gpio2_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b0>;
};
gpio3_dbclk: gpio3_dbclk {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkdiv32k_ick>;
ti,bit-shift = <18>;
reg = <0x00b4>;
};
lcd_gclk: lcd_gclk {
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
@ -545,7 +497,7 @@
clock-div = <2>;
};
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck@52c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
@ -553,7 +505,7 @@
reg = <0x052c>;
};
gfx_fck_div_ck: gfx_fck_div_ck {
gfx_fck_div_ck: gfx_fck_div_ck@52c {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&gfx_fclk_clksel_ck>;
@ -561,14 +513,14 @@
ti,max-div = <2>;
};
sysclkout_pre_ck: sysclkout_pre_ck {
sysclkout_pre_ck: sysclkout_pre_ck@700 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
reg = <0x0700>;
};
clkout2_div_ck: clkout2_div_ck {
clkout2_div_ck: clkout2_div_ck@700 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&sysclkout_pre_ck>;
@ -577,59 +529,7 @@
reg = <0x0700>;
};
dbg_sysclk_ck: dbg_sysclk_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_clkin_ck>;
ti,bit-shift = <19>;
reg = <0x0414>;
};
dbg_clka_ck: dbg_clka_ck {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&dpll_core_m4_ck>;
ti,bit-shift = <30>;
reg = <0x0414>;
};
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <22>;
reg = <0x0414>;
};
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
ti,bit-shift = <20>;
reg = <0x0414>;
};
stm_clk_div_ck: stm_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&stm_pmd_clock_mux_ck>;
ti,bit-shift = <27>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&trace_pmd_clk_mux_ck>;
ti,bit-shift = <24>;
ti,max-div = <64>;
reg = <0x0414>;
ti,index-power-of-two;
};
clkout2_ck: clkout2_ck {
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&clkout2_div_ck>;
@ -638,9 +538,88 @@
};
};
&prcm_clockdomains {
clk_24mhz_clkdm: clk_24mhz_clkdm {
compatible = "ti,clockdomain";
clocks = <&clkdiv32k_ick>;
&prcm {
l4_per_cm: l4_per_cm@0 {
compatible = "ti,omap4-cm";
reg = <0x0 0x200>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0 0x200>;
l4_per_clkctrl: clk@14 {
compatible = "ti,clkctrl";
reg = <0x14 0x13c>;
#clock-cells = <2>;
};
};
l4_wkup_cm: l4_wkup_cm@400 {
compatible = "ti,omap4-cm";
reg = <0x400 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x400 0x100>;
l4_wkup_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0xd4>;
#clock-cells = <2>;
};
};
mpu_cm: mpu_cm@600 {
compatible = "ti,omap4-cm";
reg = <0x600 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x600 0x100>;
mpu_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_rtc_cm: l4_rtc_cm@800 {
compatible = "ti,omap4-cm";
reg = <0x800 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x800 0x100>;
l4_rtc_clkctrl: clk@0 {
compatible = "ti,clkctrl";
reg = <0x0 0x4>;
#clock-cells = <2>;
};
};
gfx_l3_cm: gfx_l3_cm@900 {
compatible = "ti,omap4-cm";
reg = <0x900 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x900 0x100>;
gfx_l3_clkctrl: clk@4 {
compatible = "ti,clkctrl";
reg = <0x4 0x4>;
#clock-cells = <2>;
};
};
l4_cefuse_cm: l4_cefuse_cm@a00 {
compatible = "ti,omap4-cm";
reg = <0xa00 0x100>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xa00 0x100>;
l4_cefuse_clkctrl: clk@20 {
compatible = "ti,clkctrl";
reg = <0x20 0x4>;
#clock-cells = <2>;
};
};
};

347
arch/arm/dts/am33xx.dtsi
View File

@ -10,12 +10,14 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
#include "skeleton.dtsi"
#include <dt-bindings/clock/am3.h>
/ {
compatible = "ti,am33xx";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
i2c0 = &i2c0;
@ -27,14 +29,16 @@
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
d_can0 = &dcan0;
d_can1 = &dcan1;
d-can0 = &dcan0;
d-can1 = &dcan1;
usb0 = &usb0;
usb1 = &usb1;
phy0 = &usb0_phy;
phy1 = &usb1_phy;
ethernet0 = &cpsw_emac0;
ethernet1 = &cpsw_emac1;
spi0 = &spi0;
spi1 = &spi1;
};
cpus {
@ -45,19 +49,7 @@
device_type = "cpu";
reg = <0>;
/*
* To consider voltage drop between PMIC and SoC,
* tolerance value is reduced to 2% from 4% and
* voltage value is increased as a precaution.
*/
operating-points = <
/* kHz uV */
720000 1285000
600000 1225000
500000 1125000
275000 1125000
>;
voltage-tolerance = <2>; /* 2 percentage */
operating-points-v2 = <&cpu0_opp_table>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
@ -66,9 +58,84 @@
};
};
pmu {
cpu0_opp_table: opp-table {
compatible = "operating-points-v2-ti-cpu";
syscon = <&scm_conf>;
/*
* The three following nodes are marked with opp-suspend
* because the can not be enabled simultaneously on a
* single SoC.
*/
opp50-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <950000 931000 969000>;
opp-supported-hw = <0x06 0x0010>;
opp-suspend;
};
opp100-275000000 {
opp-hz = /bits/ 64 <275000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0x00FF>;
opp-suspend;
};
opp100-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0020>;
opp-suspend;
};
opp100-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x01 0xFFFF>;
};
opp100-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1100000 1078000 1122000>;
opp-supported-hw = <0x06 0x0040>;
};
opp120-600000000 {
opp-hz = /bits/ 64 <600000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x01 0xFFFF>;
};
opp120-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1200000 1176000 1224000>;
opp-supported-hw = <0x06 0x0080>;
};
oppturbo-720000000 {
opp-hz = /bits/ 64 <720000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x01 0xFFFF>;
};
oppturbo-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1260000 1234800 1285200>;
opp-supported-hw = <0x06 0x0100>;
};
oppnitro-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <1325000 1298500 1351500>;
opp-supported-hw = <0x04 0x0200>;
};
};
pmu@4b000000 {
compatible = "arm,cortex-a8-pmu";
interrupts = <3>;
reg = <0x4b000000 0x1000000>;
ti,hwmods = "debugss";
};
/*
@ -80,6 +147,8 @@
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};
};
@ -91,7 +160,6 @@
* the whole bus hierarchy.
*/
ocp {
u-boot,dm-spl;
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -104,9 +172,21 @@
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
wkup_m3: wkup_m3@100000 {
compatible = "ti,am3352-wkup-m3";
reg = <0x100000 0x4000>,
<0x180000 0x2000>;
reg-names = "umem", "dmem";
ti,hwmods = "wkup_m3";
ti,pm-firmware = "am335x-pm-firmware.elf";
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@ -122,6 +202,7 @@
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
#pinctrl-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
@ -129,15 +210,17 @@
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
compatible = "syscon", "simple-bus";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x800>;
scm_clocks: clocks {
#address-cells = <1>;
@ -145,6 +228,22 @@
};
};
wkup_m3_ipc: wkup_m3_ipc@1324 {
compatible = "ti,am3352-wkup-m3-ipc";
reg = <0x1324 0x24>;
interrupts = <78>;
ti,rproc = <&wkup_m3>;
mboxes = <&mailbox &mbox_wkupm3>;
};
edma_xbar: dma-router@f90 {
compatible = "ti,am335x-edma-crossbar";
reg = <0xf90 0x40>;
#dma-cells = <3>;
dma-requests = <32>;
dma-masters = <&edma>;
};
scm_clockdomains: clockdomains {
};
};
@ -158,12 +257,44 @@
};
edma: edma@49000000 {
compatible = "ti,edma3";
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
reg = <0x49000000 0x10000>,
<0x44e10f90 0x40>;
compatible = "ti,edma3-tpcc";
ti,hwmods = "tpcc";
reg = <0x49000000 0x10000>;
reg-names = "edma3_cc";
interrupts = <12 13 14>;
#dma-cells = <1>;
interrupt-names = "edma3_ccint", "edma3_mperr",
"edma3_ccerrint";
dma-requests = <64>;
#dma-cells = <2>;
ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
<&edma_tptc2 0>;
ti,edma-memcpy-channels = <20 21>;
};
edma_tptc0: tptc@49800000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc0";
reg = <0x49800000 0x100000>;
interrupts = <112>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc1: tptc@49900000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc1";
reg = <0x49900000 0x100000>;
interrupts = <113>;
interrupt-names = "edma3_tcerrint";
};
edma_tptc2: tptc@49a00000 {
compatible = "ti,edma3-tptc";
ti,hwmods = "tptc2";
reg = <0x49a00000 0x100000>;
interrupts = <114>;
interrupt-names = "edma3_tcerrint";
};
gpio0: gpio@44e07000 {
@ -211,67 +342,61 @@
};
uart0: serial@44e09000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart1";
clock-frequency = <48000000>;
reg = <0x44e09000 0x2000>;
reg-shift = <2>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26>, <&edma 27>;
dmas = <&edma 26 0>, <&edma 27 0>;
dma-names = "tx", "rx";
};
uart1: serial@48022000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart2";
clock-frequency = <48000000>;
reg = <0x48022000 0x2000>;
reg-shift = <2>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28>, <&edma 29>;
dmas = <&edma 28 0>, <&edma 29 0>;
dma-names = "tx", "rx";
};
uart2: serial@48024000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart3";
clock-frequency = <48000000>;
reg = <0x48024000 0x2000>;
reg-shift = <2>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30>, <&edma 31>;
dmas = <&edma 30 0>, <&edma 31 0>;
dma-names = "tx", "rx";
};
uart3: serial@481a6000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart4";
clock-frequency = <48000000>;
reg = <0x481a6000 0x2000>;
reg-shift = <2>;
interrupts = <44>;
status = "disabled";
};
uart4: serial@481a8000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart5";
clock-frequency = <48000000>;
reg = <0x481a8000 0x2000>;
reg-shift = <2>;
interrupts = <45>;
status = "disabled";
};
uart5: serial@481aa000 {
compatible = "ti,omap3-uart";
compatible = "ti,am3352-uart", "ti,omap3-uart";
ti,hwmods = "uart6";
clock-frequency = <48000000>;
reg = <0x481aa000 0x2000>;
reg-shift = <2>;
interrupts = <46>;
status = "disabled";
};
@ -312,8 +437,8 @@
ti,dual-volt;
ti,needs-special-reset;
ti,needs-special-hs-handling;
dmas = <&edma 24
&edma 25>;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
interrupts = <64>;
reg = <0x48060000 0x1000>;
@ -324,8 +449,8 @@
compatible = "ti,omap4-hsmmc";
ti,hwmods = "mmc2";
ti,needs-special-reset;
dmas = <&edma 2
&edma 3>;
dmas = <&edma 2 0
&edma 3 0>;
dma-names = "tx", "rx";
interrupts = <28>;
reg = <0x481d8000 0x1000>;
@ -377,7 +502,7 @@
status = "disabled";
};
mailbox: mailbox@480C8000 {
mailbox: mailbox@480c8000 {
compatible = "ti,omap4-mailbox";
reg = <0x480C8000 0x200>;
interrupts = <77>;
@ -386,6 +511,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <8>;
mbox_wkupm3: wkup_m3 {
ti,mbox-send-noirq;
ti,mbox-tx = <0 0 0>;
ti,mbox-rx = <0 0 3>;
};
@ -397,6 +523,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
clocks = <&timer1_fck>;
clock-names = "fck";
};
timer2: timer@48040000 {
@ -404,6 +532,8 @@
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
clocks = <&timer2_fck>;
clock-names = "fck";
};
timer3: timer@48042000 {
@ -451,6 +581,8 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
spi0: spi@48030000 {
@ -461,10 +593,10 @@
interrupts = <65>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi0";
dmas = <&edma 16
&edma 17
&edma 18
&edma 19>;
dmas = <&edma 16 0
&edma 17 0
&edma 18 0
&edma 19 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@ -477,10 +609,10 @@
interrupts = <125>;
ti,spi-num-cs = <2>;
ti,hwmods = "spi1";
dmas = <&edma 42
&edma 43
&edma 44
&edma 45>;
dmas = <&edma 42 0
&edma 43 0
&edma 44 0
&edma 45 0>;
dma-names = "tx0", "rx0", "tx1", "rx1";
status = "disabled";
};
@ -508,6 +640,7 @@
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb0: usb@47401000 {
@ -556,6 +689,7 @@
reg-names = "phy";
status = "disabled";
ti,ctrl_mod = <&usb_ctrl_mod>;
#phy-cells = <0>;
};
usb1: usb@47401800 {
@ -625,20 +759,24 @@
0x48300200 0x48300200 0x80>; /* EHRPWM */
ecap0: ecap@48300100 {
compatible = "ti,am33xx-ecap";
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48300100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <31>;
interrupt-names = "ecap0";
ti,hwmods = "ecap0";
status = "disabled";
};
ehrpwm0: ehrpwm@48300200 {
compatible = "ti,am33xx-ehrpwm";
ehrpwm0: pwm@48300200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48300200 0x80>;
ti,hwmods = "ehrpwm0";
clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -655,20 +793,24 @@
0x48302200 0x48302200 0x80>; /* EHRPWM */
ecap1: ecap@48302100 {
compatible = "ti,am33xx-ecap";
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48302100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <47>;
interrupt-names = "ecap1";
ti,hwmods = "ecap1";
status = "disabled";
};
ehrpwm1: ehrpwm@48302200 {
compatible = "ti,am33xx-ehrpwm";
ehrpwm1: pwm@48302200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48302200 0x80>;
ti,hwmods = "ehrpwm1";
clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
@ -685,34 +827,36 @@
0x48304200 0x48304200 0x80>; /* EHRPWM */
ecap2: ecap@48304100 {
compatible = "ti,am33xx-ecap";
compatible = "ti,am3352-ecap",
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x48304100 0x80>;
clocks = <&l4ls_gclk>;
clock-names = "fck";
interrupts = <61>;
interrupt-names = "ecap2";
ti,hwmods = "ecap2";
status = "disabled";
};
ehrpwm2: ehrpwm@48304200 {
compatible = "ti,am33xx-ehrpwm";
ehrpwm2: pwm@48304200 {
compatible = "ti,am3352-ehrpwm",
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x48304200 0x80>;
ti,hwmods = "ehrpwm2";
clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
clock-names = "tbclk", "fck";
status = "disabled";
};
};
mac: ethernet@4a100000 {
compatible = "ti,cpsw";
compatible = "ti,am335x-cpsw","ti,cpsw";
ti,hwmods = "cpgmac0";
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
bd_ram_size = <0x2000>;
no_bd_ram = <0>;
rx_descs = <64>;
mac_control = <0x20>;
slaves = <2>;
active_slave = <0>;
@ -734,7 +878,7 @@
status = "disabled";
davinci_mdio: mdio@4a101000 {
compatible = "ti,davinci_mdio";
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "davinci_mdio";
@ -763,14 +907,21 @@
ocmcram: ocmcram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x10000>; /* 64k */
};
ranges = <0x0 0x40300000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
wkup_m3: wkup_m3@44d00000 {
compatible = "ti,am3353-wkup-m3";
reg = <0x44d00000 0x4000 /* M3 UMEM */
0x44d80000 0x2000>; /* M3 DMEM */
ti,hwmods = "wkup_m3";
ti,no-reset-on-init;
pm_sram_code: pm-sram-code@0 {
compatible = "ti,sram";
reg = <0x0 0x1000>;
protect-exec;
};
pm_sram_data: pm-sram-data@1000 {
compatible = "ti,sram";
reg = <0x1000 0x1000>;
pool;
};
};
elm: elm@48080000 {
@ -795,6 +946,8 @@
interrupts = <16>;
ti,hwmods = "adc_tsc";
status = "disabled";
dmas = <&edma 53 0>, <&edma 57 0>;
dma-names = "fifo0", "fifo1";
tsc {
compatible = "ti,am3359-tsc";
@ -805,16 +958,32 @@
};
};
emif: emif@4c000000 {
compatible = "ti,emif-am3352";
reg = <0x4c000000 0x1000000>;
ti,hwmods = "emif";
interrupts = <101>;
sram = <&pm_sram_code
&pm_sram_data>;
ti,no-idle;
};
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
ti,no-idle-on-init;
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
@ -823,7 +992,7 @@
ti,hwmods = "sham";
reg = <0x53100000 0x200>;
interrupts = <109>;
dmas = <&edma 36>;
dmas = <&edma 36 0>;
dma-names = "rx";
};
@ -832,8 +1001,8 @@
ti,hwmods = "aes";
reg = <0x53500000 0xa0>;
interrupts = <103>;
dmas = <&edma 6>,
<&edma 5>;
dmas = <&edma 6 0>,
<&edma 5 0>;
dma-names = "tx", "rx";
};
@ -846,12 +1015,12 @@
interrupts = <80>, <81>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8>,
<&edma 9>;
dmas = <&edma 8 2>,
<&edma 9 2>;
dma-names = "tx", "rx";
};
mcasp1: mcasp@4803C000 {
mcasp1: mcasp@4803c000 {
compatible = "ti,am33xx-mcasp-audio";
ti,hwmods = "mcasp1";
reg = <0x4803C000 0x2000>,
@ -860,8 +1029,8 @@
interrupts = <82>, <83>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10>,
<&edma 11>;
dmas = <&edma 10 2>,
<&edma 11 2>;
dma-names = "tx", "rx";
};
@ -874,4 +1043,4 @@
};
};
/include/ "am33xx-clocks.dtsi"
#include "am33xx-clocks.dtsi"

220
arch/arm/dts/am3517-evm-ui.dtsi Normal file
View File

@ -0,0 +1,220 @@
/*
* Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/input/input.h>
/ {
codec1 {
compatible = "simple-audio-card";
simple-audio-card,name = "tlv320aic23-hifi";
simple-audio-card,widgets =
"Microphone", "Mic In",
"Line", "Line In",
"Line", "Line Out";
simple-audio-card,routing =
"Line Out", "LOUT",
"Line Out", "ROUT",
"LLINEIN", "Line In",
"RLINEIN", "Line In",
"MICIN", "Mic In";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_master>;
simple-audio-card,frame-master = <&sound_master>;
simple-audio-card,cpu {
sound-dai = <&mcbsp1>;
};
sound_master: simple-audio-card,codec {
sound-dai = <&tlv320aic23_1>;
system-clock-frequency = <12000000>;
};
};
codec2 {
compatible = "simple-audio-card";
simple-audio-card,name = "tlv320aic23-hifi";
simple-audio-card,widgets =
"Microphone", "Mic In",
"Line", "Line In",
"Line", "Line Out";
simple-audio-card,routing =
"Line Out", "LOUT",
"Line Out", "ROUT",
"LLINEIN", "Line In",
"RLINEIN", "Line In",
"MICIN", "Mic In";
simple-audio-card,format = "i2s";
simple-audio-card,bitclock-master = <&sound_master2>;
simple-audio-card,frame-master = <&sound_master2>;
simple-audio-card,cpu {
sound-dai = <&mcbsp2>;
};
sound_master2: simple-audio-card,codec {
sound-dai = <&tlv320aic23_2>;
system-clock-frequency = <12000000>;
};
};
expander-keys {
compatible = "gpio-keys-polled";
poll-interval = <100>;
record {
label = "Record";
/* linux,code = <BTN_0>; */
gpios = <&tca6416_2 15 GPIO_ACTIVE_LOW>;
};
play {
label = "Play";
linux,code = <KEY_PLAY>;
gpios = <&tca6416_2 14 GPIO_ACTIVE_LOW>;
};
Stop {
label = "Stop";
linux,code = <KEY_STOP>;
gpios = <&tca6416_2 13 GPIO_ACTIVE_LOW>;
};
fwd {
label = "FWD";
linux,code = <KEY_FASTFORWARD>;
gpios = <&tca6416_2 12 GPIO_ACTIVE_LOW>;
};
rwd {
label = "RWD";
linux,code = <KEY_REWIND>;
gpios = <&tca6416_2 11 GPIO_ACTIVE_LOW>;
};
shift {
label = "Shift";
linux,code = <KEY_LEFTSHIFT>;
gpios = <&tca6416_2 10 GPIO_ACTIVE_LOW>;
};
Mode {
label = "Mode";
linux,code = <BTN_MODE>;
gpios = <&tca6416_2 9 GPIO_ACTIVE_LOW>;
};
Menu {
label = "Menu";
linux,code = <KEY_MENU>;
gpios = <&tca6416_2 8 GPIO_ACTIVE_LOW>;
};
Up {
label = "Up";
linux,code = <KEY_UP>;
gpios = <&tca6416_2 7 GPIO_ACTIVE_LOW>;
};
Down {
label = "Down";
linux,code = <KEY_DOWN>;
gpios = <&tca6416_2 6 GPIO_ACTIVE_LOW>;
};
};
};
&i2c2 {
/* Audio codecs */
tlv320aic23_1: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
#sound-dai-cells= <0>;
status = "okay";
};
tlv320aic23_2: codec@1b {
compatible = "ti,tlv320aic23";
reg = <0x1b>;
#sound-dai-cells= <0>;
status = "okay";
};
};
&i2c3 {
/* Audio codecs */
tlv320aic23_3: codec@1a {
compatible = "ti,tlv320aic23";
reg = <0x1a>;
#sound-dai-cells= <0>;
status = "okay";
};
/* GPIO Expanders */
tca6416_2: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&vdd_io_reg>;
};
tca6416_3: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&vdd_io_reg>;
};
/* TVP5146 Analog Video decoder input */
tvp5146@5c {
compatible = "ti,tvp5146m2";
reg = <0x5c>;
};
};
&mcbsp1 {
status = "ok";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
};
&mcbsp2 {
status = "ok";
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
};
&omap3_pmx_core {
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2190, PIN_OUTPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dx */
OMAP3_CORE1_IOPAD(0x2192, PIN_INPUT | MUX_MODE0) /* mcbsp1_dx.mcbsp1_dr */
OMAP3_CORE1_IOPAD(0x2196, PIN_INPUT | MUX_MODE0) /* mcbsp_clks.mcbsp1_fsx */
OMAP3_CORE1_IOPAD(0x2198, PIN_INPUT | MUX_MODE0) /* mcbsp1_clkx.mcbsp1_clkx */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */
OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx.mcbsp2_clkx */
OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr.mcbsp2.dr */
OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx.mcbsp2_dx */
>;
};
};

3
arch/arm/dts/am3517-evm.dts
View File

@ -9,6 +9,7 @@
#include "am3517.dtsi"
#include "am3517-som.dtsi"
#include "am3517-evm-ui.dtsi"
#include <dt-bindings/input/input.h>
/ {
@ -227,7 +228,7 @@
vmmc-supply = <&vmmc_fixed>;
bus-width = <4>;
wp-gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; /* gpio_126 */
cd-gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio_127 */
cd-gpios = <&gpio4 31 GPIO_ACTIVE_LOW>; /* gpio_127 */
};
&mmc3 {

2
arch/arm/dts/am3517-som.dtsi
View File

@ -163,7 +163,7 @@
compatible = "ti,wl1271";
reg = <2>;
interrupt-parent = <&gpio6>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; /* gpio_170 */
interrupts = <10 IRQ_TYPE_EDGE_RISING>; /* gpio_170 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};

12
arch/arm/dts/am4372.dtsi
View File

@ -108,8 +108,6 @@
compatible = "ti,am437-padconf",
"pinctrl-single";
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
@ -119,8 +117,6 @@
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
@ -764,7 +760,8 @@
reg = <0x48038000 0x2000>,
<0x46000000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <80>, <81>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 8>,
@ -778,7 +775,8 @@
reg = <0x4803C000 0x2000>,
<0x46400000 0x400000>;
reg-names = "mpu", "dat";
interrupts = <82>, <83>;
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "tx", "rx";
status = "disabled";
dmas = <&edma 10>,
@ -807,6 +805,8 @@
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
status = "disabled";
};

2
arch/arm/dts/am437x-idk-evm.dts
View File

@ -106,8 +106,6 @@
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&gpio_keys_pins_default>;
#address-cells = <1>;
#size-cells = <0>;
switch@0 {
label = "power-button";

2
arch/arm/dts/bcm6858.dtsi
View File

@ -75,7 +75,7 @@
u-boot,dm-pre-reloc;
uart0: serial@ff800640 {
compatible = "brcm,bcm6858-uart";
compatible = "brcm,bcm6345-uart";
reg = <0x0 0xff800640 0x0 0x18>;
clocks = <&periph_osc>;

97
arch/arm/dts/da850-evm.dts
View File

@ -27,6 +27,65 @@
spi0 = &spi1;
};
backlight: backlight-pwm {
pinctrl-names = "default";
pinctrl-0 = <&ecap2_pins>;
power-supply = <&backlight_lcd>;
compatible = "pwm-backlight";
/*
* The PWM here corresponds to production hardware. The
* schematic needs to be 1015171 (15 March 2010), Rev A
* or newer.
*/
pwms = <&ecap2 0 50000 0>;
brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
default-brightness-level = <7>;
};
panel {
compatible = "ti,tilcdc,panel";
pinctrl-names = "default";
pinctrl-0 = <&lcd_pins>;
/*
* The vpif and the LCD are mutually exclusive.
* To enable VPIF, change the status below to 'disabled' then
* then change the status of the vpif below to 'okay'
*/
status = "okay";
enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
panel-info {
ac-bias = <255>;
ac-bias-intrpt = <0>;
dma-burst-sz = <16>;
bpp = <16>;
fdd = <0x80>;
sync-edge = <0>;
sync-ctrl = <1>;
raster-order = <0>;
fifo-th = <0>;
};
display-timings {
native-mode = <&timing0>;
timing0: 480x272 {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <3>;
hback-porch = <2>;
hsync-len = <42>;
vback-porch = <3>;
vfront-porch = <4>;
vsync-len = <11>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
};
};
};
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
@ -35,6 +94,15 @@
regulator-boot-on;
};
backlight_lcd: backlight-regulator {
compatible = "regulator-fixed";
regulator-name = "lcd_backlight_pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */
enable-active-high;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 EVM";
@ -63,6 +131,14 @@
};
};
&ecap2 {
status = "okay";
};
&ref_clk {
clock-frequency = <24000000>;
};
&pmx_core {
status = "okay";
@ -93,6 +169,10 @@
};
};
&sata {
status = "okay";
};
&serial0 {
status = "okay";
};
@ -109,6 +189,10 @@
status = "okay";
};
&lcdc {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <100000>;
@ -137,6 +221,12 @@
gpio-controller;
#gpio-cells = <2>;
};
tca6416_bb: gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
&wdt {
@ -336,5 +426,10 @@
&vpif {
pinctrl-names = "default";
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
status = "okay";
/*
* The vpif and the LCD are mutually exclusive.
* To enable VPIF, disable the ti,tilcdc,panel then
* change the status below to 'okay'
*/
status = "disabled";
};

13
arch/arm/dts/da850-lcdk.dts
View File

@ -21,8 +21,8 @@
stdout-path = "serial2:115200n8";
};
memory {
device_type = "memory";
memory@c0000000 {
/* 128 MB DDR2 SDRAM @ 0xc0000000 */
reg = <0xc0000000 0x08000000>;
};
@ -123,6 +123,10 @@
};
};
&ref_clk {
clock-frequency = <24000000>;
};
&pmx_core {
status = "okay";
@ -175,6 +179,11 @@
status = "okay";
};
&sata_refclk {
status = "okay";
clock-frequency = <100000000>;
};
&sata {
status = "okay";
};

349
arch/arm/dts/da850.dtsi
View File

@ -7,10 +7,19 @@
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases { };
memory@c0000000 {
device_type = "memory";
reg = <0xc0000000 0x0>;
};
arm {
#address-cells = <1>;
#size-cells = <1>;
@ -23,6 +32,25 @@
reg = <0xfffee000 0x2000>;
};
};
clocks: clocks {
ref_clk: ref_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "ref_clk";
};
sata_refclk: sata_refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "sata_refclk";
status = "disabled";
};
usb_refclkin: usb_refclkin {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-output-names = "usb_refclkin";
status = "disabled";
};
};
dsp: dsp@11800000 {
compatible = "ti,da850-dsp";
reg = <0x11800000 0x40000>,
@ -33,6 +61,8 @@
reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
interrupt-parent = <&intc>;
interrupts = <28>;
clocks = <&psc0 15>;
resets = <&psc0 15>;
status = "disabled";
};
soc@1c00000 {
@ -43,17 +73,57 @@
ranges = <0x0 0x01c00000 0x400000>;
interrupt-parent = <&intc>;
psc0: clock-controller@10000 {
compatible = "ti,da850-psc0";
reg = <0x10000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pll0_sysclk 1>, <&pll0_sysclk 2>,
<&pll0_sysclk 4>, <&pll0_sysclk 6>,
<&async1_clk>;
clock-names = "pll0_sysclk1", "pll0_sysclk2",
"pll0_sysclk4", "pll0_sysclk6",
"async1";
};
pll0: clock-controller@11000 {
compatible = "ti,da850-pll0";
reg = <0x11000 0x1000>;
clocks = <&ref_clk>, <&pll1_sysclk 3>;
clock-names = "clksrc", "extclksrc";
pll0_pllout: pllout {
#clock-cells = <0>;
};
pll0_sysclk: sysclk {
#clock-cells = <1>;
};
pll0_auxclk: auxclk {
#clock-cells = <0>;
};
pll0_obsclk: obsclk {
#clock-cells = <0>;
};
};
pmx_core: pinmux@14120 {
compatible = "pinctrl-single";
reg = <0x14120 0x50>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <2>;
pinctrl-single,bit-per-mux;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xf>;
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 17 0x8>,
<&range 17 8 0x4>,
<&range 26 8 0x4>,
<&range 34 80 0x8>,
<&range 129 31 0x8>;
status = "disabled";
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
pinctrl-single,bits = <
/* UART0_RTS UART0_CTS */
@ -264,8 +334,41 @@
usb_phy: usb-phy {
compatible = "ti,da830-usb-phy";
#phy-cells = <1>;
clocks = <&usb_phy_clk 0>, <&usb_phy_clk 1>;
clock-names = "usb0_clk48", "usb1_clk48";
status = "disabled";
};
usb_phy_clk: usb-phy-clocks {
compatible = "ti,da830-usb-phy-clocks";
#clock-cells = <1>;
clocks = <&psc1 1>, <&usb_refclkin>,
<&pll0_auxclk>;
clock-names = "fck", "usb_refclkin", "auxclk";
};
ehrpwm_tbclk: ehrpwm_tbclk {
compatible = "ti,da830-tbclksync";
#clock-cells = <0>;
clocks = <&psc1 17>;
clock-names = "fck";
};
div4p5_clk: div4.5 {
compatible = "ti,da830-div4p5ena";
#clock-cells = <0>;
clocks = <&pll0_pllout>;
clock-names = "pll0_pllout";
};
async1_clk: async1 {
compatible = "ti,da850-async1-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 3>, <&div4p5_clk>;
clock-names = "pll0_sysclk3", "div4.5";
};
async3_clk: async3 {
compatible = "ti,da850-async3-clksrc";
#clock-cells = <0>;
clocks = <&pll0_sysclk 2>, <&pll1_sysclk 2>;
clock-names = "pll0_sysclk2", "pll1_sysclk2";
};
};
edma0: edma@0 {
compatible = "ti,edma3-tpcc";
@ -277,18 +380,21 @@
#dma-cells = <2>;
ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
power-domains = <&psc0 0>;
};
edma0_tptc0: tptc@8000 {
compatible = "ti,edma3-tptc";
reg = <0x8000 0x400>;
interrupts = <13>;
interrupt-names = "edm3_tcerrint";
power-domains = <&psc0 1>;
};
edma0_tptc1: tptc@8400 {
compatible = "ti,edma3-tptc";
reg = <0x8400 0x400>;
interrupts = <32>;
interrupt-names = "edm3_tcerrint";
power-domains = <&psc0 2>;
};
edma1: edma@230000 {
compatible = "ti,edma3-tpcc";
@ -300,12 +406,14 @@
#dma-cells = <2>;
ti,tptcs = <&edma1_tptc0 7>;
power-domains = <&psc1 0>;
};
edma1_tptc0: tptc@238000 {
compatible = "ti,edma3-tptc";
reg = <0x238000 0x400>;
interrupts = <95>;
interrupt-names = "edm3_tcerrint";
power-domains = <&psc1 21>;
};
serial0: serial@42000 {
compatible = "ti,da830-uart", "ns16550a";
@ -313,6 +421,8 @@
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <25>;
clocks = <&psc0 9>;
power-domains = <&psc0 9>;
status = "disabled";
};
serial1: serial@10c000 {
@ -321,6 +431,8 @@
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <53>;
clocks = <&psc1 12>;
power-domains = <&psc1 12>;
status = "disabled";
};
serial2: serial@10d000 {
@ -329,6 +441,8 @@
reg-io-width = <4>;
reg-shift = <2>;
interrupts = <61>;
clocks = <&psc1 13>;
power-domains = <&psc1 13>;
status = "disabled";
};
rtc0: rtc@23000 {
@ -336,6 +450,8 @@
reg = <0x23000 0x1000>;
interrupts = <19
19>;
clocks = <&pll0_auxclk>;
clock-names = "int-clk";
status = "disabled";
};
i2c0: i2c@22000 {
@ -344,6 +460,7 @@
interrupts = <15>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&pll0_auxclk>;
status = "disabled";
};
i2c1: i2c@228000 {
@ -352,11 +469,21 @@
interrupts = <51>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&psc1 11>;
power-domains = <&psc1 11>;
status = "disabled";
};
clocksource: timer@20000 {
compatible = "ti,da830-timer";
reg = <0x20000 0x1000>;
interrupts = <12>, <13>;
interrupt-names = "tint12", "tint34";
clocks = <&pll0_auxclk>;
};
wdt: wdt@21000 {
compatible = "ti,davinci-wdt";
reg = <0x21000 0x1000>;
clocks = <&pll0_auxclk>;
status = "disabled";
};
mmc0: mmc@40000 {
@ -367,12 +494,14 @@
interrupts = <16>;
dmas = <&edma0 16 0>, <&edma0 17 0>;
dma-names = "rx", "tx";
clocks = <&psc0 5>;
status = "disabled";
};
vpif: video@217000 {
compatible = "ti,da850-vpif";
reg = <0x217000 0x1000>;
interrupts = <92>;
power-domains = <&psc1 9>;
status = "disabled";
/* VPIF capture port */
@ -395,6 +524,7 @@
interrupts = <72>;
dmas = <&edma1 28 0>, <&edma1 29 0>;
dma-names = "rx", "tx";
clocks = <&psc1 18>;
status = "disabled";
};
ehrpwm0: pwm@300000 {
@ -402,6 +532,9 @@
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x300000 0x2000>;
clocks = <&psc1 17>, <&ehrpwm_tbclk>;
clock-names = "fck", "tbclk";
power-domains = <&psc1 17>;
status = "disabled";
};
ehrpwm1: pwm@302000 {
@ -409,6 +542,9 @@
"ti,am33xx-ehrpwm";
#pwm-cells = <3>;
reg = <0x302000 0x2000>;
clocks = <&psc1 17>, <&ehrpwm_tbclk>;
clock-names = "fck", "tbclk";
power-domains = <&psc1 17>;
status = "disabled";
};
ecap0: ecap@306000 {
@ -416,6 +552,9 @@
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x306000 0x80>;
clocks = <&psc1 20>;
clock-names = "fck";
power-domains = <&psc1 20>;
status = "disabled";
};
ecap1: ecap@307000 {
@ -423,6 +562,9 @@
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x307000 0x80>;
clocks = <&psc1 20>;
clock-names = "fck";
power-domains = <&psc1 20>;
status = "disabled";
};
ecap2: ecap@308000 {
@ -430,6 +572,9 @@
"ti,am33xx-ecap";
#pwm-cells = <3>;
reg = <0x308000 0x80>;
clocks = <&psc1 20>;
clock-names = "fck";
power-domains = <&psc1 20>;
status = "disabled";
};
spi0: spi@41000 {
@ -442,6 +587,8 @@
interrupts = <20>;
dmas = <&edma0 14 0>, <&edma0 15 0>;
dma-names = "rx", "tx";
clocks = <&psc0 4>;
power-domains = <&psc0 4>;
status = "disabled";
};
spi1: spi@30e000 {
@ -454,6 +601,8 @@
interrupts = <56>;
dmas = <&edma0 18 0>, <&edma0 19 0>;
dma-names = "rx", "tx";
clocks = <&psc1 10>;
power-domains = <&psc1 10>;
status = "disabled";
};
usb0: usb@200000 {
@ -465,6 +614,8 @@
dr_mode = "otg";
phys = <&usb_phy 0>;
phy-names = "usb-phy";
clocks = <&psc1 1>;
clock-ranges;
status = "disabled";
#address-cells = <1>;
@ -488,6 +639,7 @@
interrupts = <58>;
#dma-cells = <2>;
#dma-channels = <4>;
power-domains = <&psc1 1>;
status = "okay";
};
};
@ -495,13 +647,31 @@
compatible = "ti,da850-ahci";
reg = <0x218000 0x2000>, <0x22c018 0x4>;
interrupts = <67>;
clocks = <&psc1 8>, <&sata_refclk>;
clock-names = "fck", "refclk";
status = "disabled";
};
pll1: clock-controller@21a000 {
compatible = "ti,da850-pll1";
reg = <0x21a000 0x1000>;
clocks = <&ref_clk>;
clock-names = "clksrc";
pll1_sysclk: sysclk {
#clock-cells = <1>;
};
pll1_obsclk: obsclk {
#clock-cells = <0>;
};
};
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x224000 0x1000>;
clocks = <&psc1 5>;
clock-names = "fck";
power-domains = <&psc1 5>;
status = "disabled";
};
eth0: ethernet@220000 {
@ -517,6 +687,8 @@
35
36
>;
clocks = <&psc1 5>;
power-domains = <&psc1 5>;
status = "disabled";
};
usb1: usb@225000 {
@ -525,6 +697,7 @@
interrupts = <59>;
phys = <&usb_phy 1>;
phy-names = "usb-phy";
clocks = <&psc1 2>;
status = "disabled";
};
gpio: gpio@226000 {
@ -532,16 +705,169 @@
gpio-controller;
#gpio-cells = <2>;
reg = <0x226000 0x1000>;
interrupts = <42 IRQ_TYPE_EDGE_BOTH
43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
interrupts = <42 43 44 45 46 47 48 49 50>;
ti,ngpio = <144>;
ti,davinci-gpio-unbanked = <0>;
clocks = <&psc1 3>;
clock-names = "gpio";
status = "disabled";
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&pmx_core 0 15 1>,
<&pmx_core 1 14 1>,
<&pmx_core 2 13 1>,
<&pmx_core 3 12 1>,
<&pmx_core 4 11 1>,
<&pmx_core 5 10 1>,
<&pmx_core 6 9 1>,
<&pmx_core 7 8 1>,
<&pmx_core 8 7 1>,
<&pmx_core 9 6 1>,
<&pmx_core 10 5 1>,
<&pmx_core 11 4 1>,
<&pmx_core 12 3 1>,
<&pmx_core 13 2 1>,
<&pmx_core 14 1 1>,
<&pmx_core 15 0 1>,
<&pmx_core 16 39 1>,
<&pmx_core 17 38 1>,
<&pmx_core 18 37 1>,
<&pmx_core 19 36 1>,
<&pmx_core 20 35 1>,
<&pmx_core 21 34 1>,
<&pmx_core 22 33 1>,
<&pmx_core 23 32 1>,
<&pmx_core 24 24 1>,
<&pmx_core 25 22 1>,
<&pmx_core 26 21 1>,
<&pmx_core 27 20 1>,
<&pmx_core 28 19 1>,
<&pmx_core 29 18 1>,
<&pmx_core 30 17 1>,
<&pmx_core 31 16 1>,
<&pmx_core 32 55 1>,
<&pmx_core 33 54 1>,
<&pmx_core 34 53 1>,
<&pmx_core 35 52 1>,
<&pmx_core 36 51 1>,
<&pmx_core 37 50 1>,
<&pmx_core 38 49 1>,
<&pmx_core 39 48 1>,
<&pmx_core 40 47 1>,
<&pmx_core 41 46 1>,
<&pmx_core 42 45 1>,
<&pmx_core 43 44 1>,
<&pmx_core 44 43 1>,
<&pmx_core 45 42 1>,
<&pmx_core 46 41 1>,
<&pmx_core 47 40 1>,
<&pmx_core 48 71 1>,
<&pmx_core 49 70 1>,
<&pmx_core 50 69 1>,
<&pmx_core 51 68 1>,
<&pmx_core 52 67 1>,
<&pmx_core 53 66 1>,
<&pmx_core 54 65 1>,
<&pmx_core 55 64 1>,
<&pmx_core 56 63 1>,
<&pmx_core 57 62 1>,
<&pmx_core 58 61 1>,
<&pmx_core 59 60 1>,
<&pmx_core 60 59 1>,
<&pmx_core 61 58 1>,
<&pmx_core 62 57 1>,
<&pmx_core 63 56 1>,
<&pmx_core 64 87 1>,
<&pmx_core 65 86 1>,
<&pmx_core 66 85 1>,
<&pmx_core 67 84 1>,
<&pmx_core 68 83 1>,
<&pmx_core 69 82 1>,
<&pmx_core 70 81 1>,
<&pmx_core 71 80 1>,
<&pmx_core 72 70 1>,
<&pmx_core 73 78 1>,
<&pmx_core 74 77 1>,
<&pmx_core 75 76 1>,
<&pmx_core 76 75 1>,
<&pmx_core 77 74 1>,
<&pmx_core 78 73 1>,
<&pmx_core 79 72 1>,
<&pmx_core 80 103 1>,
<&pmx_core 81 102 1>,
<&pmx_core 82 101 1>,
<&pmx_core 83 100 1>,
<&pmx_core 84 99 1>,
<&pmx_core 85 98 1>,
<&pmx_core 86 97 1>,
<&pmx_core 87 96 1>,
<&pmx_core 88 95 1>,
<&pmx_core 89 94 1>,
<&pmx_core 90 93 1>,
<&pmx_core 91 92 1>,
<&pmx_core 92 91 1>,
<&pmx_core 93 90 1>,
<&pmx_core 94 89 1>,
<&pmx_core 95 88 1>,
<&pmx_core 96 158 1>,
<&pmx_core 97 157 1>,
<&pmx_core 98 156 1>,
<&pmx_core 99 155 1>,
<&pmx_core 100 154 1>,
<&pmx_core 101 129 1>,
<&pmx_core 102 113 1>,
<&pmx_core 103 112 1>,
<&pmx_core 104 111 1>,
<&pmx_core 105 110 1>,
<&pmx_core 106 109 1>,
<&pmx_core 107 108 1>,
<&pmx_core 108 107 1>,
<&pmx_core 109 106 1>,
<&pmx_core 110 105 1>,
<&pmx_core 111 104 1>,
<&pmx_core 112 145 1>,
<&pmx_core 113 144 1>,
<&pmx_core 114 143 1>,
<&pmx_core 115 142 1>,
<&pmx_core 116 141 1>,
<&pmx_core 117 140 1>,
<&pmx_core 118 139 1>,
<&pmx_core 119 138 1>,
<&pmx_core 120 137 1>,
<&pmx_core 121 136 1>,
<&pmx_core 122 135 1>,
<&pmx_core 123 134 1>,
<&pmx_core 124 133 1>,
<&pmx_core 125 132 1>,
<&pmx_core 126 131 1>,
<&pmx_core 127 130 1>,
<&pmx_core 128 159 1>,
<&pmx_core 129 31 1>,
<&pmx_core 130 30 1>,
<&pmx_core 131 20 1>,
<&pmx_core 132 28 1>,
<&pmx_core 133 27 1>,
<&pmx_core 134 26 1>,
<&pmx_core 135 23 1>,
<&pmx_core 136 153 1>,
<&pmx_core 137 152 1>,
<&pmx_core 138 151 1>,
<&pmx_core 139 150 1>,
<&pmx_core 140 149 1>,
<&pmx_core 141 148 1>,
<&pmx_core 142 147 1>,
<&pmx_core 143 146 1>;
};
psc1: clock-controller@227000 {
compatible = "ti,da850-psc1";
reg = <0x227000 0x1000>;
#clock-cells = <1>;
#power-domain-cells = <1>;
clocks = <&pll0_sysclk 2>, <&pll0_sysclk 4>,
<&async3_clk>;
clock-names = "pll0_sysclk2", "pll0_sysclk4", "async3";
assigned-clocks = <&async3_clk>;
assigned-clock-parents = <&pll1_sysclk 2>;
};
pinconf: pin-controller@22c00c {
compatible = "ti,da850-pupd";
@ -556,6 +882,7 @@
reg-names = "mpu", "dat";
interrupts = <54>;
interrupt-names = "common";
power-domains = <&psc1 7>;
status = "disabled";
dmas = <&edma0 1 1>,
<&edma0 0 1>;
@ -567,6 +894,9 @@
reg = <0x213000 0x1000>;
interrupts = <52>;
max-pixelclock = <37500>;
clocks = <&psc1 16>;
clock-names = "fck";
power-domains = <&psc1 16>;
status = "disabled";
};
};
@ -578,6 +908,9 @@
reg = <0x68000000 0x00008000>;
ranges = <0 0 0x60000000 0x08000000
1 0 0x68000000 0x00008000>;
clocks = <&psc0 3>;
clock-names = "aemif";
clock-ranges;
status = "disabled";
};
memctrl: memory-controller@b0000000 {

4
arch/arm/dts/dm816x.dtsi
View File

@ -90,8 +90,6 @@
dm816x_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x50a>;
#address-cells = <1>;
#size-cells = <0>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xf>;
@ -127,8 +125,6 @@
};
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {

15
arch/arm/dts/logicpd-som-lv-35xx-devkit.dts
View File

@ -15,18 +15,3 @@
model = "LogicPD Zoom OMAP35xx SOM-LV Development Kit";
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3";
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb2_2_pins>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3430_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3430_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3430_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3430_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3430_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3430_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};

15
arch/arm/dts/logicpd-som-lv-37xx-devkit.dts
View File

@ -15,18 +15,3 @@
model = "LogicPD Zoom DM3730 SOM-LV Development Kit";
compatible = "logicpd,dm3730-som-lv-devkit", "ti,omap3630", "ti,omap3";
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb2_2_pins>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};

43
arch/arm/dts/logicpd-som-lv.dtsi
View File

@ -129,7 +129,7 @@
};
&mmc3 {
interrupts-extended = <&intc 94>;
interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
pinctrl-0 = <&mmc3_pins &wl127x_gpio>;
pinctrl-names = "default";
vmmc-supply = <&wl12xx_vmmc>;
@ -232,20 +232,6 @@
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
>;
};
tsc2004_pins: pinmux_tsc2004_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */
@ -267,6 +253,33 @@
OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE4) /* sys_boot1.gpio_3 */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21be, PIN_INPUT | MUX_MODE0) /* i2c2_scl */
OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT | MUX_MODE0) /* i2c3_scl */
OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT | MUX_MODE0) /* i2c3_sda */
>;
};
};
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb2_2_pins>;
hsusb2_2_pins: pinmux_hsusb2_2_pins {
pinctrl-single,pins = <
OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
>;
};
};
&uart2 {

2
arch/arm/dts/logicpd-torpedo-37xx-devkit.dts
View File

@ -35,7 +35,7 @@
* jumpering combinations for the long run.
*/
&mmc3 {
interrupts-extended = <&intc 94 &omap3_pmx_core2 0x46>;
interrupts-extended = <&intc 94 &omap3_pmx_core 0x136>;
pinctrl-0 = <&mmc3_pins &mmc3_core2_pins>;
pinctrl-names = "default";
vmmc-supply = <&wl12xx_vmmc>;

8
arch/arm/dts/stm32mp157c-ed1.dts
View File

@ -365,6 +365,14 @@
usb33d-supply = <&usb33>;
};
&hwspinlock {
status = "okay";
};
&pinctrl {
hwlocks = <&hwspinlock 0>;
};
&usbphyc_port0 {
phy-supply = <&vdd_usb>;
vdda1v1-supply = <&reg11>;

9
arch/arm/dts/stm32mp157c.dtsi
View File

@ -690,6 +690,15 @@
status = "disabled";
};
hwspinlock: hwspinlock@4c000000 {
compatible = "st,stm32-hwspinlock";
#hwlock-cells = <1>;
reg = <0x4c000000 0x400>;
clocks = <&rcc HSEM>;
clock-names = "hwspinlock";
status = "disabled";
};
rcc: rcc@50000000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;

5
arch/arm/include/asm/arch-stm32/gpio.h
View File

@ -7,6 +7,8 @@
#ifndef _GPIO_H_
#define _GPIO_H_
#define STM32_GPIOS_PER_BANK 16
enum stm32_gpio_port {
STM32_GPIO_PORT_A = 0,
STM32_GPIO_PORT_B,
@ -109,6 +111,9 @@ struct stm32_gpio_regs {
struct stm32_gpio_priv {
struct stm32_gpio_regs *regs;
unsigned int gpio_range;
};
int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
#endif /* _GPIO_H_ */

13
arch/arm/include/asm/io.h
View File

@ -160,7 +160,12 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define in_be32(a) in_arch(l,be32,a)
#define in_be16(a) in_arch(w,be16,a)
#define out_32(a,v) __raw_writel(v,a)
#define out_16(a,v) __raw_writew(v,a)
#define out_8(a,v) __raw_writeb(v,a)
#define in_32(a) __raw_readl(a)
#define in_16(a) __raw_readw(a)
#define in_8(a) __raw_readb(a)
#define clrbits(type, addr, clear) \
@ -180,6 +185,10 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define setbits_le32(addr, set) setbits(le32, addr, set)
#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
#define clrbits_32(addr, clear) clrbits(32, addr, clear)
#define setbits_32(addr, set) setbits(32, addr, set)
#define clrsetbits_32(addr, clear, set) clrsetbits(32, addr, clear, set)
#define clrbits_be16(addr, clear) clrbits(be16, addr, clear)
#define setbits_be16(addr, set) setbits(be16, addr, set)
#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
@ -188,6 +197,10 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
#define setbits_le16(addr, set) setbits(le16, addr, set)
#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
#define clrbits_16(addr, clear) clrbits(16, addr, clear)
#define setbits_16(addr, set) setbits(16, addr, set)
#define clrsetbits_16(addr, clear, set) clrsetbits(16, addr, clear, set)
#define clrbits_8(addr, clear) clrbits(8, addr, clear)
#define setbits_8(addr, set) setbits(8, addr, set)
#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)

10
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
View File

@ -48,3 +48,13 @@ SECTIONS
__bss_end = .;
} >.sdram
}
#if defined(CONFIG_SPL_MAX_SIZE)
ASSERT(__image_copy_end - __start < (CONFIG_SPL_MAX_SIZE), \
"SPL image too big");
#endif
#if defined(CONFIG_SPL_BSS_MAX_SIZE)
ASSERT(__bss_end - __bss_start < (CONFIG_SPL_BSS_MAX_SIZE), \
"SPL image BSS too big");
#endif

6
arch/arm/mach-stm32mp/include/mach/gpio.h
View File

@ -8,6 +8,8 @@
#define _STM32_GPIO_H_
#include <asm/gpio.h>
#define STM32_GPIOS_PER_BANK 16
enum stm32_gpio_port {
STM32_GPIO_PORT_A = 0,
STM32_GPIO_PORT_B,
@ -110,5 +112,9 @@ struct stm32_gpio_regs {
struct stm32_gpio_priv {
struct stm32_gpio_regs *regs;
unsigned int gpio_range;
};
int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
#endif /* _STM32_GPIO_H_ */

12
arch/sandbox/dts/test.dts
View File

@ -742,6 +742,18 @@
pinctrl {
compatible = "sandbox,pinctrl";
};
hwspinlock@0 {
compatible = "sandbox,hwspinlock";
};
dma: dma {
compatible = "sandbox,dma";
#dma-cells = <1>;
dmas = <&dma 0>, <&dma 1>, <&dma 2>;
dma-names = "m2m", "tx0", "rx0";
};
};
#include "sandbox_pmic.dtsi"

1
arch/sandbox/include/asm/state.h
View File

@ -101,6 +101,7 @@ struct sandbox_state {
ulong next_tag; /* Next address tag to allocate */
struct list_head mapmem_head; /* struct sandbox_mapmem_entry */
bool hwspinlock; /* Hardware Spinlock status */
};
/* Minimum space we guarantee in the state FDT when calling read/write*/

5
board/ti/ks2_evm/board.c
View File

@ -59,6 +59,11 @@ int dram_init(void)
return 0;
}
struct image_header *spl_get_load_buffer(ssize_t offset, size_t size)
{
return (struct image_header *)(CONFIG_SYS_TEXT_BASE);
}
int board_init(void)
{
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;

6
cmd/bootmenu.c
View File

@ -351,6 +351,12 @@ static struct bootmenu_data *bootmenu_create(int delay)
}
menu->count = i;
if ((menu->active >= menu->count)||(menu->active < 0)) { //ensure active menuitem is inside menu
printf("active menuitem (%d) is outside menu (0..%d)\n",menu->active,menu->count-1);
menu->active=0;
}
return menu;
cleanup:

22
common/main.c
View File

@ -24,15 +24,15 @@ static void run_preboot_environment_command(void)
p = env_get("preboot");
if (p != NULL) {
# ifdef CONFIG_AUTOBOOT_KEYED
int prev = disable_ctrlc(1); /* disable Control C checking */
# endif
int prev = 0;
if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
prev = disable_ctrlc(1); /* disable Ctrl-C checking */
run_command_list(p, -1, 0);
# ifdef CONFIG_AUTOBOOT_KEYED
disable_ctrlc(prev); /* restore Control C checking */
# endif
if (IS_ENABLED(CONFIG_AUTOBOOT_KEYED))
disable_ctrlc(prev); /* restore Ctrl-C checking */
}
#endif /* CONFIG_PREBOOT */
}
@ -44,17 +44,15 @@ void main_loop(void)
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
#ifdef CONFIG_VERSION_VARIABLE
env_set("ver", version_string); /* set version variable */
#endif /* CONFIG_VERSION_VARIABLE */
if (IS_ENABLED(CONFIG_VERSION_VARIABLE))
env_set("ver", version_string); /* set version variable */
cli_init();
run_preboot_environment_command();
#if defined(CONFIG_UPDATE_TFTP)
update_tftp(0UL, NULL, NULL);
#endif /* CONFIG_UPDATE_TFTP */
if (IS_ENABLED(CONFIG_UPDATE_TFTP))
update_tftp(0UL, NULL, NULL);
s = bootdelay_process();
if (cli_process_fdt(&s))

1
configs/am335x_hs_evm_uart_defconfig
View File

@ -19,7 +19,6 @@ CONFIG_ARCH_MISC_INIT=y
# CONFIG_SPL_EXT_SUPPORT is not set
CONFIG_SPL_MTD_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
# CONFIG_SPL_YMODEM_SUPPORT is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set

5
configs/am335x_pdu001_defconfig
View File

@ -18,6 +18,7 @@ CONFIG_SPL_I2C_SUPPORT=y
# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR=" "
@ -37,6 +38,10 @@ CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
CONFIG_SPL_DM=y
CONFIG_DM_GPIO=y
CONFIG_DM_I2C=y
CONFIG_BLK=y
CONFIG_SPL_BLK=y
CONFIG_DM_MMC=y
CONFIG_SPL_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_MMC_SDHCI=y
CONFIG_PINCTRL=y

2
configs/bcm968580_ram_defconfig
View File

@ -30,7 +30,7 @@ CONFIG_SPECIFY_CONSOLE_INDEX=y
CONFIG_CONS_INDEX=0
CONFIG_DM_SERIAL=y
CONFIG_SERIAL_SEARCH_ALL=y
CONFIG_BCM6858_SERIAL=y
CONFIG_BCM6345_SERIAL=y
CONFIG_SYSRESET=y
CONFIG_REGEX=y
# CONFIG_GENERATE_SMBIOS_TABLE is not set

5
configs/sandbox_defconfig
View File

@ -96,6 +96,8 @@ CONFIG_BOARD=y
CONFIG_BOARD_SANDBOX=y
CONFIG_PM8916_GPIO=y
CONFIG_SANDBOX_GPIO=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_SANDBOX=y
CONFIG_DM_I2C_COMPAT=y
CONFIG_I2C_CROS_EC_TUNNEL=y
CONFIG_I2C_CROS_EC_LDO=y
@ -216,3 +218,6 @@ CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
CONFIG_UT_OVERLAY=y
CONFIG_DMA=y
CONFIG_DMA_CHANNELS=y
CONFIG_SANDBOX_DMA=y

2
configs/stm32f746-disco_defconfig
View File

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_STM32=y
CONFIG_SYS_TEXT_BASE=0x08008000
CONFIG_SYS_MALLOC_F_LEN=0xC00
CONFIG_SYS_MALLOC_F_LEN=0xE00
CONFIG_STM32F7=y
CONFIG_TARGET_STM32F746_DISCO=y
CONFIG_ENV_VARS_UBOOT_CONFIG=y

2
configs/stm32mp15_basic_defconfig
View File

@ -32,6 +32,8 @@ CONFIG_CMD_EXT4_WRITE=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1"
CONFIG_STM32_ADC=y
CONFIG_DM_HWSPINLOCK=y
CONFIG_HWSPINLOCK_STM32=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_STM32F7=y
CONFIG_LED=y

2
drivers/Kconfig
View File

@ -40,6 +40,8 @@ source "drivers/fpga/Kconfig"
source "drivers/gpio/Kconfig"
source "drivers/hwspinlock/Kconfig"
source "drivers/i2c/Kconfig"
source "drivers/input/Kconfig"

1
drivers/Makefile
View File

@ -113,4 +113,5 @@ obj-$(CONFIG_W1) += w1/
obj-$(CONFIG_W1_EEPROM) += w1-eeprom/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock/
endif

4
drivers/clk/clk-uclass.c
View File

@ -243,6 +243,10 @@ int clk_set_defaults(struct udevice *dev)
{
int ret;
/* If this not in SPL and pre-reloc state, don't take any action. */
if (!(IS_ENABLED(CONFIG_SPL_BUILD) || (gd->flags & GD_FLG_RELOC)))
return 0;
debug("%s(%s)\n", __func__, dev_read_name(dev));
ret = clk_set_default_parents(dev);

3
drivers/clk/clk_stm32mp1.c
View File

@ -104,6 +104,7 @@
#define RCC_MP_APB2ENSETR 0XA08
#define RCC_MP_APB3ENSETR 0xA10
#define RCC_MP_AHB2ENSETR 0xA18
#define RCC_MP_AHB3ENSETR 0xA20
#define RCC_MP_AHB4ENSETR 0xA28
/* used for most of SELR register */
@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),

14
drivers/dma/Kconfig
View File

@ -12,6 +12,20 @@ config DMA
buses that is used to transfer data to and from memory.
The uclass interface is defined in include/dma.h.
config DMA_CHANNELS
bool "Enable DMA channels support"
depends on DMA
help
Enable channels support for DMA. Some DMA controllers have multiple
channels which can either transfer data to/from different devices.
config SANDBOX_DMA
bool "Enable the sandbox DMA test driver"
depends on DMA && DMA_CHANNELS && SANDBOX
help
Enable support for a test DMA uclass implementation. It stimulates
DMA transfer by simple copying data between channels.
config TI_EDMA3
bool "TI EDMA3 driver"
help

1
drivers/dma/Makefile
View File

@ -8,6 +8,7 @@ obj-$(CONFIG_DMA) += dma-uclass.o
obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
obj-$(CONFIG_APBH_DMA) += apbh_dma.o
obj-$(CONFIG_FSL_DMA) += fsl_dma.o
obj-$(CONFIG_SANDBOX_DMA) += sandbox-dma-test.o
obj-$(CONFIG_TI_KSNAV) += keystone_nav.o keystone_nav_cfg.o
obj-$(CONFIG_TI_EDMA3) += ti-edma3.o
obj-$(CONFIG_DMA_LPC32XX) += lpc32xx_dma.o

183
drivers/dma/dma-uclass.c
View File

@ -2,19 +2,192 @@
/*
* Direct Memory Access U-Class driver
*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
* Written by Mugunthan V N <mugunthanvnm@ti.com>
*
* Author: Mugunthan V N <mugunthanvnm@ti.com>
*/
#include <common.h>
#include <dma.h>
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/device-internal.h>
#include <dm/read.h>
#include <dma-uclass.h>
#include <dt-structs.h>
#include <errno.h>
#ifdef CONFIG_DMA_CHANNELS
static inline struct dma_ops *dma_dev_ops(struct udevice *dev)
{
return (struct dma_ops *)dev->driver->ops;
}
# if CONFIG_IS_ENABLED(OF_CONTROL)
static int dma_of_xlate_default(struct dma *dma,
struct ofnode_phandle_args *args)
{
debug("%s(dma=%p)\n", __func__, dma);
if (args->args_count > 1) {
pr_err("Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
if (args->args_count)
dma->id = args->args[0];
else
dma->id = 0;
return 0;
}
int dma_get_by_index(struct udevice *dev, int index, struct dma *dma)
{
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_dma;
const struct dma_ops *ops;
debug("%s(dev=%p, index=%d, dma=%p)\n", __func__, dev, index, dma);
assert(dma);
dma->dev = NULL;
ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, index,
&args);
if (ret) {
pr_err("%s: dev_read_phandle_with_args failed: err=%d\n",
__func__, ret);
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_DMA, args.node, &dev_dma);
if (ret) {
pr_err("%s: uclass_get_device_by_ofnode failed: err=%d\n",
__func__, ret);
return ret;
}
dma->dev = dev_dma;
ops = dma_dev_ops(dev_dma);
if (ops->of_xlate)
ret = ops->of_xlate(dma, &args);
else
ret = dma_of_xlate_default(dma, &args);
if (ret) {
pr_err("of_xlate() failed: %d\n", ret);
return ret;
}
return dma_request(dev_dma, dma);
}
int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma)
{
int index;
debug("%s(dev=%p, name=%s, dma=%p)\n", __func__, dev, name, dma);
dma->dev = NULL;
index = dev_read_stringlist_search(dev, "dma-names", name);
if (index < 0) {
pr_err("dev_read_stringlist_search() failed: %d\n", index);
return index;
}
return dma_get_by_index(dev, index, dma);
}
# endif /* OF_CONTROL */
int dma_request(struct udevice *dev, struct dma *dma)
{
struct dma_ops *ops = dma_dev_ops(dev);
debug("%s(dev=%p, dma=%p)\n", __func__, dev, dma);
dma->dev = dev;
if (!ops->request)
return 0;
return ops->request(dma);
}
int dma_free(struct dma *dma)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->free)
return 0;
return ops->free(dma);
}
int dma_enable(struct dma *dma)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->enable)
return -ENOSYS;
return ops->enable(dma);
}
int dma_disable(struct dma *dma)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->disable)
return -ENOSYS;
return ops->disable(dma);
}
int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->prepare_rcv_buf)
return -1;
return ops->prepare_rcv_buf(dma, dst, size);
}
int dma_receive(struct dma *dma, void **dst, void *metadata)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->receive)
return -ENOSYS;
return ops->receive(dma, dst, metadata);
}
int dma_send(struct dma *dma, void *src, size_t len, void *metadata)
{
struct dma_ops *ops = dma_dev_ops(dma->dev);
debug("%s(dma=%p)\n", __func__, dma);
if (!ops->send)
return -ENOSYS;
return ops->send(dma, src, len, metadata);
}
#endif /* CONFIG_DMA_CHANNELS */
int dma_get_device(u32 transfer_type, struct udevice **devp)
{
struct udevice *dev;

282
drivers/dma/sandbox-dma-test.c Normal file
View File

@ -0,0 +1,282 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Direct Memory Access U-Class Simulation driver
*
* Copyright (C) 2018 Texas Instruments Incorporated <www.ti.com>
*
* Author: Grygorii Strashko <grygorii.strashko@ti.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/read.h>
#include <dma-uclass.h>
#include <dt-structs.h>
#include <errno.h>
#define SANDBOX_DMA_CH_CNT 3
#define SANDBOX_DMA_BUF_SIZE 1024
struct sandbox_dma_chan {
struct sandbox_dma_dev *ud;
char name[20];
u32 id;
enum dma_direction dir;
bool in_use;
bool enabled;
};
struct sandbox_dma_dev {
struct device *dev;
u32 ch_count;
struct sandbox_dma_chan channels[SANDBOX_DMA_CH_CNT];
uchar buf[SANDBOX_DMA_BUF_SIZE];
uchar *buf_rx;
size_t data_len;
u32 meta;
};
static int sandbox_dma_transfer(struct udevice *dev, int direction,
void *dst, void *src, size_t len)
{
memcpy(dst, src, len);
return 0;
}
static int sandbox_dma_of_xlate(struct dma *dma,
struct ofnode_phandle_args *args)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
debug("%s(dma id=%u)\n", __func__, args->args[0]);
if (args->args[0] >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
dma->id = args->args[0];
uc = &ud->channels[dma->id];
if (dma->id == 1)
uc->dir = DMA_MEM_TO_DEV;
else if (dma->id == 2)
uc->dir = DMA_DEV_TO_MEM;
else
uc->dir = DMA_MEM_TO_MEM;
debug("%s(dma id=%lu dir=%d)\n", __func__, dma->id, uc->dir);
return 0;
}
static int sandbox_dma_request(struct dma *dma)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
if (dma->id >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
uc = &ud->channels[dma->id];
if (uc->in_use)
return -EBUSY;
uc->in_use = true;
debug("%s(dma id=%lu in_use=%d)\n", __func__, dma->id, uc->in_use);
return 0;
}
static int sandbox_dma_free(struct dma *dma)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
if (dma->id >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
uc = &ud->channels[dma->id];
if (!uc->in_use)
return -EINVAL;
uc->in_use = false;
ud->buf_rx = NULL;
ud->data_len = 0;
debug("%s(dma id=%lu in_use=%d)\n", __func__, dma->id, uc->in_use);
return 0;
}
static int sandbox_dma_enable(struct dma *dma)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
if (dma->id >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
uc = &ud->channels[dma->id];
if (!uc->in_use)
return -EINVAL;
if (uc->enabled)
return -EINVAL;
uc->enabled = true;
debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled);
return 0;
}
static int sandbox_dma_disable(struct dma *dma)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
if (dma->id >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
uc = &ud->channels[dma->id];
if (!uc->in_use)
return -EINVAL;
if (!uc->enabled)
return -EINVAL;
uc->enabled = false;
debug("%s(dma id=%lu enabled=%d)\n", __func__, dma->id, uc->enabled);
return 0;
}
static int sandbox_dma_send(struct dma *dma,
void *src, size_t len, void *metadata)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
if (dma->id >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
if (!src || !metadata)
return -EINVAL;
debug("%s(dma id=%lu)\n", __func__, dma->id);
uc = &ud->channels[dma->id];
if (uc->dir != DMA_MEM_TO_DEV)
return -EINVAL;
if (!uc->in_use)
return -EINVAL;
if (!uc->enabled)
return -EINVAL;
if (len >= SANDBOX_DMA_BUF_SIZE)
return -EINVAL;
memcpy(ud->buf, src, len);
ud->data_len = len;
ud->meta = *((u32 *)metadata);
debug("%s(dma id=%lu len=%zu meta=%08x)\n",
__func__, dma->id, len, ud->meta);
return 0;
}
static int sandbox_dma_receive(struct dma *dma, void **dst, void *metadata)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
struct sandbox_dma_chan *uc;
if (dma->id >= SANDBOX_DMA_CH_CNT)
return -EINVAL;
if (!dst || !metadata)
return -EINVAL;
uc = &ud->channels[dma->id];
if (uc->dir != DMA_DEV_TO_MEM)
return -EINVAL;
if (!uc->in_use)
return -EINVAL;
if (!uc->enabled)
return -EINVAL;
if (!ud->data_len)
return 0;
if (ud->buf_rx) {
memcpy(ud->buf_rx, ud->buf, ud->data_len);
*dst = ud->buf_rx;
} else {
memcpy(*dst, ud->buf, ud->data_len);
}
*((u32 *)metadata) = ud->meta;
debug("%s(dma id=%lu len=%zu meta=%08x %p)\n",
__func__, dma->id, ud->data_len, ud->meta, *dst);
return ud->data_len;
}
static int sandbox_dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
{
struct sandbox_dma_dev *ud = dev_get_priv(dma->dev);
ud->buf_rx = dst;
return 0;
}
static const struct dma_ops sandbox_dma_ops = {
.transfer = sandbox_dma_transfer,
.of_xlate = sandbox_dma_of_xlate,
.request = sandbox_dma_request,
.free = sandbox_dma_free,
.enable = sandbox_dma_enable,
.disable = sandbox_dma_disable,
.send = sandbox_dma_send,
.receive = sandbox_dma_receive,
.prepare_rcv_buf = sandbox_dma_prepare_rcv_buf,
};
static int sandbox_dma_probe(struct udevice *dev)
{
struct dma_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct sandbox_dma_dev *ud = dev_get_priv(dev);
int i, ret = 0;
uc_priv->supported = DMA_SUPPORTS_MEM_TO_MEM |
DMA_SUPPORTS_MEM_TO_DEV |
DMA_SUPPORTS_DEV_TO_MEM;
ud->ch_count = SANDBOX_DMA_CH_CNT;
ud->buf_rx = NULL;
ud->meta = 0;
ud->data_len = 0;
pr_err("Number of channels: %u\n", ud->ch_count);
for (i = 0; i < ud->ch_count; i++) {
struct sandbox_dma_chan *uc = &ud->channels[i];
uc->ud = ud;
uc->id = i;
sprintf(uc->name, "DMA chan%d\n", i);
uc->in_use = false;
uc->enabled = false;
}
return ret;
}
static const struct udevice_id sandbox_dma_ids[] = {
{ .compatible = "sandbox,dma" },
{ }
};
U_BOOT_DRIVER(sandbox_dma) = {
.name = "sandbox-dma",
.id = UCLASS_DMA,
.of_match = sandbox_dma_ids,
.ops = &sandbox_dma_ops,
.probe = sandbox_dma_probe,
.priv_auto_alloc_size = sizeof(struct sandbox_dma_dev),
};

2
drivers/dma/ti-edma3.c
View File

@ -11,7 +11,7 @@
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <dma.h>
#include <dma-uclass.h>
#include <asm/omap_common.h>
#include <asm/ti-common/ti-edma3.h>

104
drivers/gpio/stm32f7_gpio.c
View File

@ -15,17 +15,45 @@
#include <linux/errno.h>
#include <linux/io.h>
#define STM32_GPIOS_PER_BANK 16
#define MODE_BITS(gpio_pin) (gpio_pin * 2)
#define MODE_BITS_MASK 3
#define BSRR_BIT(gpio_pin, value) BIT(gpio_pin + (value ? 0 : 16))
/*
* convert gpio offset to gpio index taking into account gpio holes
* into gpio bank
*/
int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
int idx = 0;
int i;
for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
if (priv->gpio_range & BIT(i)) {
if (idx == offset)
return idx;
idx++;
}
}
/* shouldn't happen */
return -EINVAL;
}
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int bits_index = MODE_BITS(offset);
int mask = MODE_BITS_MASK << bits_index;
int bits_index;
int mask;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
bits_index = MODE_BITS(idx);
mask = MODE_BITS_MASK << bits_index;
clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_IN << bits_index);
@ -37,12 +65,20 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int bits_index = MODE_BITS(offset);
int mask = MODE_BITS_MASK << bits_index;
int bits_index;
int mask;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
bits_index = MODE_BITS(idx);
mask = MODE_BITS_MASK << bits_index;
clrsetbits_le32(&regs->moder, mask, STM32_GPIO_MODE_OUT << bits_index);
writel(BSRR_BIT(offset, value), &regs->bsrr);
writel(BSRR_BIT(idx, value), &regs->bsrr);
return 0;
}
@ -51,16 +87,26 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
return readl(&regs->idr) & BIT(offset) ? 1 : 0;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
return readl(&regs->idr) & BIT(idx) ? 1 : 0;
}
static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
writel(BSRR_BIT(offset, value), &regs->bsrr);
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
writel(BSRR_BIT(idx, value), &regs->bsrr);
return 0;
}
@ -69,10 +115,18 @@ static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int bits_index = MODE_BITS(offset);
int mask = MODE_BITS_MASK << bits_index;
int bits_index;
int mask;
int idx;
u32 mode;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
bits_index = MODE_BITS(idx);
mask = MODE_BITS_MASK << bits_index;
mode = (readl(&regs->moder) & mask) >> bits_index;
if (mode == STM32_GPIO_MODE_OUT)
return GPIOF_OUTPUT;
@ -96,8 +150,12 @@ static int gpio_stm32_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct ofnode_phandle_args args;
struct clk clk;
fdt_addr_t addr;
const char *name;
int ret;
int i;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@ -108,14 +166,25 @@ static int gpio_stm32_probe(struct udevice *dev)
if (!name)
return -EINVAL;
uc_priv->bank_name = name;
uc_priv->gpio_count = dev_read_u32_default(dev, "ngpios",
STM32_GPIOS_PER_BANK);
debug("%s, addr = 0x%p, bank_name = %s\n", __func__, (u32 *)priv->regs,
uc_priv->bank_name);
#ifdef CONFIG_CLK
struct clk clk;
int ret;
i = 0;
ret = dev_read_phandle_with_args(dev, "gpio-ranges",
NULL, 3, i, &args);
while (ret != -ENOENT) {
priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
args.args[0]);
uc_priv->gpio_count += args.args[2];
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
++i, &args);
}
dev_dbg(dev, "addr = 0x%p bank_name = %s gpio_count = %d gpio_range = 0x%x\n",
(u32 *)priv->regs, uc_priv->bank_name, uc_priv->gpio_count,
priv->gpio_range);
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
@ -127,7 +196,6 @@ static int gpio_stm32_probe(struct udevice *dev)
return ret;
}
debug("clock enabled for device %s\n", dev->name);
#endif
return 0;
}

24
drivers/hwspinlock/Kconfig Normal file
View File

@ -0,0 +1,24 @@
menu "Hardware Spinlock Support"
config DM_HWSPINLOCK
bool "Enable U-Boot hardware spinlock support"
help
This option enables U-Boot hardware spinlock support
config HWSPINLOCK_SANDBOX
bool "Enable Hardware Spinlock support for Sandbox"
depends on SANDBOX && DM_HWSPINLOCK
help
Enable hardware spinlock support in Sandbox. This is a dummy device that
can be probed and support all the methods of HWSPINLOCK, but does not
really do anything.
config HWSPINLOCK_STM32
bool "Enable Hardware Spinlock support for STM32"
depends on ARCH_STM32MP && DM_HWSPINLOCK
help
Enable hardware spinlock support in STM32MP. Hardware spinlocks are
hardware mutex which provide a synchronisation mechanism for the
various processors on the SoC.
endmenu

7
drivers/hwspinlock/Makefile Normal file
View File

@ -0,0 +1,7 @@
# SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
#
# Copyright (C) 2018, STMicroelectronics - All Rights Reserved
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock-uclass.o
obj-$(CONFIG_HWSPINLOCK_SANDBOX) += sandbox_hwspinlock.o
obj-$(CONFIG_HWSPINLOCK_STM32) += stm32_hwspinlock.o

144
drivers/hwspinlock/hwspinlock-uclass.c Normal file
View File

@ -0,0 +1,144 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <hwspinlock.h>
#include <dm/device-internal.h>
static inline const struct hwspinlock_ops *
hwspinlock_dev_ops(struct udevice *dev)
{
return (const struct hwspinlock_ops *)dev->driver->ops;
}
static int hwspinlock_of_xlate_default(struct hwspinlock *hws,
struct ofnode_phandle_args *args)
{
if (args->args_count > 1) {
debug("Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
if (args->args_count)
hws->id = args->args[0];
else
hws->id = 0;
return 0;
}
int hwspinlock_get_by_index(struct udevice *dev, int index,
struct hwspinlock *hws)
{
int ret;
struct ofnode_phandle_args args;
struct udevice *dev_hws;
const struct hwspinlock_ops *ops;
assert(hws);
hws->dev = NULL;
ret = dev_read_phandle_with_args(dev, "hwlocks", "#hwlock-cells", 1,
index, &args);
if (ret) {
dev_dbg(dev, "%s: dev_read_phandle_with_args: err=%d\n",
__func__, ret);
return ret;
}
ret = uclass_get_device_by_ofnode(UCLASS_HWSPINLOCK,
args.node, &dev_hws);
if (ret) {
dev_dbg(dev,
"%s: uclass_get_device_by_of_offset failed: err=%d\n",
__func__, ret);
return ret;
}
hws->dev = dev_hws;
ops = hwspinlock_dev_ops(dev_hws);
if (ops->of_xlate)
ret = ops->of_xlate(hws, &args);
else
ret = hwspinlock_of_xlate_default(hws, &args);
if (ret)
dev_dbg(dev, "of_xlate() failed: %d\n", ret);
return ret;
}
int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout)
{
const struct hwspinlock_ops *ops;
ulong start;
int ret;
assert(hws);
if (!hws->dev)
return -EINVAL;
ops = hwspinlock_dev_ops(hws->dev);
if (!ops->lock)
return -ENOSYS;
start = get_timer(0);
do {
ret = ops->lock(hws->dev, hws->id);
if (!ret)
return ret;
if (ops->relax)
ops->relax(hws->dev);
} while (get_timer(start) < timeout);
return -ETIMEDOUT;
}
int hwspinlock_unlock(struct hwspinlock *hws)
{
const struct hwspinlock_ops *ops;
assert(hws);
if (!hws->dev)
return -EINVAL;
ops = hwspinlock_dev_ops(hws->dev);
if (!ops->unlock)
return -ENOSYS;
return ops->unlock(hws->dev, hws->id);
}
static int hwspinlock_post_bind(struct udevice *dev)
{
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
struct hwspinlock_ops *ops = device_get_ops(dev);
static int reloc_done;
if (!reloc_done) {
if (ops->lock)
ops->lock += gd->reloc_off;
if (ops->unlock)
ops->unlock += gd->reloc_off;
if (ops->relax)
ops->relax += gd->reloc_off;
reloc_done++;
}
#endif
return 0;
}
UCLASS_DRIVER(hwspinlock) = {
.id = UCLASS_HWSPINLOCK,
.name = "hwspinlock",
.post_bind = hwspinlock_post_bind,
};

56
drivers/hwspinlock/sandbox_hwspinlock.c Normal file
View File

@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
#include <dm.h>
#include <hwspinlock.h>
#include <asm/state.h>
static int sandbox_lock(struct udevice *dev, int index)
{
struct sandbox_state *state = state_get_current();
if (index != 0)
return -1;
if (state->hwspinlock)
return -1;
state->hwspinlock = true;
return 0;
}
static int sandbox_unlock(struct udevice *dev, int index)
{
struct sandbox_state *state = state_get_current();
if (index != 0)
return -1;
if (!state->hwspinlock)
return -1;
state->hwspinlock = false;
return 0;
}
static const struct hwspinlock_ops sandbox_hwspinlock_ops = {
.lock = sandbox_lock,
.unlock = sandbox_unlock,
};
static const struct udevice_id sandbox_hwspinlock_ids[] = {
{ .compatible = "sandbox,hwspinlock" },
{}
};
U_BOOT_DRIVER(hwspinlock_sandbox) = {
.name = "hwspinlock_sandbox",
.id = UCLASS_HWSPINLOCK,
.of_match = sandbox_hwspinlock_ids,
.ops = &sandbox_hwspinlock_ops,
};

92
drivers/hwspinlock/stm32_hwspinlock.c Normal file
View File

@ -0,0 +1,92 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
#include <clk.h>
#include <dm.h>
#include <hwspinlock.h>
#include <asm/io.h>
#define STM32_MUTEX_COREID BIT(8)
#define STM32_MUTEX_LOCK_BIT BIT(31)
#define STM32_MUTEX_NUM_LOCKS 32
struct stm32mp1_hws_priv {
fdt_addr_t base;
};
static int stm32mp1_lock(struct udevice *dev, int index)
{
struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
u32 status;
if (index >= STM32_MUTEX_NUM_LOCKS)
return -EINVAL;
status = readl(priv->base + index * sizeof(u32));
if (status == (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
return -EBUSY;
writel(STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID,
priv->base + index * sizeof(u32));
status = readl(priv->base + index * sizeof(u32));
if (status != (STM32_MUTEX_LOCK_BIT | STM32_MUTEX_COREID))
return -EINVAL;
return 0;
}
static int stm32mp1_unlock(struct udevice *dev, int index)
{
struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
if (index >= STM32_MUTEX_NUM_LOCKS)
return -EINVAL;
writel(STM32_MUTEX_COREID, priv->base + index * sizeof(u32));
return 0;
}
static int stm32mp1_hwspinlock_probe(struct udevice *dev)
{
struct stm32mp1_hws_priv *priv = dev_get_priv(dev);
struct clk clk;
int ret;
priv->base = dev_read_addr(dev);
if (priv->base == FDT_ADDR_T_NONE)
return -EINVAL;
ret = clk_get_by_index(dev, 0, &clk);
if (ret)
return ret;
ret = clk_enable(&clk);
if (ret)
clk_free(&clk);
return ret;
}
static const struct hwspinlock_ops stm32mp1_hwspinlock_ops = {
.lock = stm32mp1_lock,
.unlock = stm32mp1_unlock,
};
static const struct udevice_id stm32mp1_hwspinlock_ids[] = {
{ .compatible = "st,stm32-hwspinlock" },
{}
};
U_BOOT_DRIVER(hwspinlock_stm32mp1) = {
.name = "hwspinlock_stm32mp1",
.id = UCLASS_HWSPINLOCK,
.of_match = stm32mp1_hwspinlock_ids,
.ops = &stm32mp1_hwspinlock_ops,
.probe = stm32mp1_hwspinlock_probe,
.priv_auto_alloc_size = sizeof(struct stm32mp1_hws_priv),
};

282
drivers/pinctrl/pinctrl_stm32.c
View File

@ -1,6 +1,7 @@
#include <common.h>
#include <dm.h>
#include <dm/pinctrl.h>
#include <hwspinlock.h>
#include <asm/arch/gpio.h>
#include <asm/gpio.h>
#include <asm/io.h>
@ -14,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
#define OTYPE_MSK 1
#define AFR_MASK 0xF
#ifndef CONFIG_SPL_BUILD
struct stm32_pinctrl_priv {
struct hwspinlock hws;
int pinctrl_ngpios;
struct list_head gpio_dev;
};
@ -25,7 +26,7 @@ struct stm32_gpio_bank {
struct list_head list;
};
#define MAX_PIN_PER_BANK 16
#ifndef CONFIG_SPL_BUILD
static char pin_name[PINNAME_SIZE];
#define PINMUX_MODE_COUNT 5
@ -51,122 +52,7 @@ static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset)
return af;
}
static int stm32_pinctrl_get_pins_count(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv;
struct stm32_gpio_bank *gpio_bank;
/*
* if get_pins_count has already been executed once on this
* pin-controller, no need to run it again
*/
if (priv->pinctrl_ngpios)
return priv->pinctrl_ngpios;
/*
* walk through all banks to retrieve the pin-controller
* pins number
*/
list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
priv->pinctrl_ngpios += uc_priv->gpio_count;
}
return priv->pinctrl_ngpios;
}
static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
unsigned int selector)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
struct stm32_gpio_bank *gpio_bank;
struct gpio_dev_priv *uc_priv;
int first_pin = 0;
/* look up for the bank which owns the requested pin */
list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
if (selector < (first_pin + uc_priv->gpio_count))
/* we found the bank */
return gpio_bank->gpio_dev;
first_pin += uc_priv->gpio_count;
}
return NULL;
}
static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
unsigned int selector)
{
struct gpio_dev_priv *uc_priv;
struct udevice *gpio_dev;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
if (!gpio_dev) {
snprintf(pin_name, PINNAME_SIZE, "Error");
} else {
uc_priv = dev_get_uclass_priv(gpio_dev);
snprintf(pin_name, PINNAME_SIZE, "%s%d",
uc_priv->bank_name,
selector % MAX_PIN_PER_BANK);
}
return pin_name;
}
static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
unsigned int selector,
char *buf,
int size)
{
struct udevice *gpio_dev;
const char *label;
int gpio_pin;
int mode;
int af_num;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector);
if (!gpio_dev)
return -ENODEV;
/* translate pin-controller pin number to gpio pin number */
gpio_pin = selector % MAX_PIN_PER_BANK;
mode = gpio_get_raw_function(gpio_dev, gpio_pin, &label);
dev_dbg(dev, "selector = %d gpio_pin = %d mode = %d\n",
selector, gpio_pin, mode);
switch (mode) {
case GPIOF_UNKNOWN:
/* should never happen */
return -EINVAL;
case GPIOF_UNUSED:
snprintf(buf, size, "%s", pinmux_mode[mode]);
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_pin);
snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
break;
case GPIOF_OUTPUT:
case GPIOF_INPUT:
snprintf(buf, size, "%s %s",
pinmux_mode[mode], label ? label : "");
break;
}
return 0;
}
int stm32_pinctrl_probe(struct udevice *dev)
static int stm32_populate_gpio_dev_list(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
struct udevice *gpio_dev;
@ -174,8 +60,6 @@ int stm32_pinctrl_probe(struct udevice *dev)
struct stm32_gpio_bank *gpio_bank;
int ret;
INIT_LIST_HEAD(&priv->gpio_dev);
/*
* parse pin-controller sub-nodes (ie gpio bank nodes) and fill
* a list with all gpio device reference which belongs to the
@ -200,19 +84,173 @@ int stm32_pinctrl_probe(struct udevice *dev)
return 0;
}
static int stm32_pinctrl_get_pins_count(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
struct gpio_dev_priv *uc_priv;
struct stm32_gpio_bank *gpio_bank;
/*
* if get_pins_count has already been executed once on this
* pin-controller, no need to run it again
*/
if (priv->pinctrl_ngpios)
return priv->pinctrl_ngpios;
if (list_empty(&priv->gpio_dev))
stm32_populate_gpio_dev_list(dev);
/*
* walk through all banks to retrieve the pin-controller
* pins number
*/
list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
priv->pinctrl_ngpios += uc_priv->gpio_count;
}
return priv->pinctrl_ngpios;
}
static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
unsigned int selector,
unsigned int *idx)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
struct stm32_gpio_bank *gpio_bank;
struct gpio_dev_priv *uc_priv;
int pin_count = 0;
if (list_empty(&priv->gpio_dev))
stm32_populate_gpio_dev_list(dev);
/* look up for the bank which owns the requested pin */
list_for_each_entry(gpio_bank, &priv->gpio_dev, list) {
uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev);
if (selector < (pin_count + uc_priv->gpio_count)) {
/*
* we found the bank, convert pin selector to
* gpio bank index
*/
*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
selector - pin_count);
if (*idx < 0)
return NULL;
return gpio_bank->gpio_dev;
}
pin_count += uc_priv->gpio_count;
}
return NULL;
}
static const char *stm32_pinctrl_get_pin_name(struct udevice *dev,
unsigned int selector)
{
struct gpio_dev_priv *uc_priv;
struct udevice *gpio_dev;
unsigned int gpio_idx;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
if (!gpio_dev) {
snprintf(pin_name, PINNAME_SIZE, "Error");
} else {
uc_priv = dev_get_uclass_priv(gpio_dev);
snprintf(pin_name, PINNAME_SIZE, "%s%d",
uc_priv->bank_name,
gpio_idx);
}
return pin_name;
}
static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
unsigned int selector,
char *buf,
int size)
{
struct udevice *gpio_dev;
const char *label;
int mode;
int af_num;
unsigned int gpio_idx;
/* look up for the bank which owns the requested pin */
gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx);
if (!gpio_dev)
return -ENODEV;
mode = gpio_get_raw_function(gpio_dev, gpio_idx, &label);
dev_dbg(dev, "selector = %d gpio_idx = %d mode = %d\n",
selector, gpio_idx, mode);
switch (mode) {
case GPIOF_UNKNOWN:
/* should never happen */
return -EINVAL;
case GPIOF_UNUSED:
snprintf(buf, size, "%s", pinmux_mode[mode]);
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
snprintf(buf, size, "%s %d", pinmux_mode[mode], af_num);
break;
case GPIOF_OUTPUT:
case GPIOF_INPUT:
snprintf(buf, size, "%s %s",
pinmux_mode[mode], label ? label : "");
break;
}
return 0;
}
#endif
int stm32_pinctrl_probe(struct udevice *dev)
{
struct stm32_pinctrl_priv *priv = dev_get_priv(dev);
int ret;
INIT_LIST_HEAD(&priv->gpio_dev);
/* hwspinlock property is optional, just log the error */
ret = hwspinlock_get_by_index(dev, 0, &priv->hws);
if (ret)
debug("%s: hwspinlock_get_by_index may have failed (%d)\n",
__func__, ret);
return 0;
}
static int stm32_gpio_config(struct gpio_desc *desc,
const struct stm32_gpio_ctl *ctl)
{
struct stm32_gpio_priv *priv = dev_get_priv(desc->dev);
struct stm32_gpio_regs *regs = priv->regs;
struct stm32_pinctrl_priv *ctrl_priv;
int ret;
u32 index;
if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 ||
ctl->pupd > 2 || ctl->speed > 3)
return -EINVAL;
ctrl_priv = dev_get_priv(dev_get_parent(desc->dev));
ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10);
if (ret == -ETIME) {
dev_err(desc->dev, "HWSpinlock timeout\n");
return ret;
}
index = (desc->offset & 0x07) * 4;
clrsetbits_le32(&regs->afr[desc->offset >> 3], AFR_MASK << index,
ctl->af << index);
@ -227,6 +265,8 @@ static int stm32_gpio_config(struct gpio_desc *desc,
index = desc->offset;
clrsetbits_le32(&regs->otyper, OTYPE_MSK << index, ctl->otype << index);
hwspinlock_unlock(&ctrl_priv->hws);
return 0;
}
@ -393,8 +433,6 @@ U_BOOT_DRIVER(pinctrl_stm32) = {
.of_match = stm32_pinctrl_ids,
.ops = &stm32_pinctrl_ops,
.bind = dm_scan_fdt_dev,
#ifndef CONFIG_SPL_BUILD
.probe = stm32_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct stm32_pinctrl_priv),
#endif
};

8
drivers/serial/Kconfig
View File

@ -506,16 +506,10 @@ config BCM283X_PL011_SERIAL
config BCM6345_SERIAL
bool "Support for BCM6345 UART"
depends on DM_SERIAL && ARCH_BMIPS
depends on DM_SERIAL
help
Select this to enable UART on BCM6345 SoCs.
config BCM6858_SERIAL
bool "Support for BCM6858 UART"
depends on DM_SERIAL && ARCH_BCM6858
help
Select this to enable UART on BCM6358 SoCs.
config FSL_LINFLEXUART
bool "Freescale Linflex UART support"
depends on DM_SERIAL

1
drivers/serial/Makefile
View File

@ -35,7 +35,6 @@ obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
obj-$(CONFIG_ARM_DCC) += arm_dcc.o
obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
obj-$(CONFIG_BCM6858_SERIAL) += serial_bcm6858.o
obj-$(CONFIG_EFI_APP) += serial_efi.o
obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
obj-$(CONFIG_MCFUART) += mcfuart.o

99
drivers/serial/serial_bcm6345.c
View File

@ -89,26 +89,26 @@ struct bcm6345_serial_priv {
/* enable rx & tx operation on uart */
static void bcm6345_serial_enable(void __iomem *base)
{
setbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}
/* disable rx & tx operation on uart */
static void bcm6345_serial_disable(void __iomem *base)
{
clrbits_be32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}
/* clear all unread data in rx fifo and unsent data in tx fifo */
static void bcm6345_serial_flush(void __iomem *base)
{
/* empty rx and tx fifo */
setbits_be32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
UART_CTL_RSTTXFIFO_MASK);
setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
UART_CTL_RSTTXFIFO_MASK);
/* read any pending char to make sure all irq status are cleared */
readl_be(base + UART_FIFO_REG);
readl(base + UART_FIFO_REG);
}
static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
@ -120,40 +120,40 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
bcm6345_serial_flush(base);
/* set uart control config */
clrsetbits_be32(base + UART_CTL_REG,
/* clear rx timeout */
UART_CTL_RXTIMEOUT_MASK |
/* clear stop bits */
UART_CTL_STOPBITS_MASK |
/* clear bits per symbol */
UART_CTL_BITSPERSYM_MASK |
/* clear xmit break */
UART_CTL_XMITBRK_MASK |
/* clear reserved bit */
UART_CTL_RSVD_MASK |
/* disable parity */
UART_CTL_RXPAREN_MASK |
UART_CTL_TXPAREN_MASK |
/* disable loopback */
UART_CTL_LOOPBACK_MASK,
/* set timeout to 5 */
UART_CTL_RXTIMEOUT_5 |
/* set 8 bits/symbol */
UART_CTL_BITSPERSYM_8 |
/* set 1 stop bit */
UART_CTL_STOPBITS_1 |
/* set parity to even */
UART_CTL_RXPAREVEN_MASK |
UART_CTL_TXPAREVEN_MASK);
clrsetbits_32(base + UART_CTL_REG,
/* clear rx timeout */
UART_CTL_RXTIMEOUT_MASK |
/* clear stop bits */
UART_CTL_STOPBITS_MASK |
/* clear bits per symbol */
UART_CTL_BITSPERSYM_MASK |
/* clear xmit break */
UART_CTL_XMITBRK_MASK |
/* clear reserved bit */
UART_CTL_RSVD_MASK |
/* disable parity */
UART_CTL_RXPAREN_MASK |
UART_CTL_TXPAREN_MASK |
/* disable loopback */
UART_CTL_LOOPBACK_MASK,
/* set timeout to 5 */
UART_CTL_RXTIMEOUT_5 |
/* set 8 bits/symbol */
UART_CTL_BITSPERSYM_8 |
/* set 1 stop bit */
UART_CTL_STOPBITS_1 |
/* set parity to even */
UART_CTL_RXPAREVEN_MASK |
UART_CTL_TXPAREVEN_MASK);
/* set uart fifo config */
clrsetbits_be32(base + UART_FIFO_CFG_REG,
/* clear fifo config */
UART_FIFO_CFG_RX_MASK |
UART_FIFO_CFG_TX_MASK,
/* set fifo config to 4 */
UART_FIFO_CFG_RX_4 |
UART_FIFO_CFG_TX_4);
clrsetbits_32(base + UART_FIFO_CFG_REG,
/* clear fifo config */
UART_FIFO_CFG_RX_MASK |
UART_FIFO_CFG_TX_MASK,
/* set fifo config to 4 */
UART_FIFO_CFG_RX_4 |
UART_FIFO_CFG_TX_4);
/* set baud rate */
val = ((clk / baudrate) >> 4);
@ -161,10 +161,10 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
val = (val >> 1);
else
val = (val >> 1) - 1;
writel_be(val, base + UART_BAUD_REG);
writel(val, base + UART_BAUD_REG);
/* clear interrupts */
writel_be(0, base + UART_IR_REG);
writel(0, base + UART_IR_REG);
/* enable uart */
bcm6345_serial_enable(base);
@ -175,7 +175,7 @@ static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
static int bcm6345_serial_pending(struct udevice *dev, bool input)
{
struct bcm6345_serial_priv *priv = dev_get_priv(dev);
u32 val = readl_be(priv->base + UART_IR_REG);
u32 val = readl(priv->base + UART_IR_REG);
if (input)
return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
@ -195,11 +195,11 @@ static int bcm6345_serial_putc(struct udevice *dev, const char ch)
struct bcm6345_serial_priv *priv = dev_get_priv(dev);
u32 val;
val = readl_be(priv->base + UART_IR_REG);
val = readl(priv->base + UART_IR_REG);
if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
return -EAGAIN;
writel_be(ch, priv->base + UART_FIFO_REG);
writel(ch, priv->base + UART_FIFO_REG);
return 0;
}
@ -209,14 +209,13 @@ static int bcm6345_serial_getc(struct udevice *dev)
struct bcm6345_serial_priv *priv = dev_get_priv(dev);
u32 val;
val = readl_be(priv->base + UART_IR_REG);
val = readl(priv->base + UART_IR_REG);
if (val & UART_IR_STAT(UART_IR_RXOVER))
setbits_be32(priv->base + UART_CTL_REG,
UART_CTL_RSTRXFIFO_MASK);
setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK);
if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
return -EAGAIN;
val = readl_be(priv->base + UART_FIFO_REG);
val = readl(priv->base + UART_FIFO_REG);
if (val & UART_FIFO_ANYERR_MASK)
return -EAGAIN;
@ -277,7 +276,7 @@ static inline void _debug_uart_init(void)
static inline void wait_xfered(void __iomem *base)
{
do {
u32 val = readl_be(base + UART_IR_REG);
u32 val = readl(base + UART_IR_REG);
if (val & UART_IR_STAT(UART_IR_TXEMPTY))
break;
} while (1);
@ -288,7 +287,7 @@ static inline void _debug_uart_putc(int ch)
void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
wait_xfered(base);
writel_be(ch, base + UART_FIFO_REG);
writel(ch, base + UART_FIFO_REG);
wait_xfered(base);
}

300
drivers/serial/serial_bcm6858.c
View File

@ -1,300 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
*
* Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
* Derived from linux/drivers/tty/serial/serial_bcm6345.c
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*/
#include <clk.h>
#include <dm.h>
#include <debug_uart.h>
#include <errno.h>
#include <serial.h>
#include <asm/io.h>
#include <asm/types.h>
/* UART Control register */
#define UART_CTL_REG 0x0
#define UART_CTL_RXTIMEOUT_MASK 0x1f
#define UART_CTL_RXTIMEOUT_5 0x5
#define UART_CTL_RSTRXFIFO_SHIFT 6
#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
#define UART_CTL_RSTTXFIFO_SHIFT 7
#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
#define UART_CTL_STOPBITS_SHIFT 8
#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
#define UART_CTL_BITSPERSYM_SHIFT 12
#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
#define UART_CTL_BITSPERSYM_8 (0x3 << UART_CTL_BITSPERSYM_SHIFT)
#define UART_CTL_XMITBRK_SHIFT 14
#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
#define UART_CTL_RSVD_SHIFT 15
#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
#define UART_CTL_RXPAREVEN_SHIFT 16
#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
#define UART_CTL_RXPAREN_SHIFT 17
#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
#define UART_CTL_TXPAREVEN_SHIFT 18
#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
#define UART_CTL_TXPAREN_SHIFT 19
#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
#define UART_CTL_LOOPBACK_SHIFT 20
#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
#define UART_CTL_RXEN_SHIFT 21
#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
#define UART_CTL_TXEN_SHIFT 22
#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
#define UART_CTL_BRGEN_SHIFT 23
#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
/* UART Baudword register */
#define UART_BAUD_REG 0x4
/* UART FIFO Config register */
#define UART_FIFO_CFG_REG 0x8
#define UART_FIFO_CFG_RX_SHIFT 8
#define UART_FIFO_CFG_RX_MASK (0xf << UART_FIFO_CFG_RX_SHIFT)
#define UART_FIFO_CFG_RX_4 (0x4 << UART_FIFO_CFG_RX_SHIFT)
#define UART_FIFO_CFG_TX_SHIFT 12
#define UART_FIFO_CFG_TX_MASK (0xf << UART_FIFO_CFG_TX_SHIFT)
#define UART_FIFO_CFG_TX_4 (0x4 << UART_FIFO_CFG_TX_SHIFT)
/* UART Interrupt register */
#define UART_IR_REG 0x10
#define UART_IR_STAT(x) (1 << (x))
#define UART_IR_TXEMPTY 5
#define UART_IR_RXOVER 7
#define UART_IR_RXNOTEMPTY 11
/* UART FIFO register */
#define UART_FIFO_REG 0x14
#define UART_FIFO_VALID_MASK 0xff
#define UART_FIFO_FRAMEERR_SHIFT 8
#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
#define UART_FIFO_PARERR_SHIFT 9
#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
#define UART_FIFO_BRKDET_SHIFT 10
#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
UART_FIFO_PARERR_MASK | \
UART_FIFO_BRKDET_MASK)
struct bcm6858_serial_priv {
void __iomem *base;
ulong uartclk;
};
/* enable rx & tx operation on uart */
static void bcm6858_serial_enable(void __iomem *base)
{
setbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}
/* disable rx & tx operation on uart */
static void bcm6858_serial_disable(void __iomem *base)
{
clrbits_le32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK |
UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK);
}
/* clear all unread data in rx fifo and unsent data in tx fifo */
static void bcm6858_serial_flush(void __iomem *base)
{
/* empty rx and tx fifo */
setbits_le32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK |
UART_CTL_RSTTXFIFO_MASK);
/* read any pending char to make sure all irq status are cleared */
readl(base + UART_FIFO_REG);
}
static int bcm6858_serial_init(void __iomem *base, ulong clk, u32 baudrate)
{
u32 val;
/* mask all irq and flush port */
bcm6858_serial_disable(base);
bcm6858_serial_flush(base);
/* set uart control config */
clrsetbits_le32(base + UART_CTL_REG,
/* clear rx timeout */
UART_CTL_RXTIMEOUT_MASK |
/* clear stop bits */
UART_CTL_STOPBITS_MASK |
/* clear bits per symbol */
UART_CTL_BITSPERSYM_MASK |
/* clear xmit break */
UART_CTL_XMITBRK_MASK |
/* clear reserved bit */
UART_CTL_RSVD_MASK |
/* disable parity */
UART_CTL_RXPAREN_MASK |
UART_CTL_TXPAREN_MASK |
/* disable loopback */
UART_CTL_LOOPBACK_MASK,
/* set timeout to 5 */
UART_CTL_RXTIMEOUT_5 |
/* set 8 bits/symbol */
UART_CTL_BITSPERSYM_8 |
/* set 1 stop bit */
UART_CTL_STOPBITS_1 |
/* set parity to even */
UART_CTL_RXPAREVEN_MASK |
UART_CTL_TXPAREVEN_MASK);
/* set uart fifo config */
clrsetbits_le32(base + UART_FIFO_CFG_REG,
/* clear fifo config */
UART_FIFO_CFG_RX_MASK |
UART_FIFO_CFG_TX_MASK,
/* set fifo config to 4 */
UART_FIFO_CFG_RX_4 |
UART_FIFO_CFG_TX_4);
/* set baud rate */
val = ((clk / baudrate) >> 4);
if (val & 0x1)
val = (val >> 1);
else
val = (val >> 1) - 1;
writel(val, base + UART_BAUD_REG);
/* clear interrupts */
writel(0, base + UART_IR_REG);
/* enable uart */
bcm6858_serial_enable(base);
return 0;
}
static int bcm6858_serial_pending(struct udevice *dev, bool input)
{
struct bcm6858_serial_priv *priv = dev_get_priv(dev);
u32 val = readl(priv->base + UART_IR_REG);
if (input)
return !!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY));
else
return !(val & UART_IR_STAT(UART_IR_TXEMPTY));
}
static int bcm6858_serial_setbrg(struct udevice *dev, int baudrate)
{
struct bcm6858_serial_priv *priv = dev_get_priv(dev);
return bcm6858_serial_init(priv->base, priv->uartclk, baudrate);
}
static int bcm6858_serial_putc(struct udevice *dev, const char ch)
{
struct bcm6858_serial_priv *priv = dev_get_priv(dev);
u32 val;
val = readl(priv->base + UART_IR_REG);
if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
return -EAGAIN;
writel(ch, priv->base + UART_FIFO_REG);
return 0;
}
static int bcm6858_serial_getc(struct udevice *dev)
{
struct bcm6858_serial_priv *priv = dev_get_priv(dev);
u32 val;
val = readl(priv->base + UART_IR_REG);
if (val & UART_IR_STAT(UART_IR_RXOVER))
setbits_le32(priv->base + UART_CTL_REG,
UART_CTL_RSTRXFIFO_MASK);
if (!(val & UART_IR_STAT(UART_IR_RXNOTEMPTY)))
return -EAGAIN;
val = readl(priv->base + UART_FIFO_REG);
if (val & UART_FIFO_ANYERR_MASK)
return -EAGAIN;
return val & UART_FIFO_VALID_MASK;
}
static int bcm6858_serial_probe(struct udevice *dev)
{
struct bcm6858_serial_priv *priv = dev_get_priv(dev);
struct clk clk;
int ret;
/* get address */
priv->base = dev_remap_addr(dev);
if (!priv->base)
return -EINVAL;
/* get clock rate */
ret = clk_get_by_index(dev, 0, &clk);
if (ret < 0)
return ret;
priv->uartclk = clk_get_rate(&clk);
clk_free(&clk);
/* initialize serial */
return bcm6858_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
}
static const struct dm_serial_ops bcm6858_serial_ops = {
.putc = bcm6858_serial_putc,
.pending = bcm6858_serial_pending,
.getc = bcm6858_serial_getc,
.setbrg = bcm6858_serial_setbrg,
};
static const struct udevice_id bcm6858_serial_ids[] = {
{ .compatible = "brcm,bcm6858-uart" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(bcm6858_serial) = {
.name = "bcm6858-uart",
.id = UCLASS_SERIAL,
.of_match = bcm6858_serial_ids,
.probe = bcm6858_serial_probe,
.priv_auto_alloc_size = sizeof(struct bcm6858_serial_priv),
.ops = &bcm6858_serial_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_BCM6858
static inline void _debug_uart_init(void)
{
void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
bcm6858_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
}
static inline void wait_xfered(void __iomem *base)
{
do {
u32 val = readl(base + UART_IR_REG);
if (val & UART_IR_STAT(UART_IR_TXEMPTY))
break;
} while (1);
}
static inline void _debug_uart_putc(int ch)
{
void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
wait_xfered(base);
writel(ch, base + UART_FIFO_REG);
wait_xfered(base);
}
DEBUG_UART_FUNCS
#endif

42
drivers/serial/serial_omap.c
View File

@ -7,7 +7,6 @@
*/
#include <common.h>
#include <debug_uart.h>
#include <dm.h>
#include <dt-structs.h>
#include <ns16550.h>
@ -20,6 +19,47 @@
#ifdef CONFIG_DEBUG_UART_OMAP
#ifndef CONFIG_SYS_NS16550_IER
#define CONFIG_SYS_NS16550_IER 0x00
#endif
#define UART_MCRVAL 0x00
#define UART_LCRVAL UART_LCR_8N1
static inline void serial_out_shift(void *addr, int shift, int value)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
outb(value, (ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
out_le32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
out_be32(addr, value);
#elif defined(CONFIG_SYS_NS16550_MEM32)
writel(value, addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
writeb(value, addr + (1 << shift) - 1);
#else
writeb(value, addr);
#endif
}
static inline int serial_in_shift(void *addr, int shift)
{
#ifdef CONFIG_SYS_NS16550_PORT_MAPPED
return inb((ulong)addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_LITTLE_ENDIAN)
return in_le32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32) && defined(CONFIG_SYS_BIG_ENDIAN)
return in_be32(addr);
#elif defined(CONFIG_SYS_NS16550_MEM32)
return readl(addr);
#elif defined(CONFIG_SYS_BIG_ENDIAN)
return readb(addr + (1 << shift) - 1);
#else
return readb(addr);
#endif
}
#include <debug_uart.h>
static inline void _debug_uart_init(void)

4
drivers/w1/w1-uclass.c
View File

@ -84,10 +84,6 @@ static int w1_enumerate(struct udevice *bus)
rn |= (tmp64 << i);
}
/* last device or error, aborting here */
if ((triplet_ret & 0x03) == 0x03)
last_device = true;
if ((triplet_ret & 0x03) != 0x03) {
if (desc_bit == last_zero || last_zero < 0) {
last_device = 1;

14
fs/fat/fat.c
View File

@ -571,6 +571,17 @@ static int get_fs_info(fsdata *mydata)
mydata->sect_size, cur_part_info.blksz);
return -1;
}
if (mydata->clust_size == 0) {
printf("Error: FAT cluster size not set\n");
return -1;
}
if ((unsigned int)mydata->clust_size * mydata->sect_size >
MAX_CLUSTSIZE) {
printf("Error: FAT cluster size too big (cs=%u, max=%u)\n",
(unsigned int)mydata->clust_size * mydata->sect_size,
MAX_CLUSTSIZE);
return -1;
}
if (mydata->fatsize == 32) {
mydata->data_begin = mydata->rootdir_sect -
@ -810,6 +821,9 @@ static dir_entry *extract_vfat_name(fat_itr *itr)
slot2str((dir_slot *)dent, buf, &idx);
if (n + idx >= sizeof(itr->l_name))
return NULL;
/* shift accumulated long-name up and copy new part in: */
memmove(itr->l_name + idx, itr->l_name, n);
memcpy(itr->l_name, buf, idx);

1
include/dm/uclass-id.h
View File

@ -42,6 +42,7 @@ enum uclass_id {
UCLASS_FIRMWARE, /* Firmware */
UCLASS_FS_FIRMWARE_LOADER, /* Generic loader */
UCLASS_GPIO, /* Bank of general-purpose I/O pins */
UCLASS_HWSPINLOCK, /* Hardware semaphores */
UCLASS_I2C, /* I2C bus */
UCLASS_I2C_EEPROM, /* I2C EEPROM device */
UCLASS_I2C_GENERIC, /* Generic I2C device */

128
include/dma-uclass.h Normal file
View File

@ -0,0 +1,128 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
* Written by Mugunthan V N <mugunthanvnm@ti.com>
*
*/
#ifndef _DMA_UCLASS_H
#define _DMA_UCLASS_H
/* See dma.h for background documentation. */
#include <dma.h>
struct ofnode_phandle_args;
/*
* struct dma_ops - Driver model DMA operations
*
* The uclass interface is implemented by all DMA devices which use
* driver model.
*/
struct dma_ops {
#ifdef CONFIG_DMA_CHANNELS
/**
* of_xlate - Translate a client's device-tree (OF) DMA specifier.
*
* The DMA core calls this function as the first step in implementing
* a client's dma_get_by_*() call.
*
* If this function pointer is set to NULL, the DMA core will use a
* default implementation, which assumes #dma-cells = <1>, and that
* the DT cell contains a simple integer DMA Channel.
*
* At present, the DMA API solely supports device-tree. If this
* changes, other xxx_xlate() functions may be added to support those
* other mechanisms.
*
* @dma: The dma struct to hold the translation result.
* @args: The dma specifier values from device tree.
* @return 0 if OK, or a negative error code.
*/
int (*of_xlate)(struct dma *dma,
struct ofnode_phandle_args *args);
/**
* request - Request a translated DMA.
*
* The DMA core calls this function as the second step in
* implementing a client's dma_get_by_*() call, following a successful
* xxx_xlate() call, or as the only step in implementing a client's
* dma_request() call.
*
* @dma: The DMA struct to request; this has been filled in by
* a previoux xxx_xlate() function call, or by the caller of
* dma_request().
* @return 0 if OK, or a negative error code.
*/
int (*request)(struct dma *dma);
/**
* free - Free a previously requested dma.
*
* This is the implementation of the client dma_free() API.
*
* @dma: The DMA to free.
* @return 0 if OK, or a negative error code.
*/
int (*free)(struct dma *dma);
/**
* enable() - Enable a DMA Channel.
*
* @dma: The DMA Channel to manipulate.
* @return zero on success, or -ve error code.
*/
int (*enable)(struct dma *dma);
/**
* disable() - Disable a DMA Channel.
*
* @dma: The DMA Channel to manipulate.
* @return zero on success, or -ve error code.
*/
int (*disable)(struct dma *dma);
/**
* prepare_rcv_buf() - Prepare/Add receive DMA buffer.
*
* @dma: The DMA Channel to manipulate.
* @dst: The receive buffer pointer.
* @size: The receive buffer size
* @return zero on success, or -ve error code.
*/
int (*prepare_rcv_buf)(struct dma *dma, void *dst, size_t size);
/**
* receive() - Receive a DMA transfer.
*
* @dma: The DMA Channel to manipulate.
* @dst: The destination pointer.
* @metadata: DMA driver's specific data
* @return zero on success, or -ve error code.
*/
int (*receive)(struct dma *dma, void **dst, void *metadata);
/**
* send() - Send a DMA transfer.
*
* @dma: The DMA Channel to manipulate.
* @src: The source pointer.
* @len: Length of the data to be sent (number of bytes).
* @metadata: DMA driver's specific data
* @return zero on success, or -ve error code.
*/
int (*send)(struct dma *dma, void *src, size_t len, void *metadata);
#endif /* CONFIG_DMA_CHANNELS */
/**
* transfer() - Issue a DMA transfer. The implementation must
* wait until the transfer is done.
*
* @dev: The DMA device
* @direction: direction of data transfer (should be one from
* enum dma_direction)
* @dst: The destination pointer.
* @src: The source pointer.
* @len: Length of the data to be copied (number of bytes).
* @return zero on success, or -ve error code.
*/
int (*transfer)(struct udevice *dev, int direction, void *dst,
void *src, size_t len);
};
#endif /* _DMA_UCLASS_H */

282
include/dma.h
View File

@ -1,12 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2015
* Texas Instruments Incorporated, <www.ti.com>
* Copyright (C) 2018 Álvaro Fernández Rojas <noltari@gmail.com>
* Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
* Written by Mugunthan V N <mugunthanvnm@ti.com>
*
*/
#ifndef _DMA_H_
#define _DMA_H_
#include <linux/errno.h>
#include <linux/types.h>
/*
* enum dma_direction - dma transfer direction indicator
* @DMA_MEM_TO_MEM: Memcpy mode
@ -26,28 +31,6 @@ enum dma_direction {
#define DMA_SUPPORTS_DEV_TO_MEM BIT(2)
#define DMA_SUPPORTS_DEV_TO_DEV BIT(3)
/*
* struct dma_ops - Driver model DMA operations
*
* The uclass interface is implemented by all DMA devices which use
* driver model.
*/
struct dma_ops {
/*
* Get the current timer count
*
* @dev: The DMA device
* @direction: direction of data transfer should be one from
enum dma_direction
* @dst: Destination pointer
* @src: Source pointer
* @len: Length of the data to be copied.
* @return: 0 if OK, -ve on error
*/
int (*transfer)(struct udevice *dev, int direction, void *dst,
void *src, size_t len);
};
/*
* struct dma_dev_priv - information about a device used by the uclass
*
@ -58,6 +41,257 @@ struct dma_dev_priv {
u32 supported;
};
#ifdef CONFIG_DMA_CHANNELS
/**
* A DMA is a feature of computer systems that allows certain hardware
* subsystems to access main system memory, independent of the CPU.
* DMA channels are typically generated externally to the HW module
* consuming them, by an entity this API calls a DMA provider. This API
* provides a standard means for drivers to enable and disable DMAs, and to
* copy, send and receive data using DMA.
*
* A driver that implements UCLASS_DMA is a DMA provider. A provider will
* often implement multiple separate DMAs, since the hardware it manages
* often has this capability. dma_uclass.h describes the interface which
* DMA providers must implement.
*
* DMA consumers/clients are the HW modules driven by the DMA channels. This
* header file describes the API used by drivers for those HW modules.
*
* DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking).
* Note. dma_send() is sync operation always - it'll start transfer and will
* poll for it to complete:
* - get/request dma channel
* struct dma dma_tx;
* ret = dma_get_by_name(common->dev, "tx0", &dma_tx);
* if (ret) ...
*
* - enable dma channel
* ret = dma_enable(&dma_tx);
* if (ret) ...
*
* - dma transmit DMA_MEM_TO_DEV.
* struct ti_drv_packet_data packet_data;
*
* packet_data.opt1 = val1;
* packet_data.opt2 = val2;
* ret = dma_send(&dma_tx, packet, length, &packet_data);
* if (ret) ..
*
* DMA consumer DMA_DEV_TO_MEM (receive) usage example (based on networking).
* Note. dma_receive() is sync operation always - it'll start transfer
* (if required) and will poll for it to complete (or for any previously
* configured dev2mem transfer to complete):
* - get/request dma channel
* struct dma dma_rx;
* ret = dma_get_by_name(common->dev, "rx0", &dma_rx);
* if (ret) ...
*
* - enable dma channel
* ret = dma_enable(&dma_rx);
* if (ret) ...
*
* - dma receive DMA_DEV_TO_MEM.
* struct ti_drv_packet_data packet_data;
*
* len = dma_receive(&dma_rx, (void **)packet, &packet_data);
* if (ret < 0) ...
*
* DMA consumer DMA_DEV_TO_MEM (receive) zero-copy usage example (based on
* networking). Networking subsystem allows to configure and use few receive
* buffers (dev2mem), as Networking RX DMA channels usually implemented
* as streaming interface
* - get/request dma channel
* struct dma dma_rx;
* ret = dma_get_by_name(common->dev, "rx0", &dma_rx);
* if (ret) ...
*
* for (i = 0; i < RX_DESC_NUM; i++) {
* ret = dma_prepare_rcv_buf(&dma_rx,
* net_rx_packets[i],
* RX_BUF_SIZE);
* if (ret) ...
* }
*
* - enable dma channel
* ret = dma_enable(&dma_rx);
* if (ret) ...
*
* - dma receive DMA_DEV_TO_MEM.
* struct ti_drv_packet_data packet_data;
*
* len = dma_receive(&dma_rx, (void **)packet, &packet_data);
* if (ret < 0) ..
*
* -- process packet --
*
* - return buffer back to DAM channel
* ret = dma_prepare_rcv_buf(&dma_rx,
* net_rx_packets[rx_next],
* RX_BUF_SIZE);
*/
struct udevice;
/**
* struct dma - A handle to (allowing control of) a single DMA.
*
* Clients provide storage for DMA handles. The content of the structure is
* managed solely by the DMA API and DMA drivers. A DMA struct is
* initialized by "get"ing the DMA struct. The DMA struct is passed to all
* other DMA APIs to identify which DMA channel to operate upon.
*
* @dev: The device which implements the DMA channel.
* @id: The DMA channel ID within the provider.
*
* Currently, the DMA API assumes that a single integer ID is enough to
* identify and configure any DMA channel for any DMA provider. If this
* assumption becomes invalid in the future, the struct could be expanded to
* either (a) add more fields to allow DMA providers to store additional
* information, or (b) replace the id field with an opaque pointer, which the
* provider would dynamically allocated during its .of_xlate op, and process
* during is .request op. This may require the addition of an extra op to clean
* up the allocation.
*/
struct dma {
struct udevice *dev;
/*
* Written by of_xlate. We assume a single id is enough for now. In the
* future, we might add more fields here.
*/
unsigned long id;
};
# if CONFIG_IS_ENABLED(OF_CONTROL) && CONFIG_IS_ENABLED(DMA)
/**
* dma_get_by_index - Get/request a DMA by integer index.
*
* This looks up and requests a DMA. The index is relative to the client
* device; each device is assumed to have n DMAs associated with it somehow,
* and this function finds and requests one of them. The mapping of client
* device DMA indices to provider DMAs may be via device-tree properties,
* board-provided mapping tables, or some other mechanism.
*
* @dev: The client device.
* @index: The index of the DMA to request, within the client's list of
* DMA channels.
* @dma: A pointer to a DMA struct to initialize.
* @return 0 if OK, or a negative error code.
*/
int dma_get_by_index(struct udevice *dev, int index, struct dma *dma);
/**
* dma_get_by_name - Get/request a DMA by name.
*
* This looks up and requests a DMA. The name is relative to the client
* device; each device is assumed to have n DMAs associated with it somehow,
* and this function finds and requests one of them. The mapping of client
* device DMA names to provider DMAs may be via device-tree properties,
* board-provided mapping tables, or some other mechanism.
*
* @dev: The client device.
* @name: The name of the DMA to request, within the client's list of
* DMA channels.
* @dma: A pointer to a DMA struct to initialize.
* @return 0 if OK, or a negative error code.
*/
int dma_get_by_name(struct udevice *dev, const char *name, struct dma *dma);
# else
static inline int dma_get_by_index(struct udevice *dev, int index,
struct dma *dma)
{
return -ENOSYS;
}
static inline int dma_get_by_name(struct udevice *dev, const char *name,
struct dma *dma)
{
return -ENOSYS;
}
# endif
/**
* dma_request - Request a DMA by provider-specific ID.
*
* This requests a DMA using a provider-specific ID. Generally, this function
* should not be used, since dma_get_by_index/name() provide an interface that
* better separates clients from intimate knowledge of DMA providers.
* However, this function may be useful in core SoC-specific code.
*
* @dev: The DMA provider device.
* @dma: A pointer to a DMA struct to initialize. The caller must
* have already initialized any field in this struct which the
* DMA provider uses to identify the DMA channel.
* @return 0 if OK, or a negative error code.
*/
int dma_request(struct udevice *dev, struct dma *dma);
/**
* dma_free - Free a previously requested DMA.
*
* @dma: A DMA struct that was previously successfully requested by
* dma_request/get_by_*().
* @return 0 if OK, or a negative error code.
*/
int dma_free(struct dma *dma);
/**
* dma_enable() - Enable (turn on) a DMA channel.
*
* @dma: A DMA struct that was previously successfully requested by
* dma_request/get_by_*().
* @return zero on success, or -ve error code.
*/
int dma_enable(struct dma *dma);
/**
* dma_disable() - Disable (turn off) a DMA channel.
*
* @dma: A DMA struct that was previously successfully requested by
* dma_request/get_by_*().
* @return zero on success, or -ve error code.
*/
int dma_disable(struct dma *dma);
/**
* dma_prepare_rcv_buf() - Prepare/add receive DMA buffer.
*
* It allows to implement zero-copy async DMA_DEV_TO_MEM (receive) transactions
* if supported by DMA providers.
*
* @dma: A DMA struct that was previously successfully requested by
* dma_request/get_by_*().
* @dst: The receive buffer pointer.
* @size: The receive buffer size
* @return zero on success, or -ve error code.
*/
int dma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size);
/**
* dma_receive() - Receive a DMA transfer.
*
* @dma: A DMA struct that was previously successfully requested by
* dma_request/get_by_*().
* @dst: The destination pointer.
* @metadata: DMA driver's channel specific data
* @return length of received data on success, or zero - no data,
* or -ve error code.
*/
int dma_receive(struct dma *dma, void **dst, void *metadata);
/**
* dma_send() - Send a DMA transfer.
*
* @dma: A DMA struct that was previously successfully requested by
* dma_request/get_by_*().
* @src: The source pointer.
* @len: Length of the data to be sent (number of bytes).
* @metadata: DMA driver's channel specific data
* @return zero on success, or -ve error code.
*/
int dma_send(struct dma *dma, void *src, size_t len, void *metadata);
#endif /* CONFIG_DMA_CHANNELS */
/*
* dma_get_device - get a DMA device which supports transfer
* type of transfer_type

227
include/dt-bindings/clock/am3.h Normal file
View File

@ -0,0 +1,227 @@
/*
* Copyright 2017 Texas Instruments, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __DT_BINDINGS_CLK_AM3_H
#define __DT_BINDINGS_CLK_AM3_H
#define AM3_CLKCTRL_OFFSET 0x0
#define AM3_CLKCTRL_INDEX(offset) ((offset) - AM3_CLKCTRL_OFFSET)
/* XXX: Compatibility part begin, remove this once compatibility support is no longer needed */
/* l4_per clocks */
#define AM3_L4_PER_CLKCTRL_OFFSET 0x14
#define AM3_L4_PER_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_PER_CLKCTRL_OFFSET)
#define AM3_CPGMAC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14)
#define AM3_LCDC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x18)
#define AM3_USB_OTG_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x1c)
#define AM3_TPTC0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x24)
#define AM3_EMIF_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x28)
#define AM3_OCMCRAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x2c)
#define AM3_GPMC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x30)
#define AM3_MCASP0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x34)
#define AM3_UART6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x38)
#define AM3_MMC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x3c)
#define AM3_ELM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x40)
#define AM3_I2C3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x44)
#define AM3_I2C2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x48)
#define AM3_SPI0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x4c)
#define AM3_SPI1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x50)
#define AM3_L4_LS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x60)
#define AM3_MCASP1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x68)
#define AM3_UART2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x6c)
#define AM3_UART3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x70)
#define AM3_UART4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x74)
#define AM3_UART5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x78)
#define AM3_TIMER7_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x7c)
#define AM3_TIMER2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x80)
#define AM3_TIMER3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x84)
#define AM3_TIMER4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x88)
#define AM3_RNG_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x90)
#define AM3_AES_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x94)
#define AM3_SHAM_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xa0)
#define AM3_GPIO2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xac)
#define AM3_GPIO3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb0)
#define AM3_GPIO4_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xb4)
#define AM3_TPCC_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xbc)
#define AM3_D_CAN0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc0)
#define AM3_D_CAN1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xc4)
#define AM3_EPWMSS1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xcc)
#define AM3_EPWMSS0_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd4)
#define AM3_EPWMSS2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xd8)
#define AM3_L3_INSTR_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xdc)
#define AM3_L3_MAIN_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe0)
#define AM3_PRUSS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xe8)
#define AM3_TIMER5_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xec)
#define AM3_TIMER6_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf0)
#define AM3_MMC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf4)
#define AM3_MMC3_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xf8)
#define AM3_TPTC1_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0xfc)
#define AM3_TPTC2_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x100)
#define AM3_SPINLOCK_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x10c)
#define AM3_MAILBOX_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x110)
#define AM3_L4_HS_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x120)
#define AM3_OCPWP_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x130)
#define AM3_CLKDIV32K_CLKCTRL AM3_L4_PER_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CLKCTRL_OFFSET 0x4
#define AM3_L4_WKUP_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_CLKCTRL_OFFSET)
#define AM3_CONTROL_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x4)
#define AM3_GPIO1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc)
#define AM3_DEBUGSS_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0x14)
#define AM3_WKUP_M3_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb0)
#define AM3_UART1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb4)
#define AM3_I2C1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xb8)
#define AM3_ADC_TSC_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xbc)
#define AM3_SMARTREFLEX0_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc0)
#define AM3_TIMER1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc4)
#define AM3_SMARTREFLEX1_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xc8)
#define AM3_WD_TIMER2_CLKCTRL AM3_L4_WKUP_CLKCTRL_INDEX(0xd4)
/* mpu clocks */
#define AM3_MPU_CLKCTRL_OFFSET 0x4
#define AM3_MPU_CLKCTRL_INDEX(offset) ((offset) - AM3_MPU_CLKCTRL_OFFSET)
#define AM3_MPU_CLKCTRL AM3_MPU_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_CLKCTRL_OFFSET 0x4
#define AM3_GFX_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_GFX_L3_CLKCTRL_OFFSET)
#define AM3_GFX_CLKCTRL AM3_GFX_L3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CLKCTRL_OFFSET 0x20
#define AM3_L4_CEFUSE_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_CEFUSE_CLKCTRL_OFFSET)
#define AM3_CEFUSE_CLKCTRL AM3_L4_CEFUSE_CLKCTRL_INDEX(0x20)
/* XXX: Compatibility part end */
/* l4ls clocks */
#define AM3_L4LS_CLKCTRL_OFFSET 0x38
#define AM3_L4LS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4LS_CLKCTRL_OFFSET)
#define AM3_L4LS_UART6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x38)
#define AM3_L4LS_MMC1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x3c)
#define AM3_L4LS_ELM_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x40)
#define AM3_L4LS_I2C3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x44)
#define AM3_L4LS_I2C2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x48)
#define AM3_L4LS_SPI0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x4c)
#define AM3_L4LS_SPI1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x50)
#define AM3_L4LS_L4_LS_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x60)
#define AM3_L4LS_UART2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x6c)
#define AM3_L4LS_UART3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x70)
#define AM3_L4LS_UART4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x74)
#define AM3_L4LS_UART5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x78)
#define AM3_L4LS_TIMER7_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x7c)
#define AM3_L4LS_TIMER2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x80)
#define AM3_L4LS_TIMER3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x84)
#define AM3_L4LS_TIMER4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x88)
#define AM3_L4LS_RNG_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x90)
#define AM3_L4LS_GPIO2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xac)
#define AM3_L4LS_GPIO3_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb0)
#define AM3_L4LS_GPIO4_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xb4)
#define AM3_L4LS_D_CAN0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc0)
#define AM3_L4LS_D_CAN1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xc4)
#define AM3_L4LS_EPWMSS1_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xcc)
#define AM3_L4LS_EPWMSS0_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd4)
#define AM3_L4LS_EPWMSS2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xd8)
#define AM3_L4LS_TIMER5_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xec)
#define AM3_L4LS_TIMER6_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf0)
#define AM3_L4LS_MMC2_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0xf4)
#define AM3_L4LS_SPINLOCK_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x10c)
#define AM3_L4LS_MAILBOX_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x110)
#define AM3_L4LS_OCPWP_CLKCTRL AM3_L4LS_CLKCTRL_INDEX(0x130)
/* l3s clocks */
#define AM3_L3S_CLKCTRL_OFFSET 0x1c
#define AM3_L3S_CLKCTRL_INDEX(offset) ((offset) - AM3_L3S_CLKCTRL_OFFSET)
#define AM3_L3S_USB_OTG_HS_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x1c)
#define AM3_L3S_GPMC_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x30)
#define AM3_L3S_MCASP0_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x34)
#define AM3_L3S_MCASP1_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0x68)
#define AM3_L3S_MMC3_CLKCTRL AM3_L3S_CLKCTRL_INDEX(0xf8)
/* l3 clocks */
#define AM3_L3_CLKCTRL_OFFSET 0x24
#define AM3_L3_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_CLKCTRL_OFFSET)
#define AM3_L3_TPTC0_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x24)
#define AM3_L3_EMIF_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x28)
#define AM3_L3_OCMCRAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x2c)
#define AM3_L3_AES_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x94)
#define AM3_L3_SHAM_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xa0)
#define AM3_L3_TPCC_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xbc)
#define AM3_L3_L3_INSTR_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xdc)
#define AM3_L3_L3_MAIN_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xe0)
#define AM3_L3_TPTC1_CLKCTRL AM3_L3_CLKCTRL_INDEX(0xfc)
#define AM3_L3_TPTC2_CLKCTRL AM3_L3_CLKCTRL_INDEX(0x100)
/* l4hs clocks */
#define AM3_L4HS_CLKCTRL_OFFSET 0x120
#define AM3_L4HS_CLKCTRL_INDEX(offset) ((offset) - AM3_L4HS_CLKCTRL_OFFSET)
#define AM3_L4HS_L4_HS_CLKCTRL AM3_L4HS_CLKCTRL_INDEX(0x120)
/* pruss_ocp clocks */
#define AM3_PRUSS_OCP_CLKCTRL_OFFSET 0xe8
#define AM3_PRUSS_OCP_CLKCTRL_INDEX(offset) ((offset) - AM3_PRUSS_OCP_CLKCTRL_OFFSET)
#define AM3_PRUSS_OCP_PRUSS_CLKCTRL AM3_PRUSS_OCP_CLKCTRL_INDEX(0xe8)
/* cpsw_125mhz clocks */
#define AM3_CPSW_125MHZ_CPGMAC0_CLKCTRL AM3_CLKCTRL_INDEX(0x14)
/* lcdc clocks */
#define AM3_LCDC_CLKCTRL_OFFSET 0x18
#define AM3_LCDC_CLKCTRL_INDEX(offset) ((offset) - AM3_LCDC_CLKCTRL_OFFSET)
#define AM3_LCDC_LCDC_CLKCTRL AM3_LCDC_CLKCTRL_INDEX(0x18)
/* clk_24mhz clocks */
#define AM3_CLK_24MHZ_CLKCTRL_OFFSET 0x14c
#define AM3_CLK_24MHZ_CLKCTRL_INDEX(offset) ((offset) - AM3_CLK_24MHZ_CLKCTRL_OFFSET)
#define AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL AM3_CLK_24MHZ_CLKCTRL_INDEX(0x14c)
/* l4_wkup clocks */
#define AM3_L4_WKUP_CONTROL_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
#define AM3_L4_WKUP_GPIO1_CLKCTRL AM3_CLKCTRL_INDEX(0x8)
#define AM3_L4_WKUP_L4_WKUP_CLKCTRL AM3_CLKCTRL_INDEX(0xc)
#define AM3_L4_WKUP_UART1_CLKCTRL AM3_CLKCTRL_INDEX(0xb4)
#define AM3_L4_WKUP_I2C1_CLKCTRL AM3_CLKCTRL_INDEX(0xb8)
#define AM3_L4_WKUP_ADC_TSC_CLKCTRL AM3_CLKCTRL_INDEX(0xbc)
#define AM3_L4_WKUP_SMARTREFLEX0_CLKCTRL AM3_CLKCTRL_INDEX(0xc0)
#define AM3_L4_WKUP_TIMER1_CLKCTRL AM3_CLKCTRL_INDEX(0xc4)
#define AM3_L4_WKUP_SMARTREFLEX1_CLKCTRL AM3_CLKCTRL_INDEX(0xc8)
#define AM3_L4_WKUP_WD_TIMER2_CLKCTRL AM3_CLKCTRL_INDEX(0xd4)
/* l3_aon clocks */
#define AM3_L3_AON_CLKCTRL_OFFSET 0x14
#define AM3_L3_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L3_AON_CLKCTRL_OFFSET)
#define AM3_L3_AON_DEBUGSS_CLKCTRL AM3_L3_AON_CLKCTRL_INDEX(0x14)
/* l4_wkup_aon clocks */
#define AM3_L4_WKUP_AON_CLKCTRL_OFFSET 0xb0
#define AM3_L4_WKUP_AON_CLKCTRL_INDEX(offset) ((offset) - AM3_L4_WKUP_AON_CLKCTRL_OFFSET)
#define AM3_L4_WKUP_AON_WKUP_M3_CLKCTRL AM3_L4_WKUP_AON_CLKCTRL_INDEX(0xb0)
/* mpu clocks */
#define AM3_MPU_MPU_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_rtc clocks */
#define AM3_L4_RTC_RTC_CLKCTRL AM3_CLKCTRL_INDEX(0x0)
/* gfx_l3 clocks */
#define AM3_GFX_L3_GFX_CLKCTRL AM3_CLKCTRL_INDEX(0x4)
/* l4_cefuse clocks */
#define AM3_L4_CEFUSE_CEFUSE_CLKCTRL AM3_CLKCTRL_INDEX(0x20)
#endif

140
include/hwspinlock.h Normal file
View File

@ -0,0 +1,140 @@
/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#ifndef _HWSPINLOCK_H_
#define _HWSPINLOCK_H_
/**
* Implement a hwspinlock uclass.
* Hardware spinlocks are used to perform hardware protection of
* critical sections and synchronisation between multiprocessors.
*/
struct udevice;
/**
* struct hwspinlock - A handle to (allowing control of) a single hardware
* spinlock.
*
* @dev: The device which implements the hardware spinlock.
* @id: The hardware spinlock ID within the provider.
*/
struct hwspinlock {
struct udevice *dev;
unsigned long id;
};
#if CONFIG_IS_ENABLED(DM_HWSPINLOCK)
/**
* hwspinlock_get_by_index - Get a hardware spinlock by integer index
*
* This looks up and request a hardware spinlock. The index is relative to the
* client device; each device is assumed to have n hardware spinlock associated
* with it somehow, and this function finds and requests one of them.
*
* @dev: The client device.
* @index: The index of the hardware spinlock to request, within the
* client's list of hardware spinlock.
* @hws: A pointer to a hardware spinlock struct to initialize.
* @return 0 if OK, or a negative error code.
*/
int hwspinlock_get_by_index(struct udevice *dev,
int index, struct hwspinlock *hws);
/**
* Lock the hardware spinlock
*
* @hws: A hardware spinlock struct that previously requested by
* hwspinlock_get_by_index
* @timeout: Timeout value in msecs
* @return: 0 if OK, -ETIMEDOUT if timeout, -ve on other errors
*/
int hwspinlock_lock_timeout(struct hwspinlock *hws, unsigned int timeout);
/**
* Unlock the hardware spinlock
*
* @hws: A hardware spinlock struct that previously requested by
* hwspinlock_get_by_index
* @return: 0 if OK, -ve on error
*/
int hwspinlock_unlock(struct hwspinlock *hws);
#else
static inline int hwspinlock_get_by_index(struct udevice *dev,
int index,
struct hwspinlock *hws)
{
return -ENOSYS;
}
static inline int hwspinlock_lock_timeout(struct hwspinlock *hws,
int timeout)
{
return -ENOSYS;
}
static inline int hwspinlock_unlock(struct hwspinlock *hws)
{
return -ENOSYS;
}
#endif /* CONFIG_DM_HWSPINLOCK */
struct ofnode_phandle_args;
/**
* struct hwspinlock_ops - Driver model hwspinlock operations
*
* The uclass interface is implemented by all hwspinlock devices which use
* driver model.
*/
struct hwspinlock_ops {
/**
* of_xlate - Translate a client's device-tree (OF) hardware specifier.
*
* The hardware core calls this function as the first step in
* implementing a client's hwspinlock_get_by_*() call.
*
* @hws: The hardware spinlock struct to hold the translation
* result.
* @args: The hardware spinlock specifier values from device tree.
* @return 0 if OK, or a negative error code.
*/
int (*of_xlate)(struct hwspinlock *hws,
struct ofnode_phandle_args *args);
/**
* Lock the hardware spinlock
*
* @dev: hwspinlock Device
* @index: index of the lock to be used
* @return 0 if OK, -ve on error
*/
int (*lock)(struct udevice *dev, int index);
/**
* Unlock the hardware spinlock
*
* @dev: hwspinlock Device
* @index: index of the lock to be unlocked
* @return 0 if OK, -ve on error
*/
int (*unlock)(struct udevice *dev, int index);
/**
* Relax - optional
* Platform-specific relax method, called by hwspinlock core
* while spinning on a lock, between two successive call to
* lock
*
* @dev: hwspinlock Device
*/
void (*relax)(struct udevice *dev);
};
#endif /* _HWSPINLOCK_H_ */

4
include/spl.h
View File

@ -52,9 +52,9 @@ static inline bool u_boot_first_phase(void)
/* A string name for SPL or TPL */
#ifdef CONFIG_SPL_BUILD
# ifdef CONFIG_TPL_BUILD
# define SPL_TPL_NAME "tpl"
# define SPL_TPL_NAME "TPL"
# else
# define SPL_TPL_NAME "spl"
# define SPL_TPL_NAME "SPL"
# endif
# define SPL_TPL_PROMPT SPL_TPL_NAME ": "
#else

2
test/dm/Makefile
View File

@ -19,6 +19,7 @@ obj-$(CONFIG_CLK) += clk.o
obj-$(CONFIG_DM_ETH) += eth.o
obj-$(CONFIG_FIRMWARE) += firmware.o
obj-$(CONFIG_DM_GPIO) += gpio.o
obj-$(CONFIG_DM_HWSPINLOCK) += hwspinlock.o
obj-$(CONFIG_DM_I2C) += i2c.o
obj-$(CONFIG_LED) += led.o
obj-$(CONFIG_DM_MAILBOX) += mailbox.o
@ -54,4 +55,5 @@ obj-$(CONFIG_DM_SERIAL) += serial.o
obj-$(CONFIG_CPU) += cpu.o
obj-$(CONFIG_TEE) += tee.o
obj-$(CONFIG_VIRTIO_SANDBOX) += virtio.o
obj-$(CONFIG_DMA) += dma.o
endif

123
test/dm/dma.c Normal file
View File

@ -0,0 +1,123 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Direct Memory Access U-Class tests
*
* Copyright (C) 2018 Texas Instruments Incorporated <www.ti.com>
* Grygorii Strashko <grygorii.strashko@ti.com>
*/
#include <common.h>
#include <dm.h>
#include <dm/test.h>
#include <dma.h>
#include <test/ut.h>
static int dm_test_dma_m2m(struct unit_test_state *uts)
{
struct udevice *dev;
struct dma dma_m2m;
u8 src_buf[512];
u8 dst_buf[512];
size_t len = 512;
int i;
ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
ut_assertok(dma_get_by_name(dev, "m2m", &dma_m2m));
memset(dst_buf, 0, len);
for (i = 0; i < len; i++)
src_buf[i] = i;
ut_assertok(dma_memcpy(dst_buf, src_buf, len));
ut_assertok(memcmp(src_buf, dst_buf, len));
return 0;
}
DM_TEST(dm_test_dma_m2m, DM_TESTF_SCAN_FDT);
static int dm_test_dma(struct unit_test_state *uts)
{
struct udevice *dev;
struct dma dma_tx, dma_rx;
u8 src_buf[512];
u8 dst_buf[512];
void *dst_ptr;
size_t len = 512;
u32 meta1, meta2;
int i;
ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
ut_assertok(dma_enable(&dma_tx));
ut_assertok(dma_enable(&dma_rx));
memset(dst_buf, 0, len);
for (i = 0; i < len; i++)
src_buf[i] = i;
meta1 = 0xADADDEAD;
meta2 = 0;
dst_ptr = &dst_buf;
ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
ut_asserteq(0xADADDEAD, meta2);
ut_assertok(dma_disable(&dma_tx));
ut_assertok(dma_disable(&dma_rx));
ut_assertok(dma_free(&dma_tx));
ut_assertok(dma_free(&dma_rx));
ut_assertok(memcmp(src_buf, dst_buf, len));
return 0;
}
DM_TEST(dm_test_dma, DM_TESTF_SCAN_FDT);
static int dm_test_dma_rx(struct unit_test_state *uts)
{
struct udevice *dev;
struct dma dma_tx, dma_rx;
u8 src_buf[512];
u8 dst_buf[512];
void *dst_ptr;
size_t len = 512;
u32 meta1, meta2;
int i;
ut_assertok(uclass_get_device_by_name(UCLASS_DMA, "dma", &dev));
ut_assertok(dma_get_by_name(dev, "tx0", &dma_tx));
ut_assertok(dma_get_by_name(dev, "rx0", &dma_rx));
ut_assertok(dma_enable(&dma_tx));
ut_assertok(dma_enable(&dma_rx));
memset(dst_buf, 0, len);
for (i = 0; i < len; i++)
src_buf[i] = i;
meta1 = 0xADADDEAD;
meta2 = 0;
dst_ptr = NULL;
ut_assertok(dma_prepare_rcv_buf(&dma_tx, dst_buf, len));
ut_assertok(dma_send(&dma_tx, src_buf, len, &meta1));
ut_asserteq(len, dma_receive(&dma_rx, &dst_ptr, &meta2));
ut_asserteq(0xADADDEAD, meta2);
ut_asserteq_ptr(dst_buf, dst_ptr);
ut_assertok(dma_disable(&dma_tx));
ut_assertok(dma_disable(&dma_rx));
ut_assertok(dma_free(&dma_tx));
ut_assertok(dma_free(&dma_rx));
ut_assertok(memcmp(src_buf, dst_buf, len));
return 0;
}
DM_TEST(dm_test_dma_rx, DM_TESTF_SCAN_FDT);

40
test/dm/hwspinlock.c Normal file
View File

@ -0,0 +1,40 @@
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
*/
#include <common.h>
#include <dm.h>
#include <hwspinlock.h>
#include <asm/state.h>
#include <asm/test.h>
#include <dm/test.h>
#include <test/ut.h>
/* Test that hwspinlock driver functions are called */
static int dm_test_hwspinlock_base(struct unit_test_state *uts)
{
struct sandbox_state *state = state_get_current();
struct hwspinlock hws;
ut_assertok(uclass_get_device(UCLASS_HWSPINLOCK, 0, &hws.dev));
ut_assertnonnull(hws.dev);
ut_asserteq(false, state->hwspinlock);
hws.id = 0;
ut_assertok(hwspinlock_lock_timeout(&hws, 1));
ut_asserteq(true, state->hwspinlock);
ut_assertok(hwspinlock_unlock(&hws));
ut_asserteq(false, state->hwspinlock);
ut_assertok(hwspinlock_lock_timeout(&hws, 1));
ut_assertok(!hwspinlock_lock_timeout(&hws, 1));
ut_assertok(hwspinlock_unlock(&hws));
ut_assertok(!hwspinlock_unlock(&hws));
return 0;
}
DM_TEST(dm_test_hwspinlock_base, DM_TESTF_SCAN_PDATA | DM_TESTF_SCAN_FDT);

2
test/py/u_boot_console_base.py
View File

@ -16,7 +16,7 @@ import sys
import u_boot_spawn
# Regexes for text we expect U-Boot to send to the console.
pattern_u_boot_spl_signon = re.compile('(U-Boot spl \\d{4}\\.\\d{2}[^\r\n]*\\))')
pattern_u_boot_spl_signon = re.compile('(U-Boot SPL \\d{4}\\.\\d{2}[^\r\n]*\\))')
pattern_u_boot_main_signon = re.compile('(U-Boot \\d{4}\\.\\d{2}[^\r\n]*\\))')
pattern_stop_autoboot_prompt = re.compile('Hit any key to stop autoboot: ')
pattern_unknown_command = re.compile('Unknown command \'.*\' - try \'help\'')