ddr: marvell: a38x: add support for twin-die combined memory device
commit 6285efb8a118940877522c4c07bd7c64569b4f5f upstream. the twin-die combined memory device should be treatened as X8 device and not as X16 one Signed-off-by: Moti Buskila <motib@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> [ - the default value for twin_die_combined is set to NOT_COMBINED for all boards, as this was default behaviour prior this change ] Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
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@ -286,6 +286,7 @@ static struct mv_ddr_topology_map board_topology_map_1g = {
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MV_DDR_TIM_2T} }, /* timing */
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MV_DDR_TIM_2T} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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{0} /* timing parameters */
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};
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};
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@ -308,6 +309,7 @@ static struct mv_ddr_topology_map board_topology_map_2g = {
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MV_DDR_TIM_2T} }, /* timing */
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MV_DDR_TIM_2T} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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{0} /* timing parameters */
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};
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};
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@ -73,6 +73,7 @@ static struct mv_ddr_topology_map board_topology_map = {
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MV_DDR_TIM_DEFAULT} }, /* timing */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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{0} /* timing parameters */
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};
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};
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@ -94,6 +94,7 @@ static struct mv_ddr_topology_map board_topology_map = {
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MV_DDR_TIM_DEFAULT} }, /* timing */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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{0} /* timing parameters */
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};
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};
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@ -68,6 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = {
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MV_DDR_TIM_2T} }, /* timing */
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MV_DDR_TIM_2T} }, /* timing */
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BUS_MASK_32BIT_ECC, /* subphys mask */
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BUS_MASK_32BIT_ECC, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{0}, /* timing parameters */
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{ {0} }, /* electrical configuration */
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{ {0} }, /* electrical configuration */
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@ -71,6 +71,7 @@ static struct mv_ddr_topology_map ddr_topology_map = {
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MV_DDR_TIM_DEFAULT} }, /* timing */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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{0} /* timing parameters */
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@ -71,6 +71,7 @@ static struct mv_ddr_topology_map board_topology_map = {
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MV_DDR_TIM_DEFAULT} }, /* timing */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT_ECC, /* Busses mask */
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BUS_MASK_32BIT_ECC, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0} /* timing parameters */
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{0} /* timing parameters */
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};
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};
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@ -142,6 +142,7 @@ static struct mv_ddr_topology_map board_topology_map = {
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MV_DDR_TIM_DEFAULT} }, /* timing */
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MV_DDR_TIM_DEFAULT} }, /* timing */
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BUS_MASK_32BIT, /* Busses mask */
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BUS_MASK_32BIT, /* Busses mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined */
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{ {0} }, /* raw spd data */
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{0}, /* timing parameters */
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{ {0} }, /* electrical configuration */
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{ {0} }, /* electrical configuration */
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@ -14,6 +14,11 @@
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#define MV_DDR_MAX_BUS_NUM 9
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#define MV_DDR_MAX_BUS_NUM 9
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#define MV_DDR_MAX_IFACE_NUM 1
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#define MV_DDR_MAX_IFACE_NUM 1
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enum mv_ddr_twin_die {
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COMBINED,
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NOT_COMBINED,
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};
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struct bus_params {
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struct bus_params {
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/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
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/* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
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u8 cs_bitmask;
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u8 cs_bitmask;
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@ -47,6 +52,9 @@ struct if_params {
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/* The DDR frequency for each interfaces */
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/* The DDR frequency for each interfaces */
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enum mv_ddr_freq memory_freq;
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enum mv_ddr_freq memory_freq;
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/* ddr twin-die */
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enum mv_ddr_twin_die twin_die_combined;
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/*
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/*
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* delay CAS Write Latency
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* delay CAS Write Latency
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* - 0 for using default value (jedec suggested)
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* - 0 for using default value (jedec suggested)
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@ -113,6 +121,9 @@ struct mv_ddr_topology_map {
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/* source of ddr configuration data */
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/* source of ddr configuration data */
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enum mv_ddr_cfg_src cfg_src;
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enum mv_ddr_cfg_src cfg_src;
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/* ddr twin-die */
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enum mv_ddr_twin_die twin_die_combined;
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/* raw spd data */
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/* raw spd data */
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union mv_ddr_spd_data spd_data;
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union mv_ddr_spd_data spd_data;
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@ -193,6 +204,7 @@ struct mv_ddr_iface {
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/* ddr interface topology map */
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/* ddr interface topology map */
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struct mv_ddr_topology_map tm;
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struct mv_ddr_topology_map tm;
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};
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};
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struct mv_ddr_iface *mv_ddr_iface_get(void);
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struct mv_ddr_iface *mv_ddr_iface_get(void);
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@ -127,6 +127,11 @@ int mv_ddr_topology_map_update(void)
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speed_bin_index = iface_params->speed_bin_index;
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speed_bin_index = iface_params->speed_bin_index;
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freq = iface_params->memory_freq;
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freq = iface_params->memory_freq;
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if (tm->twin_die_combined == COMBINED) {
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iface_params->bus_width = MV_DDR_DEV_WIDTH_8BIT;
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iface_params->memory_size -= 1;
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}
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if (iface_params->cas_l == 0)
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if (iface_params->cas_l == 0)
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iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
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iface_params->cas_l = mv_ddr_cl_val_get(speed_bin_index, freq);
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@ -281,7 +286,6 @@ unsigned long long mv_ddr_mem_sz_per_cs_get(void)
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mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
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mem_sz_per_cs = (unsigned long long)mem_size[iface_params->memory_size] *
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(unsigned long long)sphys /
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(unsigned long long)sphys /
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(unsigned long long)sphys_per_dunit;
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(unsigned long long)sphys_per_dunit;
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return mem_sz_per_cs;
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return mem_sz_per_cs;
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}
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}
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