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arm: meson: remove static ethernet link setup 

The static ethernet link type config code is no more needed because now handled by
the meson8b glue driver, delete it.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong 2021-02-25 09:44:38 +01:00
parent 775998d451
commit 2fbd37001c
19 changed files with 2 additions and 215 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
arch/arm/include/asm/arch-meson/axg.h
View File

@ -31,26 +31,4 @@
#define AXG_AO_BL31_RSVMEM_SIZE_SHIFT 16
#define AXG_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
/* Peripherals registers */
#define AXG_PERIPHS_ADDR(off) (AXG_PERIPHS_BASE + ((off) << 2))
#define AXG_ETH_REG_0 AXG_PERIPHS_ADDR(0x50)
#define AXG_ETH_REG_1 AXG_PERIPHS_ADDR(0x51)
#define AXG_ETH_REG_0_PHY_INTF_RGMII BIT(0)
#define AXG_ETH_REG_0_PHY_INTF_RMII BIT(2)
#define AXG_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
#define AXG_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
#define AXG_ETH_REG_0_PHY_CLK_EN BIT(10)
#define AXG_ETH_REG_0_INVERT_RMII_CLK BIT(11)
#define AXG_ETH_REG_0_CLK_EN BIT(12)
/* HIU registers */
#define AXG_HIU_ADDR(off) (AXG_HIU_BASE + ((off) << 2))
#define AXG_MEM_PD_REG_0 AXG_HIU_ADDR(0x40)
/* Ethernet memory power domain */
#define AXG_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
#endif /* __AXG_H__ */

12
arch/arm/include/asm/arch-meson/eth.h
View File

@ -7,18 +7,6 @@
#ifndef __MESON_ETH_H__
#define __MESON_ETH_H__
#include <phy.h>
enum {
/* Use Internal RMII PHY */
MESON_USE_INTERNAL_RMII_PHY = 1,
};
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags);
/* Generate an unique MAC address based on the HW serial */
int meson_generate_serial_ethaddr(void);

35
arch/arm/include/asm/arch-meson/g12a.h
View File

@ -32,39 +32,4 @@
#define G12A_AO_BL31_RSVMEM_SIZE_SHIFT 16
#define G12A_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
/* Peripherals registers */
#define G12A_PERIPHS_ADDR(off) (G12A_PERIPHS_BASE + ((off) << 2))
#define G12A_ETH_REG_0 G12A_PERIPHS_ADDR(0x50)
#define G12A_ETH_REG_1 G12A_PERIPHS_ADDR(0x51)
#define G12A_ETH_REG_0_PHY_INTF_RGMII BIT(0)
#define G12A_ETH_REG_0_PHY_INTF_RMII BIT(2)
#define G12A_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
#define G12A_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
#define G12A_ETH_REG_0_PHY_CLK_EN BIT(10)
#define G12A_ETH_REG_0_INVERT_RMII_CLK BIT(11)
#define G12A_ETH_REG_0_CLK_EN BIT(12)
#define G12A_ETH_PHY_ADDR(off) (G12A_ETH_PHY_BASE + ((off) << 2))
#define ETH_PLL_CNTL0 G12A_ETH_PHY_ADDR(0x11)
#define ETH_PLL_CNTL1 G12A_ETH_PHY_ADDR(0x12)
#define ETH_PLL_CNTL2 G12A_ETH_PHY_ADDR(0x13)
#define ETH_PLL_CNTL3 G12A_ETH_PHY_ADDR(0x14)
#define ETH_PLL_CNTL4 G12A_ETH_PHY_ADDR(0x15)
#define ETH_PLL_CNTL5 G12A_ETH_PHY_ADDR(0x16)
#define ETH_PLL_CNTL6 G12A_ETH_PHY_ADDR(0x17)
#define ETH_PLL_CNTL7 G12A_ETH_PHY_ADDR(0x18)
#define ETH_PHY_CNTL0 G12A_ETH_PHY_ADDR(0x20)
#define ETH_PHY_CNTL1 G12A_ETH_PHY_ADDR(0x21)
#define ETH_PHY_CNTL2 G12A_ETH_PHY_ADDR(0x22)
/* HIU registers */
#define G12A_HIU_ADDR(off) (G12A_HIU_BASE + ((off) << 2))
#define G12A_MEM_PD_REG_0 G12A_HIU_ADDR(0x40)
/* Ethernet memory power domain */
#define G12A_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
#endif /* __G12A_H__ */

20
arch/arm/include/asm/arch-meson/gx.h
View File

@ -41,24 +41,4 @@
#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
#define GX_ETH_REG_0_PHY_INTF BIT(0)
#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
#define GX_ETH_REG_0_CLK_EN BIT(12)
/* HIU registers */
#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2))
#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)
/* Ethernet memory power domain */
#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
#endif /* __GX_H__ */

34
arch/arm/mach-meson/board-axg.c
View File

@ -91,40 +91,6 @@ static struct mm_region axg_mem_map[] = {
struct mm_region *mem_map = axg_mem_map;
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RGMII |
AXG_ETH_REG_0_TX_PHASE(1) |
AXG_ETH_REG_0_TX_RATIO(4) |
AXG_ETH_REG_0_PHY_CLK_EN |
AXG_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(AXG_ETH_REG_0, AXG_ETH_REG_0_PHY_INTF_RMII |
AXG_ETH_REG_0_INVERT_RMII_CLK |
AXG_ETH_REG_0_CLK_EN);
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
/* Enable power gate */
clrbits_le32(AXG_MEM_PD_REG_0, AXG_MEM_PD_REG_0_ETH_MASK);
}
#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_gx_dwc2_data;

31
arch/arm/mach-meson/board-g12a.c
View File

@ -97,37 +97,6 @@ static struct mm_region g12a_mem_map[] = {
struct mm_region *mem_map = g12a_mem_map;
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RGMII |
G12A_ETH_REG_0_TX_PHASE(1) |
G12A_ETH_REG_0_TX_RATIO(4) |
G12A_ETH_REG_0_PHY_CLK_EN |
G12A_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(G12A_ETH_REG_0, G12A_ETH_REG_0_PHY_INTF_RMII |
G12A_ETH_REG_0_INVERT_RMII_CLK |
G12A_ETH_REG_0_CLK_EN);
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
}
#if CONFIG_IS_ENABLED(USB_DWC3_MESON_G12A) && \
CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_g12a_dwc2_data;

35
arch/arm/mach-meson/board-gx.c
View File

@ -109,41 +109,6 @@ static struct mm_region gx_mem_map[] = {
struct mm_region *mem_map = gx_mem_map;
/* Configure the Ethernet MAC with the requested interface mode
* with some optional flags.
*/
void meson_eth_init(phy_interface_t mode, unsigned int flags)
{
switch (mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
/* Set RGMII mode */
setbits_le32(GX_ETH_REG_0, GX_ETH_REG_0_PHY_INTF |
GX_ETH_REG_0_TX_PHASE(1) |
GX_ETH_REG_0_TX_RATIO(4) |
GX_ETH_REG_0_PHY_CLK_EN |
GX_ETH_REG_0_CLK_EN);
break;
case PHY_INTERFACE_MODE_RMII:
/* Set RMII mode */
out_le32(GX_ETH_REG_0, GX_ETH_REG_0_INVERT_RMII_CLK |
GX_ETH_REG_0_CLK_EN);
if (!IS_ENABLED(CONFIG_MESON_GXBB))
writel(0x10110181, GX_ETH_REG_2);
break;
default:
printf("Invalid Ethernet interface mode\n");
return;
}
}
#if CONFIG_IS_ENABLED(USB_DWC3_MESON_GXL) && \
CONFIG_IS_ENABLED(USB_GADGET_DWC2_OTG)
static struct dwc2_plat_otg_data meson_gx_dwc2_data;

2
board/amlogic/beelink-s922x/beelink-s922x.c
View File

@ -28,8 +28,6 @@ int misc_init_r(void)
meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
env_set("soc_rev", tmp);
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
efuse_mac_addr, EFUSE_MAC_SIZE);

2
board/amlogic/odroid-n2/odroid-n2.c
View File

@ -115,8 +115,6 @@ int misc_init_r(void)
meson_get_soc_rev(tmp, sizeof(tmp)) > 0)
env_set("soc_rev", tmp);
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
efuse_mac_addr, EFUSE_MAC_SIZE);

2
board/amlogic/p200/p200.c
View File

@ -25,8 +25,6 @@ int misc_init_r(void)
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);

2
board/amlogic/p201/p201.c
View File

@ -25,8 +25,6 @@ int misc_init_r(void)
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_eth_init(PHY_INTERFACE_MODE_RMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);

3
board/amlogic/p212/p212.c
View File

@ -26,9 +26,6 @@ int misc_init_r(void)
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_USE_INTERNAL_RMII_PHY);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);

2
board/amlogic/q200/q200.c
View File

@ -26,8 +26,6 @@ int misc_init_r(void)
char serial[EFUSE_SN_SIZE];
ssize_t len;
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
mac_addr, EFUSE_MAC_SIZE);

2
board/amlogic/s400/s400.c
View File

@ -16,8 +16,6 @@
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
meson_generate_serial_ethaddr();
return 0;

3
board/amlogic/sei510/sei510.c
View File

@ -18,9 +18,6 @@
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_USE_INTERNAL_RMII_PHY);
meson_generate_serial_ethaddr();
env_set("serial#", "AMLG12ASEI510");

3
board/amlogic/sei610/sei610.c
View File

@ -18,9 +18,6 @@
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_USE_INTERNAL_RMII_PHY);
meson_generate_serial_ethaddr();
env_set("serial#", "AMLG12ASEI610");

3
board/amlogic/u200/u200.c
View File

@ -16,8 +16,7 @@
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RMII,
MESON_USE_INTERNAL_RMII_PHY);
meson_generate_serial_ethaddr();
return 0;
}

2
board/amlogic/vim3/vim3.c
View File

@ -149,8 +149,6 @@ int misc_init_r(void)
char efuse_mac_addr[EFUSE_MAC_SIZE], tmp[3];
ssize_t len;
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
len = meson_sm_read_efuse(EFUSE_MAC_OFFSET,
efuse_mac_addr, EFUSE_MAC_SIZE);

2
board/amlogic/w400/w400.c
View File

@ -14,7 +14,7 @@
int misc_init_r(void)
{
meson_eth_init(PHY_INTERFACE_MODE_RGMII, 0);
meson_generate_serial_ethaddr();
return 0;
}