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https://github.com/brain-hackers/u-boot-brain
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phy: marvell: cp110: let the firmware perform training for XFI
Replace the XFI training with appropriate SMC call, so the firmware will perform exact initialization. Update Stefan 2021-03-23: Move comphy_smc() function to an earlier place - necessary for the mainline merge. Change-Id: I789b130b05529dc80dadcf66aef407d93595b762 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Igal Liberman <igall@marvell.com>
This commit is contained in:
Grzegorz Jaszczyk
Stefan Roese
parent
f635c3b3a2
commit
2e28b597fa
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@ -28,6 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define MV_SIP_COMPHY_POWER_ON 0x82000001
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#define MV_SIP_COMPHY_POWER_OFF 0x82000002
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#define MV_SIP_COMPHY_PLL_LOCK 0x82000003
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#define MV_SIP_COMPHY_XFI_TRAIN 0x82000004
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/* Used to distinguish between different possible callers (U-boot/Linux) */
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#define COMPHY_CALLER_UBOOT (0x1 << 21)
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@ -133,196 +134,6 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val,
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return 0;
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}
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/* This function performs RX training for single FFE value.
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* The result of the RX training is located in:
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* Saved DFE values Register[10:15].
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*
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* The result is returned to the caller using *result
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*
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* Return '1' on succsess.
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* Return '0' on failure.
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*/
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static int comphy_cp110_test_single_ffe(
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struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane, u32 ffe, u32 *result)
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{
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u32 mask, data, timeout;
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void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
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void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane);
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void __iomem *sd_ip_addr = SD_ADDR(hpipe_base_addr, lane);
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/* Configure PRBS counters */
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mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK;
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data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_DATA_MASK;
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data = 0x64 << HPIPE_PHY_TEST_DATA_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask);
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mask = HPIPE_PHY_TEST_EN_MASK;
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data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mdelay(50);
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/* Set the FFE value */
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mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK;
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data = ffe << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
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/* Start RX training */
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mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
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data = 1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
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/* Check the result of RX training */
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timeout = RX_TRAINING_TIMEOUT;
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while (timeout) {
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data = readl(sd_ip_addr + SD_EXTERNAL_STATUS1_REG);
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if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK)
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break;
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mdelay(1);
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timeout--;
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}
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if (timeout == 0)
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return 0;
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if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK)
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return 0;
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/* Stop RX training */
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mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK;
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data = 0 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET;
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reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask);
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/* Read the result */
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data = readl(hpipe_addr + HPIPE_SAVED_DFE_VALUES_REG);
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data &= HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK;
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data >>= HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET;
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*result = data;
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printf("FFE = %d, result = 0x%x\n", ffe, *result);
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/* Clear the PRBS counters */
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mask = HPIPE_PHY_TEST_RESET_MASK;
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data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET;
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mask |= HPIPE_PHY_TEST_EN_MASK;
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data |= 0x0 << HPIPE_PHY_TEST_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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mask = HPIPE_PHY_TEST_RESET_MASK;
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data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET;
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reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask);
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return 1;
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}
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/* This function performs RX training for all FFE possible values.
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* We get the result for each FFE and eventually the best FFE will
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* be used and set to the HW.
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*
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* Return '1' on succsess.
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* Return '0' on failure.
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*/
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int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane)
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{
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u32 mask, data, i, rx_train_result;
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u32 max_rx_train = 0, max_rx_train_index = 0;
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void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr;
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void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane);
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int ret;
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debug_enter();
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if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
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pr_err("Comphy %d isn't configured to SFI\n", lane);
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return 0;
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}
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/* Configure SQ threshold and CDR lock */
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mask = HPIPE_SQUELCH_THRESH_IN_MASK;
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data = 0xc << HPIPE_SQUELCH_THRESH_IN_OFFSET;
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reg_set(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG, data, mask);
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mask = HPIPE_SQ_DEGLITCH_WIDTH_P_MASK;
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data = 0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET;
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mask |= HPIPE_SQ_DEGLITCH_WIDTH_N_MASK;
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data |= 0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET;
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mask |= HPIPE_SQ_DEGLITCH_EN_MASK;
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data |= 0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_SQ_GLITCH_FILTER_CTRL, data, mask);
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mask = HPIPE_CDR_LOCK_DET_EN_MASK;
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data = 0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET;
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reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask);
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udelay(100);
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/* Determine if we have a cable attached to this comphy, if not,
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* we can't perform RX training.
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*/
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data = readl(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG);
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if (data & HPIPE_SQUELCH_DETECTED_MASK) {
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pr_err("Squelsh is not detected, can't perform RX training\n");
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return 0;
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}
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data = readl(hpipe_addr + HPIPE_LOOPBACK_REG);
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if (!(data & HPIPE_CDR_LOCK_MASK)) {
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pr_err("CDR is not locked, can't perform RX training\n");
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return 0;
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}
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/* Do preparations for RX training */
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mask = HPIPE_DFE_RES_FORCE_MASK;
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data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask);
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mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK;
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data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET;
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mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK;
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data |= 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET;
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reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask);
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/* Performs RX training for all possible FFE (Feed Forward
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* Equalization, possible values are 0-7).
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* We update the best value reached and the FFE which gave this value.
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*/
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for (i = 0; i < MAX_NUM_OF_FFE; i++) {
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rx_train_result = 0;
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ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane,
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i, &rx_train_result);
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if (ret && (rx_train_result > max_rx_train)) {
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max_rx_train = rx_train_result;
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max_rx_train_index = i;
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}
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}
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/* If we were able to determine which FFE gives the best value,
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* now we need to set it and run RX training again (only for this
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* FFE).
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*/
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if (max_rx_train) {
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ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane,
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max_rx_train_index,
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&rx_train_result);
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if (ret == 1)
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printf("RX Training passed(FFE = %d, result = 0x%x)\n",
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max_rx_train_index, rx_train_result);
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} else {
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pr_err("RX training failed\n");
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ret = 0;
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}
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debug_exit();
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return ret;
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}
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static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
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u32 lane, u32 mode)
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{
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@ -343,6 +154,34 @@ static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
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return pregs.regs[0] ? 0 : 1;
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}
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/* This function performs RX training for all FFE possible values.
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* We get the result for each FFE and eventually the best FFE will
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* be used and set to the HW.
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*
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* Return '1' on succsess.
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* Return '0' on failure.
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*/
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int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
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u32 lane)
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{
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int ret;
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debug_enter();
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if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
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pr_err("Comphy %d isn't configured to SFI\n", lane);
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return 0;
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}
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/* Mode is not relevant for xfi training */
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ret = comphy_smc(MV_SIP_COMPHY_XFI_TRAIN,
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ptr_chip_cfg->comphy_base_addr, lane, 0);
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debug_exit();
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return ret;
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}
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static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
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void __iomem *comphy_base_addr, int cp_index,
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u32 type)
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