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phy: marvell: cp110: let the firmware configure comphy for USB

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Replace the comphy initialization for USB with appropriate SMC call,
so the firmware will execute required serdes configuration.

Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
This commit is contained in:
Grzegorz Jaszczyk 2018-03-29 12:30:20 +02:00 committed by Stefan Roese
parent 26d9763f3b
commit f635c3b3a2
1 changed files with 9 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

133
drivers/phy/marvell/comphy_cp110.c
View File

@ -323,128 +323,6 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
return ret;
}
static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base,
void __iomem *comphy_base)
{
u32 mask, data, ret = 1;
void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
void __iomem *addr;
debug_enter();
debug("stage: RFU configurations - hard reset comphy\n");
/* RFU configurations - hard reset comphy */
mask = COMMON_PHY_CFG1_PWR_UP_MASK;
data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
mask |= COMMON_PHY_PHY_MODE_MASK;
data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET;
reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
/* release from hard reset */
mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
/* Wait 1ms - until band gap and ref clock ready */
mdelay(1);
/* Start comphy Configuration */
debug("stage: Comphy configuration\n");
/* Set PIPE soft reset */
mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK;
data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET;
/* Set PHY datapath width mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET;
/* Set Data bus width USB mode for V0 */
mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET;
/* Set CORE_CLK output frequency for 250Mhz */
mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK;
data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET;
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask);
/* Set PLL ready delay for 0x2 */
reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG,
0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET,
HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK);
/* Set reference clock to come from group 1 - 25Mhz */
reg_set(hpipe_addr + HPIPE_MISC_REG,
0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET,
HPIPE_MISC_REFCLK_SEL_MASK);
/* Set reference frequcency select - 0x2 */
mask = HPIPE_PWR_PLL_REF_FREQ_MASK;
data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET;
/* Set PHY mode to USB - 0x5 */
mask |= HPIPE_PWR_PLL_PHY_MODE_MASK;
data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET;
reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask);
/* Set the amount of time spent in the LoZ state - set for 0x7 */
reg_set(hpipe_addr + HPIPE_GLOBAL_PM_CTRL,
0x7 << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET,
HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK);
/* Set max PHY generation setting - 5Gbps */
reg_set(hpipe_addr + HPIPE_INTERFACE_REG,
0x1 << HPIPE_INTERFACE_GEN_MAX_OFFSET,
HPIPE_INTERFACE_GEN_MAX_MASK);
/* Set select data width 20Bit (SEL_BITS[2:0]) */
reg_set(hpipe_addr + HPIPE_LOOPBACK_REG,
0x1 << HPIPE_LOOPBACK_SEL_OFFSET,
HPIPE_LOOPBACK_SEL_MASK);
/* select de-emphasize 3.5db */
reg_set(hpipe_addr + HPIPE_LANE_CONFIG0_REG,
0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET,
HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK);
/* override tx margining from the MAC */
reg_set(hpipe_addr + HPIPE_TST_MODE_CTRL_REG,
0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET,
HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK);
/* Start analog paramters from ETP(HW) */
debug("stage: Analog paramters from ETP(HW)\n");
/* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */
mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK;
data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET;
/* Set Override PHY DFE control pins for 0x1 */
mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK;
data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET;
/* Set Spread Spectrum Clock Enable fot 0x1 */
mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK;
data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET;
reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask);
/* End of analog parameters */
debug("stage: Comphy power up\n");
/* Release from PIPE soft reset */
reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG,
0x0 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET,
HPIPE_RST_CLK_CTRL_PIPE_RST_MASK);
/* wait 15ms - for comphy calibration done */
debug("stage: Check PLL\n");
/* Read lane status */
addr = hpipe_addr + HPIPE_LANE_STATUS1_REG;
data = HPIPE_LANE_STATUS1_PCLK_EN_MASK;
mask = data;
data = polling_with_timeout(addr, data, mask, 15000);
if (data != 0) {
debug("Read from reg = %p - value = 0x%x\n",
hpipe_addr + HPIPE_LANE_STATUS1_REG, data);
pr_err("HPIPE_LANE_STATUS1_PCLK_EN_MASK is 0\n");
ret = 0;
}
debug_exit();
return ret;
}
static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
u32 lane, u32 mode)
{
@ -960,9 +838,16 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
break;
case COMPHY_TYPE_USB3_HOST0:
case COMPHY_TYPE_USB3_HOST1:
mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3H_MODE);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
case COMPHY_TYPE_USB3_DEVICE:
ret = comphy_usb3_power_up(lane, hpipe_base_addr,
comphy_base_addr);
mode = COMPHY_FW_MODE_FORMAT(COMPHY_USB3D_MODE);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
case COMPHY_TYPE_SGMII0:
case COMPHY_TYPE_SGMII1: