arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file
This patch move u-boot properties to -u-boot.dtsi file. Signed-off-by: Sam Shih <sam.shih@mediatek.com> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
This commit is contained in:
Sam Shih
Tom Rini
parent
c7fbc62082
commit
098c063765
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@ -0,0 +1,29 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sam Shih <sam.shih@mediatek.com>
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*/
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&topckgen {
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u-boot,dm-pre-reloc;
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};
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&topckgen {
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u-boot,dm-pre-reloc;
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};
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&pericfg {
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u-boot,dm-pre-reloc;
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};
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&timer0 {
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u-boot,dm-pre-reloc;
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};
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&apmixedsys {
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u-boot,dm-pre-reloc;
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};
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&uart2 {
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u-boot,dm-pre-reloc;
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};
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@ -101,21 +101,18 @@
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compatible = "mediatek,mt7623-topckgen";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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infracfg: syscon@10001000 {
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compatible = "mediatek,mt7623-infracfg", "syscon";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pericfg: syscon@10003000 {
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compatible = "mediatek,mt7623-pericfg", "syscon";
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reg = <0x10003000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pinctrl: pinctrl@10005000 {
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@ -155,7 +152,6 @@
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&system_clk>;
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clock-names = "system-clk";
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u-boot,dm-pre-reloc;
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};
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sysirq: interrupt-controller@10200100 {
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@ -170,7 +166,6 @@
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compatible = "mediatek,mt7623-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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gic: interrupt-controller@10211000 {
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@ -215,7 +210,6 @@
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<&pericfg CLK_PERI_UART2>;
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clock-names = "baud", "bus";
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status = "disabled";
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u-boot,dm-pre-reloc;
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};
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uart3: serial@11005000 {
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include "mt7623.dtsi"
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#include "mt7623-u-boot.dtsi"
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/ {
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model = "Bananapi BPI-R2";
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@ -22,3 +22,39 @@
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#endif
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};
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};
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&infracfg {
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u-boot,dm-pre-reloc;
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};
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&pericfg {
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u-boot,dm-pre-reloc;
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};
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&timer0 {
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u-boot,dm-pre-reloc;
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};
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&mcucfg {
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u-boot,dm-pre-reloc;
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};
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&dramc {
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u-boot,dm-pre-reloc;
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};
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&apmixedsys {
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u-boot,dm-pre-reloc;
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};
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&topckgen {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&snfi {
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u-boot,dm-pre-reloc;
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};
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@ -7,6 +7,7 @@
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/dts-v1/;
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#include "mt7629.dtsi"
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#include "mt7629-rfb-u-boot.dtsi"
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/ {
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model = "MediaTek MT7629 RFB";
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@ -68,14 +68,12 @@
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compatible = "mediatek,mt7629-infracfg", "syscon";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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pericfg: syscon@10002000 {
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compatible = "mediatek,mt7629-pericfg", "syscon";
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reg = <0x10002000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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timer0: timer@10004000 {
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@ -85,7 +83,6 @@
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clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
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<&topckgen CLK_TOP_10M_SEL>;
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clock-names = "mux", "src";
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u-boot,dm-pre-reloc;
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};
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scpsys: scpsys@10006000 {
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@ -103,7 +100,6 @@
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compatible = "mediatek,mt7629-mcucfg", "syscon";
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reg = <0x10200000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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sysirq: interrupt-controller@10200a80 {
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@ -124,21 +120,18 @@
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<&topckgen CLK_TOP_MEM_SEL>,
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<&topckgen CLK_TOP_DMPLL>;
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clock-names = "phy", "phy_mux", "mem", "mem_mux";
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u-boot,dm-pre-reloc;
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};
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apmixedsys: clock-controller@10209000 {
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compatible = "mediatek,mt7629-apmixedsys";
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reg = <0x10209000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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topckgen: clock-controller@10210000 {
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compatible = "mediatek,mt7629-topckgen";
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reg = <0x10210000 0x1000>;
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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watchdog: watchdog@10212000 {
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@ -186,7 +179,6 @@
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status = "disabled";
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assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
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u-boot,dm-pre-reloc;
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};
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uart1: serial@11003000 {
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@ -228,7 +220,6 @@
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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};
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ethsys: syscon@1b000000 {
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