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Merge pull request #21 from brain-hackers/x1-2021.07+fslc 

Support PW-H1 for 2021.07+fslc
This commit is contained in:
Takumi Sueda 2022-01-24 23:46:28 +09:00 committed by GitHub
parent 467a6e6d35 c6fab5a020
commit 0449ff1430
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 145 additions and 179 deletions
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208
arch/arm/dts/imx7ulp-pwh1.dts
View File

@ -11,11 +11,11 @@
#include "imx7ulp.dtsi" #include "imx7ulp.dtsi"
/ { / {
model = "NXP i.MX7ULP EVK"; model = "NXP i.MX7ULP Sharp Brain PW-H1";
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system"; compatible = "fsl,imx7ulp-pwh1", "fsl,imx7ulp", "Generic DT based system";
chosen { chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200"; bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
stdout-path = &lpuart4; stdout-path = &lpuart4;
}; };
@ -47,6 +47,13 @@
#reset-cells = <0>; #reset-cells = <0>;
}; };
emmc_sdhc1_pwrseq: emmc-sdhc1-reset {
compatible = "mmc-pwrseq-emmc";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_rst>;
reset-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
};
regulators { regulators {
compatible = "simple-bus"; compatible = "simple-bus";
#address-cells = <1>; #address-cells = <1>;
@ -66,7 +73,7 @@
compatible = "regulator-fixed"; compatible = "regulator-fixed";
reg = <0>; reg = <0>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>; pinctrl-0 = <&pinctrl_usbotg1_vbus>;
regulator-name = "usb_otg1_vbus"; regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
@ -77,6 +84,8 @@
reg_vsd_3v3: regulator@1 { reg_vsd_3v3: regulator@1 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
reg = <1>; reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc0_vsd>;
regulator-name = "VSD_3V3"; regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
@ -84,33 +93,23 @@
enable-active-high; enable-active-high;
}; };
reg_vsd_3v3b: regulator@2 { reg_vmmc_3v3: regulator@2 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
reg = <2>; reg = <2>;
regulator-name = "VSD_3V3B"; regulator-name = "VMMC_3V3";
regulator-min-microvolt = <3300000>; regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
}; };
reg_vsd_1v8: regulator@3 { reg_vqmmc_1v8: regulator@3 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
reg = <3>; reg = <3>;
regulator-name = "VSD_1V8"; regulator-name = "VQMMC_1V8";
regulator-min-microvolt = <1800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>; regulator-max-microvolt = <1800000>;
enable-active-high;
}; };
}; };
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_extcon_usb1>;
};
pf1550-rpmsg { pf1550-rpmsg {
compatible = "fsl,pf1550-rpmsg"; compatible = "fsl,pf1550-rpmsg";
sw1_reg: SW1 { sw1_reg: SW1 {
@ -172,152 +171,144 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_1>; pinctrl-0 = <&pinctrl_hog_1>;
imx7ulp-evk { imx7ulp-pwh1 {
pinctrl_hog_1: hoggrp-1 { pinctrl_hog_1: hoggrp-1 {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */ IMX7ULP_PAD_PTC1__PTC1 0x20000
ULP1_PAD_PTC1__PTC1 0x20100
ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
>; >;
}; };
pinctrl_backlight: backlight_grp { pinctrl_backlight: backlight_grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTF2__PTF2 0x20100 IMX7ULP_PAD_PTF2__PTF2 0x20000
>; >;
}; };
pinctrl_lpi2c5: lpi2c5grp { pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTC4__LPI2C5_SCL 0x527 IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
ULP1_PAD_PTC5__LPI2C5_SDA 0x527 IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
>; >;
}; };
pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp { pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTC19__PTC19 0x20103 IMX7ULP_PAD_PTC19__PTC19 0x20003
>; >;
}; };
pinctrl_lpuart4: lpuart4grp { pinctrl_lpuart4: lpuart4grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTC3__LPUART4_RX 0x400 IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
ULP1_PAD_PTC2__LPUART4_TX 0x400 IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
>; >;
}; };
pinctrl_lpuart6: lpuart6grp { pinctrl_lpuart6: lpuart6grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTE10__LPUART6_TX 0x400 IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
ULP1_PAD_PTE11__LPUART6_RX 0x400 IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
ULP1_PAD_PTE9__LPUART6_RTS_B 0x400 IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
ULP1_PAD_PTE8__LPUART6_CTS_B 0x400 IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */ IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
>; >;
}; };
pinctrl_lpuart7: lpuart7grp { pinctrl_lpuart7: lpuart7grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTF14__LPUART7_TX 0x400 IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
ULP1_PAD_PTF15__LPUART7_RX 0x400 IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
ULP1_PAD_PTF13__LPUART7_RTS_B 0x400 IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
ULP1_PAD_PTF12__LPUART7_CTS_B 0x400 IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
>; >;
}; };
pinctrl_usdhc0: usdhc0grp { pinctrl_usdhc0: usdhc0grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTD1__SDHC0_CMD 0x843 IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
ULP1_PAD_PTD2__SDHC0_CLK 0x10843 IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10043
ULP1_PAD_PTD7__SDHC0_D3 0x843 IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
ULP1_PAD_PTD8__SDHC0_D2 0x843 IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
ULP1_PAD_PTD9__SDHC0_D1 0x843 IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
ULP1_PAD_PTD10__SDHC0_D0 0x843 IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
>;
};
pinctrl_usdhc0_vsd: usdhc0grp_vsd {
fsl,pins = <
IMX7ULP_PAD_PTD0__PTD0 0x20000 /* SD_POWER_FET_ON */
>; >;
}; };
pinctrl_usdhc0_8bit: usdhc0grp_8bit { pinctrl_usdhc0_8bit: usdhc0grp_8bit {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTD1__SDHC0_CMD 0x843 IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
ULP1_PAD_PTD2__SDHC0_CLK 0x843 IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
ULP1_PAD_PTD3__SDHC0_D7 0x843 IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
ULP1_PAD_PTD4__SDHC0_D6 0x843 IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
ULP1_PAD_PTD5__SDHC0_D5 0x843 IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
ULP1_PAD_PTD6__SDHC0_D4 0x843 IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
ULP1_PAD_PTD7__SDHC0_D3 0x843 IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
ULP1_PAD_PTD8__SDHC0_D2 0x843 IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
ULP1_PAD_PTD9__SDHC0_D1 0x843 IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
ULP1_PAD_PTD10__SDHC0_D0 0x843 IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>; >;
}; };
pinctrl_lpi2c7: lpi2c7grp { pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTF12__LPI2C7_SCL 0x527 IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
ULP1_PAD_PTF13__LPI2C7_SDA 0x527 IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
>; >;
}; };
pinctrl_lpspi3: lpspi3grp { pinctrl_lpspi3: lpspi3grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTF16__LPSPI3_SIN 0x300 IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
ULP1_PAD_PTF17__LPSPI3_SOUT 0x300 IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
ULP1_PAD_PTF18__LPSPI3_SCK 0x300 IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
ULP1_PAD_PTF19__LPSPI3_PCS0 0x300 IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
>; >;
}; };
pinctrl_usb_otg1: usbotg1grp { pinctrl_usbotg1_vbus: otg1vbusgrp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTC0__PTC0 0x30100 IMX7ULP_PAD_PTC0__PTC0 0x20000
>; >;
}; };
pinctrl_extcon_usb1: extcon1grp { pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTC8__PTC8 0x30103 IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>; >;
}; };
pinctrl_usdhc1: usdhc1grp { pinctrl_usdhc1_8bit: usdhc1grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTE3__SDHC1_CMD 0x843 IMX7ULP_PAD_PTE3__SDHC1_CMD 0x03
ULP1_PAD_PTE2__SDHC1_CLK 0x843 IMX7ULP_PAD_PTE2__SDHC1_CLK 0x02
ULP1_PAD_PTE1__SDHC1_D0 0x843 IMX7ULP_PAD_PTE1__SDHC1_D0 0x03
ULP1_PAD_PTE0__SDHC1_D1 0x843 IMX7ULP_PAD_PTE0__SDHC1_D1 0x03
ULP1_PAD_PTE5__SDHC1_D2 0x843 IMX7ULP_PAD_PTE5__SDHC1_D2 0x03
ULP1_PAD_PTE4__SDHC1_D3 0x843 IMX7ULP_PAD_PTE4__SDHC1_D3 0x03
>; IMX7ULP_PAD_PTE6__SDHC1_D4 0x03
}; IMX7ULP_PAD_PTE7__SDHC1_D5 0x03
IMX7ULP_PAD_PTE8__SDHC1_D6 0x03
pinctrl_usdhc1_8bit: usdhc1grp_8bit { IMX7ULP_PAD_PTE9__SDHC1_D7 0x03
fsl,pins = < IMX7ULP_PAD_PTE10__SDHC1_DQS 0x03
ULP1_PAD_PTE3__SDHC1_CMD 0x803
ULP1_PAD_PTE2__SDHC1_CLK 0x802
ULP1_PAD_PTE9__SDHC1_D7 0x803
ULP1_PAD_PTE8__SDHC1_D6 0x803
ULP1_PAD_PTE7__SDHC1_D5 0x803
ULP1_PAD_PTE6__SDHC1_D4 0x803
ULP1_PAD_PTE4__SDHC1_D3 0x803
ULP1_PAD_PTE5__SDHC1_D2 0x803
ULP1_PAD_PTE0__SDHC1_D1 0x803
ULP1_PAD_PTE1__SDHC1_D0 0x803
>; >;
}; };
pinctrl_usdhc1_rst: usdhc1grp_rst { pinctrl_usdhc1_rst: usdhc1grp_rst {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */ IMX7ULP_PAD_PTE11__PTE11 0x10003
>; >;
}; };
pinctrl_wifi: wifigrp { pinctrl_dsi_hdmi: dsi_hdmi_grp {
fsl,pins = < fsl,pins = <
ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */ IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
>; >;
}; };
}; };
@ -328,7 +319,7 @@
disp-dev = "mipi_dsi_northwest"; disp-dev = "mipi_dsi_northwest";
display = <&display0>; display = <&display0>;
display0: display { display0: display@0 {
bits-per-pixel = <16>; bits-per-pixel = <16>;
bus-width = <24>; bus-width = <24>;
@ -367,21 +358,6 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>; pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay"; status = "okay";
fxas2100x@20 {
compatible = "fsl,fxas2100x";
reg = <0x20>;
};
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
}; };
&lpspi3 { &lpspi3 {
@ -430,22 +406,26 @@
&usbotg1 { &usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>; vbus-supply = <&reg_usb_otg1_vbus>;
extcon = <0>, <&extcon_usb1>; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
srp-disable; srp-disable;
hnp-disable; hnp-disable;
adp-disable; adp-disable;
status = "okay"; status = "okay";
}; };
&usbphy1 {
fsl,tx-d-cal = <88>;
};
&usdhc0 { &usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>; pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0>; pinctrl-1 = <&pinctrl_usdhc0>;
pinctrl-2 = <&pinctrl_usdhc0>; pinctrl-2 = <&pinctrl_usdhc0>;
pinctrl-3 = <&pinctrl_usdhc0>; pinctrl-3 = <&pinctrl_usdhc0>;
cd-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; broken-cd;
vmmc-supply = <&reg_vsd_3v3>; vmmc-supply = <&reg_vsd_3v3>;
vqmmc-supply = <&vldo2_reg>;
status = "okay"; status = "okay";
}; };
@ -455,8 +435,10 @@
pinctrl-1 = <&pinctrl_usdhc1_8bit>; pinctrl-1 = <&pinctrl_usdhc1_8bit>;
pinctrl-2 = <&pinctrl_usdhc1_8bit>; pinctrl-2 = <&pinctrl_usdhc1_8bit>;
pinctrl-3 = <&pinctrl_usdhc1_8bit>; pinctrl-3 = <&pinctrl_usdhc1_8bit>;
data-bus = <8>;
vmmc-supply = <&reg_vsd_1v8>; non-removable;
vqmmc-supply = <&vldo1_reg>; vmmc-supply = <&reg_vmmc_3v3>;
vqmmc-supply = <&reg_vqmmc_1v8>;
mmc-pwrseq = <&emmc_sdhc1_pwrseq>;
status = "okay"; status = "okay";
}; };

3
arch/arm/mach-imx/mx7ulp/Kconfig
View File

@ -27,7 +27,8 @@ config TARGET_MX7ULP_EVK
select SYS_ARCH_TIMER select SYS_ARCH_TIMER
config TARGET_PWH1 config TARGET_PWH1
bool "Support PW-H1 board" bool "Support PW-H1 board"
select MX7ULP
select SYS_ARCH_TIMER select SYS_ARCH_TIMER
endchoice endchoice

2
board/sharp/pwh1/imximage.cfg
View File

@ -24,7 +24,7 @@ BOOT_FROM sd
#ifdef CONFIG_USE_IMXIMG_PLUGIN #ifdef CONFIG_USE_IMXIMG_PLUGIN
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ /*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000 PLUGIN board/sharp/pwh1/plugin.bin 0x2F020000
#else #else
#ifdef CONFIG_SECURE_BOOT #ifdef CONFIG_SECURE_BOOT

1
board/sharp/pwh1/mx7ulp_pwh1.c
View File

@ -4,6 +4,7 @@
*/ */
#include <common.h> #include <common.h>
#include <asm/global_data.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/arch/mx7ulp-pins.h> #include <asm/arch/mx7ulp-pins.h>

35
configs/pwh1_defconfig
View File

@ -1,33 +1,38 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX7ULP=y CONFIG_ARCH_MX7ULP=y
CONFIG_SYS_TEXT_BASE=0x60000000 CONFIG_SYS_TEXT_BASE=0x60000000
CONFIG_TARGET_PWH1=y
CONFIG_NR_DRAM_BANKS=1 CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x60000000
CONFIG_SYS_MEMTEST_END=0x66000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-pwh1"
CONFIG_TARGET_PWH1=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/sharp/pwh1/imximage.cfg" CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/sharp/pwh1/imximage.cfg"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_ELF is not set CONFIG_CMD_GPIO=y
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_MMC=y CONFIG_CMD_MMC=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-pwh1" CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set # CONFIG_NET is not set
CONFIG_DM=y CONFIG_DM=y
# CONFIG_DM_GPIO is not set CONFIG_BOUNCE_BUFFER=y
# CONFIG_IMX_RGPIO2P is not set CONFIG_IMX_RGPIO2P=y
# CONFIG_MXC_GPIO is not set # CONFIG_MXC_GPIO is not set
CONFIG_DM_MMC=y CONFIG_SUPPORT_EMMC_BOOT=y
# CONFIG_MMC_VERBOSE is not set CONFIG_FSL_USDHC=y
CONFIG_FSL_ESDHC=y CONFIG_MTD=y
CONFIG_PINCTRL=y CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX7ULP=y CONFIG_PINCTRL_IMX7ULP=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_SERIAL=y CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y CONFIG_FSL_LPUART=y
# CONFIG_EFI_LOADER is not set

29
drivers/mmc/fsl_esdhc_imx.c
View File

@ -653,7 +653,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4); clk = (pre_div << 8) | (div << 4);
#ifdef CONFIG_FSL_USDHC #ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
if (ret)
pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
#else #else
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
#endif #endif
@ -665,7 +668,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n"); pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
#ifdef CONFIG_FSL_USDHC #ifdef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN); esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#else #else
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif #endif
@ -720,8 +723,14 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev); struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
struct fsl_esdhc *regs = priv->esdhc_regs; struct fsl_esdhc *regs = priv->esdhc_regs;
u32 val; u32 val;
u32 tmp;
int ret;
if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) { if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
if (ret)
pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET); esdhc_write32(&regs->strobe_dllctrl, ESDHC_STROBE_DLL_CTRL_RESET);
/* /*
@ -739,6 +748,7 @@ static void esdhc_set_strobe_dll(struct mmc *mmc)
pr_warn("HS400 strobe DLL status REF not lock!\n"); pr_warn("HS400 strobe DLL status REF not lock!\n");
if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK)) if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
pr_warn("HS400 strobe DLL status SLV not lock!\n"); pr_warn("HS400 strobe DLL status SLV not lock!\n");
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
} }
} }
@ -970,14 +980,18 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#ifdef MMC_SUPPORTS_TUNING #ifdef MMC_SUPPORTS_TUNING
if (mmc->clk_disable) { if (mmc->clk_disable) {
#ifdef CONFIG_FSL_USDHC #ifdef CONFIG_FSL_USDHC
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN); u32 tmp;
esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100);
if (ret)
pr_warn("fsl_esdhc_imx: Internal clock never gate off.\n");
#else #else
esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN); esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
#endif #endif
} else { } else {
#ifdef CONFIG_FSL_USDHC #ifdef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
VENDORSPEC_CKEN);
#else #else
esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif #endif
@ -1053,7 +1067,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
#ifndef CONFIG_FSL_USDHC #ifndef CONFIG_FSL_USDHC
esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
#else #else
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN); esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
#endif #endif
/* Set the initial clock speed */ /* Set the initial clock speed */
@ -1191,8 +1205,7 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
esdhc_write32(&regs->autoc12err, 0); esdhc_write32(&regs->autoc12err, 0);
esdhc_write32(&regs->clktunectrlstatus, 0); esdhc_write32(&regs->clktunectrlstatus, 0);
#else #else
esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | esdhc_setbits32(&regs->vendorspec, VENDORSPEC_FRC_SDCLK_ON);
VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
#endif #endif
if (priv->vs18_enable) if (priv->vs18_enable)

44
include/configs/pwh1.h
View File

@ -5,43 +5,18 @@
* Configuration settings for the Freescale i.MX7ULP EVK board. * Configuration settings for the Freescale i.MX7ULP EVK board.
*/ */
#ifndef __MX7ULP_EVK_CONFIG_H #ifndef __MX7ULP_PWH1_CONFIG_H
#define __MX7ULP_EVK_CONFIG_H #define __MX7ULP_PWH1_CONFIG_H
#include <linux/sizes.h> #include <linux/sizes.h>
#include <asm/arch/imx-regs.h> #include <asm/arch/imx-regs.h>
/*Uncomment it to use secure boot*/
/*#define CONFIG_SECURE_BOOT*/
#ifdef CONFIG_SECURE_BOOT
#ifndef CONFIG_CSF_SIZE
#define CONFIG_CSF_SIZE 0x4000
#endif
#endif
#define CONFIG_BOARD_POSTCLK_INIT #define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_SYS_BOOTM_LEN 0x1000000 #define CONFIG_SYS_BOOTM_LEN 0x1000000
#define SRC_BASE_ADDR CMC1_RBASE
#define IRAM_BASE_ADDR OCRAM_0_BASE
#define IOMUXC_BASE_ADDR IOMUXC1_RBASE
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_FSL_USDHC
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
#define CONFIG_SYS_FSL_USDHC_NUM 1
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 #define CONFIG_SYS_MMC_IMG_LOAD_PART 1
#define CONFIG_ENV_OFFSET (12 * SZ_64K)
#define CONFIG_ENV_SIZE SZ_8K
/* Using ULP WDOG for reset */ /* Using ULP WDOG for reset */
#define WDOG_BASE_ADDR WDG1_RBASE #define WDOG_BASE_ADDR WDG1_RBASE
@ -55,15 +30,9 @@
/* Size of malloc() pool */ /* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) #define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
/* UART */ /* UART */
#define LPUART_BASE LPUART4_RBASE #define LPUART_BASE LPUART4_RBASE
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_SYS_CACHELINE_SIZE 64
/* Miscellaneous configurable options */ /* Miscellaneous configurable options */
@ -75,14 +44,11 @@
/* Physical Memory Map */ /* Physical Memory Map */
#define PHYS_SDRAM 0x60000000 #define PHYS_SDRAM 0x60000000
#define PHYS_SDRAM_SIZE 0x8000000 #define PHYS_SDRAM_SIZE SZ_128M
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_LOADADDR 0x60800000 #define CONFIG_LOADADDR 0x60800000
#define CONFIG_SYS_MEMTEST_END 0x66000000
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"script=boot.scr\0" \ "script=boot.scr\0" \
"image=zImage\0" \ "image=zImage\0" \
@ -169,8 +135,4 @@
#define CONFIG_SYS_INIT_SP_ADDR \ #define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#ifndef CONFIG_SYS_DCACHE_OFF
#define CONFIG_CMD_CACHE
#endif
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */

2
include/fsl_esdhc_imx.h
View File

@ -39,6 +39,7 @@
#define VENDORSPEC_HCKEN 0x00001000 #define VENDORSPEC_HCKEN 0x00001000
#define VENDORSPEC_IPGEN 0x00000800 #define VENDORSPEC_IPGEN 0x00000800
#define VENDORSPEC_INIT 0x20007809 #define VENDORSPEC_INIT 0x20007809
#define VENDORSPEC_FRC_SDCLK_ON 0x00000100
#define IRQSTAT 0x0002e030 #define IRQSTAT 0x0002e030
#define IRQSTAT_DMAE (0x10000000) #define IRQSTAT_DMAE (0x10000000)
@ -96,6 +97,7 @@
#define PRSSTAT_CINS (0x00010000) #define PRSSTAT_CINS (0x00010000)
#define PRSSTAT_BREN (0x00000800) #define PRSSTAT_BREN (0x00000800)
#define PRSSTAT_BWEN (0x00000400) #define PRSSTAT_BWEN (0x00000400)
#define PRSSTAT_SDOFF (0x00000080)
#define PRSSTAT_SDSTB (0X00000008) #define PRSSTAT_SDSTB (0X00000008)
#define PRSSTAT_DLA (0x00000004) #define PRSSTAT_DLA (0x00000004)
#define PRSSTAT_CICHB (0x00000002) #define PRSSTAT_CICHB (0x00000002)