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board: ti: am335x: Add platdata for cpsw in SPL
The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL is enabled. Use static platdata instead to save space. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
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8a616cc292
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@ -875,6 +875,55 @@ int board_late_init(void)
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}
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}
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#endif
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#endif
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/* CPSW platdata */
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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struct cpsw_slave_data slave_data[] = {
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{
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.slave_reg_ofs = CPSW_SLAVE0_OFFSET,
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.sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
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.phy_addr = 0,
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},
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{
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.slave_reg_ofs = CPSW_SLAVE1_OFFSET,
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.sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
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.phy_addr = 1,
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},
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};
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struct cpsw_platform_data am335_eth_data = {
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.cpsw_base = CPSW_BASE,
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.version = CPSW_CTRL_VERSION_2,
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.bd_ram_ofs = CPSW_BD_OFFSET,
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.ale_reg_ofs = CPSW_ALE_OFFSET,
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.cpdma_reg_ofs = CPSW_CPDMA_OFFSET,
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.mdio_div = CPSW_MDIO_DIV,
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.host_port_reg_ofs = CPSW_HOST_PORT_OFFSET,
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.channels = 8,
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.slaves = 2,
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.slave_data = slave_data,
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.ale_entries = 1024,
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.bd_ram_ofs = 0x2000,
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.mac_control = 0x20,
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.active_slave = 0,
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.mdio_base = 0x4a101000,
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.gmii_sel = 0x44e10650,
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.phy_sel_compat = "ti,am3352-cpsw-phy-sel",
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.syscon_addr = 0x44e10630,
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.macid_sel_compat = "cpsw,am33xx",
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};
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struct eth_pdata cpsw_pdata = {
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.iobase = 0x4a100000,
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.phy_interface = 0,
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.priv_pdata = &am335_eth_data,
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};
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U_BOOT_DEVICE(am335x_eth) = {
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.name = "eth_cpsw",
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.platdata = &cpsw_pdata,
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};
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#endif
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#ifndef CONFIG_DM_ETH
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#ifndef CONFIG_DM_ETH
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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@ -33,24 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define GIGABITEN BIT(7)
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#define GIGABITEN BIT(7)
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#define FULLDUPLEXEN BIT(0)
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#define FULLDUPLEXEN BIT(0)
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#define MIIEN BIT(15)
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#define MIIEN BIT(15)
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/* reg offset */
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#define CPSW_HOST_PORT_OFFSET 0x108
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#define CPSW_SLAVE0_OFFSET 0x208
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#define CPSW_SLAVE1_OFFSET 0x308
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#define CPSW_SLAVE_SIZE 0x100
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#define CPSW_CPDMA_OFFSET 0x800
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#define CPSW_HW_STATS 0x900
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#define CPSW_STATERAM_OFFSET 0xa00
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#define CPSW_CPTS_OFFSET 0xc00
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#define CPSW_ALE_OFFSET 0xd00
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#define CPSW_SLIVER0_OFFSET 0xd80
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#define CPSW_SLIVER1_OFFSET 0xdc0
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#define CPSW_BD_OFFSET 0x2000
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#define CPSW_MDIO_DIV 0xff
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#define AM335X_GMII_SEL_OFFSET 0x630
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/* DMA Registers */
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/* DMA Registers */
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#define CPDMA_TXCONTROL 0x004
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#define CPDMA_TXCONTROL 0x004
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#define CPDMA_RXCONTROL 0x014
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#define CPDMA_RXCONTROL 0x014
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@ -16,6 +16,23 @@
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#ifndef _CPSW_H_
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#ifndef _CPSW_H_
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#define _CPSW_H_
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#define _CPSW_H_
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/* reg offset */
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#define CPSW_HOST_PORT_OFFSET 0x108
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#define CPSW_SLAVE0_OFFSET 0x208
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#define CPSW_SLAVE1_OFFSET 0x308
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#define CPSW_SLAVE_SIZE 0x100
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#define CPSW_CPDMA_OFFSET 0x800
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#define CPSW_HW_STATS 0x900
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#define CPSW_STATERAM_OFFSET 0xa00
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#define CPSW_CPTS_OFFSET 0xc00
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#define CPSW_ALE_OFFSET 0xd00
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#define CPSW_SLIVER0_OFFSET 0xd80
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#define CPSW_SLIVER1_OFFSET 0xdc0
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#define CPSW_BD_OFFSET 0x2000
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#define CPSW_MDIO_DIV 0xff
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#define AM335X_GMII_SEL_OFFSET 0x630
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struct cpsw_slave_data {
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struct cpsw_slave_data {
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u32 slave_reg_ofs;
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u32 slave_reg_ofs;
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u32 sliver_reg_ofs;
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u32 sliver_reg_ofs;
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