diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index d67f94ad47..b811fb088b 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -875,6 +875,55 @@ int board_late_init(void)
 }
 #endif
 
+/* CPSW platdata */
+#if !CONFIG_IS_ENABLED(OF_CONTROL)
+struct cpsw_slave_data slave_data[] = {
+	{
+		.slave_reg_ofs  = CPSW_SLAVE0_OFFSET,
+		.sliver_reg_ofs = CPSW_SLIVER0_OFFSET,
+		.phy_addr       = 0,
+	},
+	{
+		.slave_reg_ofs  = CPSW_SLAVE1_OFFSET,
+		.sliver_reg_ofs = CPSW_SLIVER1_OFFSET,
+		.phy_addr       = 1,
+	},
+};
+
+struct cpsw_platform_data am335_eth_data = {
+	.cpsw_base		= CPSW_BASE,
+	.version		= CPSW_CTRL_VERSION_2,
+	.bd_ram_ofs		= CPSW_BD_OFFSET,
+	.ale_reg_ofs		= CPSW_ALE_OFFSET,
+	.cpdma_reg_ofs		= CPSW_CPDMA_OFFSET,
+	.mdio_div		= CPSW_MDIO_DIV,
+	.host_port_reg_ofs	= CPSW_HOST_PORT_OFFSET,
+	.channels		= 8,
+	.slaves			= 2,
+	.slave_data		= slave_data,
+	.ale_entries		= 1024,
+	.bd_ram_ofs		= 0x2000,
+	.mac_control		= 0x20,
+	.active_slave		= 0,
+	.mdio_base		= 0x4a101000,
+	.gmii_sel		= 0x44e10650,
+	.phy_sel_compat		= "ti,am3352-cpsw-phy-sel",
+	.syscon_addr		= 0x44e10630,
+	.macid_sel_compat	= "cpsw,am33xx",
+};
+
+struct eth_pdata cpsw_pdata = {
+	.iobase = 0x4a100000,
+	.phy_interface = 0,
+	.priv_pdata = &am335_eth_data,
+};
+
+U_BOOT_DEVICE(am335x_eth) = {
+	.name = "eth_cpsw",
+	.platdata = &cpsw_pdata,
+};
+#endif
+
 #ifndef CONFIG_DM_ETH
 
 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
diff --git a/drivers/net/ti/cpsw.c b/drivers/net/ti/cpsw.c
index e16c270985..20ddb44dd8 100644
--- a/drivers/net/ti/cpsw.c
+++ b/drivers/net/ti/cpsw.c
@@ -33,24 +33,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GIGABITEN		BIT(7)
 #define FULLDUPLEXEN		BIT(0)
 #define MIIEN			BIT(15)
-
-/* reg offset */
-#define CPSW_HOST_PORT_OFFSET	0x108
-#define CPSW_SLAVE0_OFFSET	0x208
-#define CPSW_SLAVE1_OFFSET	0x308
-#define CPSW_SLAVE_SIZE		0x100
-#define CPSW_CPDMA_OFFSET	0x800
-#define CPSW_HW_STATS		0x900
-#define CPSW_STATERAM_OFFSET	0xa00
-#define CPSW_CPTS_OFFSET	0xc00
-#define CPSW_ALE_OFFSET		0xd00
-#define CPSW_SLIVER0_OFFSET	0xd80
-#define CPSW_SLIVER1_OFFSET	0xdc0
-#define CPSW_BD_OFFSET		0x2000
-#define CPSW_MDIO_DIV		0xff
-
-#define AM335X_GMII_SEL_OFFSET	0x630
-
 /* DMA Registers */
 #define CPDMA_TXCONTROL		0x004
 #define CPDMA_RXCONTROL		0x014
diff --git a/include/cpsw.h b/include/cpsw.h
index 0023151bc0..96ff254f98 100644
--- a/include/cpsw.h
+++ b/include/cpsw.h
@@ -16,6 +16,23 @@
 #ifndef _CPSW_H_
 #define _CPSW_H_
 
+/* reg offset */
+#define CPSW_HOST_PORT_OFFSET	0x108
+#define CPSW_SLAVE0_OFFSET	0x208
+#define CPSW_SLAVE1_OFFSET	0x308
+#define CPSW_SLAVE_SIZE		0x100
+#define CPSW_CPDMA_OFFSET	0x800
+#define CPSW_HW_STATS		0x900
+#define CPSW_STATERAM_OFFSET	0xa00
+#define CPSW_CPTS_OFFSET	0xc00
+#define CPSW_ALE_OFFSET		0xd00
+#define CPSW_SLIVER0_OFFSET	0xd80
+#define CPSW_SLIVER1_OFFSET	0xdc0
+#define CPSW_BD_OFFSET		0x2000
+#define CPSW_MDIO_DIV		0xff
+
+#define AM335X_GMII_SEL_OFFSET	0x630
+
 struct cpsw_slave_data {
 	u32		slave_reg_ofs;
 	u32		sliver_reg_ofs;