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https://github.com/brain-hackers/u-boot-brain
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237 lines
5.5 KiB
C
237 lines
5.5 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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* Author: Ken Ma<make@marvell.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <wait_bit.h>
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#define MVMDIO_SMI_DATA_SHIFT 0
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#define MVMDIO_SMI_PHY_ADDR_SHIFT 16
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#define MVMDIO_SMI_PHY_REG_SHIFT 21
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#define MVMDIO_SMI_READ_OPERATION BIT(26)
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#define MVMDIO_SMI_WRITE_OPERATION 0
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#define MVMDIO_SMI_READ_VALID BIT(27)
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#define MVMDIO_SMI_BUSY BIT(28)
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#define MVMDIO_XSMI_MGNT_REG 0x0
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#define MVMDIO_XSMI_PHYADDR_SHIFT 16
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#define MVMDIO_XSMI_DEVADDR_SHIFT 21
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#define MVMDIO_XSMI_WRITE_OPERATION (0x5 << 26)
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#define MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
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#define MVMDIO_XSMI_READ_VALID BIT(29)
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#define MVMDIO_XSMI_BUSY BIT(30)
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#define MVMDIO_XSMI_ADDR_REG 0x8
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enum mvmdio_bus_type {
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BUS_TYPE_SMI,
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BUS_TYPE_XSMI
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};
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struct mvmdio_priv {
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void *mdio_base;
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enum mvmdio_bus_type type;
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};
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static int mvmdio_smi_read(struct udevice *dev, int addr,
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int devad, int reg)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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u32 val;
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int ret;
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if (devad != MDIO_DEVAD_NONE)
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return -EOPNOTSUPP;
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ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
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false, CONFIG_SYS_HZ, false);
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if (ret < 0)
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return ret;
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writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(reg << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_READ_OPERATION),
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priv->mdio_base);
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ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
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false, CONFIG_SYS_HZ, false);
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if (ret < 0)
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return ret;
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val = readl(priv->mdio_base);
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if (!(val & MVMDIO_SMI_READ_VALID)) {
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pr_err("SMI bus read not valid\n");
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return -ENODEV;
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}
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return val & GENMASK(15, 0);
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}
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static int mvmdio_smi_write(struct udevice *dev, int addr, int devad,
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int reg, u16 value)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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int ret;
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if (devad != MDIO_DEVAD_NONE)
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return -EOPNOTSUPP;
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ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
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false, CONFIG_SYS_HZ, false);
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if (ret < 0)
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return ret;
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writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
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(reg << MVMDIO_SMI_PHY_REG_SHIFT) |
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MVMDIO_SMI_WRITE_OPERATION |
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(value << MVMDIO_SMI_DATA_SHIFT)),
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priv->mdio_base);
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return 0;
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}
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static int mvmdio_xsmi_read(struct udevice *dev, int addr,
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int devad, int reg)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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int ret;
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if (devad == MDIO_DEVAD_NONE)
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return -EOPNOTSUPP;
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ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
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false, CONFIG_SYS_HZ, false);
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if (ret < 0)
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return ret;
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writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
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writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
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(devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
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MVMDIO_XSMI_READ_OPERATION),
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priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
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ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
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false, CONFIG_SYS_HZ, false);
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if (ret < 0)
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return ret;
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if (!(readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) &
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MVMDIO_XSMI_READ_VALID)) {
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pr_err("XSMI bus read not valid\n");
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return -ENODEV;
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}
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return readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
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}
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static int mvmdio_xsmi_write(struct udevice *dev, int addr, int devad,
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int reg, u16 value)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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int ret;
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if (devad == MDIO_DEVAD_NONE)
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return -EOPNOTSUPP;
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ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
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false, CONFIG_SYS_HZ, false);
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if (ret < 0)
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return ret;
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writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
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writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
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(devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
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MVMDIO_XSMI_WRITE_OPERATION | value),
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priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
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return 0;
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}
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static int mvmdio_read(struct udevice *dev, int addr, int devad, int reg)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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int err = -ENOTSUPP;
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switch (priv->type) {
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case BUS_TYPE_SMI:
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err = mvmdio_smi_read(dev, addr, devad, reg);
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break;
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case BUS_TYPE_XSMI:
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err = mvmdio_xsmi_read(dev, addr, devad, reg);
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break;
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}
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return err;
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}
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static int mvmdio_write(struct udevice *dev, int addr, int devad, int reg,
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u16 value)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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int err = -ENOTSUPP;
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switch (priv->type) {
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case BUS_TYPE_SMI:
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err = mvmdio_smi_write(dev, addr, devad, reg, value);
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break;
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case BUS_TYPE_XSMI:
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err = mvmdio_xsmi_write(dev, addr, devad, reg, value);
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break;
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}
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return err;
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}
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/*
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* Name the device, we use the device tree node name.
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* This can be overwritten by MDIO class code if device-name property is
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* present.
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*/
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static int mvmdio_bind(struct udevice *dev)
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{
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if (ofnode_valid(dev->node))
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device_set_name(dev, ofnode_get_name(dev->node));
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return 0;
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}
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/* Get device base address and type, either C22 SMII or C45 XSMI */
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static int mvmdio_probe(struct udevice *dev)
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{
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struct mvmdio_priv *priv = dev_get_priv(dev);
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priv->mdio_base = (void *)dev_read_addr(dev);
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priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
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return 0;
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}
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static const struct mdio_ops mvmdio_ops = {
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.read = mvmdio_read,
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.write = mvmdio_write,
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};
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static const struct udevice_id mvmdio_ids[] = {
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{ .compatible = "marvell,orion-mdio", .data = BUS_TYPE_SMI },
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{ .compatible = "marvell,xmdio", .data = BUS_TYPE_XSMI },
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{ }
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};
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U_BOOT_DRIVER(mvmdio) = {
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.name = "mvmdio",
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.id = UCLASS_MDIO,
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.of_match = mvmdio_ids,
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.bind = mvmdio_bind,
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.probe = mvmdio_probe,
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.ops = &mvmdio_ops,
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.priv_auto_alloc_size = sizeof(struct mvmdio_priv),
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};
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