drivers: net: add marvell MDIO driver

This patch adds a separate driver for the MDIO interface of the
Marvell Ethernet controllers based on driver model. There are two
reasons to have a separate driver rather than including it inside
the MAC driver itself:
  *) The MDIO interface is shared by all Ethernet ports, so a driver
     must guarantee non-concurrent accesses to this MDIO interface. The
     most logical way is to have a separate driver that handles this
     single MDIO interface, used by all Ethernet ports.
  *) The MDIO interface is the same between the existing mv643xx_eth
     driver and the new mvneta/mvpp2 driver. Even though it is for now
     only used by the mvneta/mvpp2 driver, it will in the future be
     used by the mv643xx_eth driver as well.

This driver supports SMI IEEE for 802.3 Clause 22 and XSMI for IEEE
802.3 Clause 45.

This patch also adds device tree binding for marvell MDIO driver.

Signed-off-by: Ken Ma <make@marvell.com>
Signed-off-by: Alex Marginean <alexm.osslist@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

doc/device-tree-bindings/net/marvell-mdio.txt

@@ -0,0 +1,15 @@
+* Marvell MDIO Ethernet Controller interface
+
+The Ethernet controllers of the Marvel Armada 3700 and Armada 7k/8k
+have an identical unit that provides an interface with the MDIO bus.
+This driver handles this MDIO interface.
+
+Mandatory properties:
+SoC specific:
+	- #address-cells: Must be <1>.
+	- #size-cells: Must be <0>.
+	- compatible: Should be "marvell,orion-mdio" (for SMI)
+				"marvell,xmdio"	     (for XSMI)
+	- reg: Base address and size SMI/XMSI bus.
+
+Please refer to "mdio.txt" for generic MDIO bus bindings.

drivers/net/Kconfig

@@ -604,4 +604,14 @@ config MDIO_MUX_I2CREG
 	  an I2C chip.  The board it was developed for uses a mux controlled by
 	  on-board FPGA which in turn is accessed as a chip over I2C.
 
+config MVMDIO
+	bool "Marvell MDIO interface support"
+	depends on DM_MDIO
+	help
+	  This driver supports the MDIO interface found in the network
+	  interface units of the Marvell EBU SoCs (Kirkwood, Orion5x,
+	  Dove, Armada 370, Armada XP, Armada 37xx and Armada7K/8K/8KP).
+
+	  This driver is used by the MVPP2 and MVNETA drivers.
+
 endif # NETDEVICES

drivers/net/Makefile

@@ -42,6 +42,7 @@ obj-$(CONFIG_MDIO_MUX_SANDBOX) += mdio_mux_sandbox.o
 obj-$(CONFIG_MPC8XX_FEC) += mpc8xx_fec.o
 obj-$(CONFIG_MT7628_ETH) += mt7628-eth.o
 obj-$(CONFIG_MVGBE) += mvgbe.o
+obj-$(CONFIG_MVMDIO) += mvmdio.o
 obj-$(CONFIG_MVNETA) += mvneta.o
 obj-$(CONFIG_MVPP2) += mvpp2.o
 obj-$(CONFIG_NATSEMI) += natsemi.o

drivers/net/mvmdio.c

@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Marvell International Ltd.
+ * Author: Ken Ma<make@marvell.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+#include <miiphy.h>
+#include <phy.h>
+#include <asm/io.h>
+#include <wait_bit.h>
+
+#define MVMDIO_SMI_DATA_SHIFT		0
+#define MVMDIO_SMI_PHY_ADDR_SHIFT	16
+#define MVMDIO_SMI_PHY_REG_SHIFT	21
+#define MVMDIO_SMI_READ_OPERATION	BIT(26)
+#define MVMDIO_SMI_WRITE_OPERATION	0
+#define MVMDIO_SMI_READ_VALID		BIT(27)
+#define MVMDIO_SMI_BUSY			BIT(28)
+
+#define MVMDIO_XSMI_MGNT_REG		0x0
+#define MVMDIO_XSMI_PHYADDR_SHIFT	16
+#define MVMDIO_XSMI_DEVADDR_SHIFT	21
+#define MVMDIO_XSMI_WRITE_OPERATION	(0x5 << 26)
+#define MVMDIO_XSMI_READ_OPERATION	(0x7 << 26)
+#define MVMDIO_XSMI_READ_VALID		BIT(29)
+#define MVMDIO_XSMI_BUSY		BIT(30)
+#define MVMDIO_XSMI_ADDR_REG		0x8
+
+enum mvmdio_bus_type {
+	BUS_TYPE_SMI,
+	BUS_TYPE_XSMI
+};
+
+struct mvmdio_priv {
+	void *mdio_base;
+	enum mvmdio_bus_type type;
+};
+
+static int mvmdio_smi_read(struct udevice *dev, int addr,
+			   int devad, int reg)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+	u32 val;
+	int ret;
+
+	if (devad != MDIO_DEVAD_NONE)
+		return -EOPNOTSUPP;
+
+	ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+				false, CONFIG_SYS_HZ, false);
+	if (ret < 0)
+		return ret;
+
+	writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
+		(reg << MVMDIO_SMI_PHY_REG_SHIFT)  |
+		MVMDIO_SMI_READ_OPERATION),
+	       priv->mdio_base);
+
+	ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+				false, CONFIG_SYS_HZ, false);
+	if (ret < 0)
+		return ret;
+
+	val = readl(priv->mdio_base);
+	if (!(val & MVMDIO_SMI_READ_VALID)) {
+		pr_err("SMI bus read not valid\n");
+		return -ENODEV;
+	}
+
+	return val & GENMASK(15, 0);
+}
+
+static int mvmdio_smi_write(struct udevice *dev, int addr, int devad,
+			    int reg, u16 value)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (devad != MDIO_DEVAD_NONE)
+		return -EOPNOTSUPP;
+
+	ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_SMI_BUSY,
+				false, CONFIG_SYS_HZ, false);
+	if (ret < 0)
+		return ret;
+
+	writel(((addr << MVMDIO_SMI_PHY_ADDR_SHIFT) |
+		(reg << MVMDIO_SMI_PHY_REG_SHIFT)  |
+		MVMDIO_SMI_WRITE_OPERATION            |
+		(value << MVMDIO_SMI_DATA_SHIFT)),
+	       priv->mdio_base);
+
+	return 0;
+}
+
+static int mvmdio_xsmi_read(struct udevice *dev, int addr,
+			    int devad, int reg)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (devad == MDIO_DEVAD_NONE)
+		return -EOPNOTSUPP;
+
+	ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+				false, CONFIG_SYS_HZ, false);
+	if (ret < 0)
+		return ret;
+
+	writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
+	writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
+		(devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
+		MVMDIO_XSMI_READ_OPERATION),
+	       priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
+
+	ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+				false, CONFIG_SYS_HZ, false);
+	if (ret < 0)
+		return ret;
+
+	if (!(readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) &
+	      MVMDIO_XSMI_READ_VALID)) {
+		pr_err("XSMI bus read not valid\n");
+		return -ENODEV;
+	}
+
+	return readl(priv->mdio_base + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
+}
+
+static int mvmdio_xsmi_write(struct udevice *dev, int addr, int devad,
+			     int reg, u16 value)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+	int ret;
+
+	if (devad == MDIO_DEVAD_NONE)
+		return -EOPNOTSUPP;
+
+	ret = wait_for_bit_le32(priv->mdio_base, MVMDIO_XSMI_BUSY,
+				false, CONFIG_SYS_HZ, false);
+	if (ret < 0)
+		return ret;
+
+	writel(reg & GENMASK(15, 0), priv->mdio_base + MVMDIO_XSMI_ADDR_REG);
+	writel(((addr << MVMDIO_XSMI_PHYADDR_SHIFT) |
+		(devad << MVMDIO_XSMI_DEVADDR_SHIFT) |
+		MVMDIO_XSMI_WRITE_OPERATION | value),
+	       priv->mdio_base + MVMDIO_XSMI_MGNT_REG);
+
+	return 0;
+}
+
+static int mvmdio_read(struct udevice *dev, int addr, int devad, int reg)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+	int err = -ENOTSUPP;
+
+	switch (priv->type) {
+	case BUS_TYPE_SMI:
+		err = mvmdio_smi_read(dev, addr, devad, reg);
+		break;
+	case BUS_TYPE_XSMI:
+		err = mvmdio_xsmi_read(dev, addr, devad, reg);
+		break;
+	}
+
+	return err;
+}
+
+static int mvmdio_write(struct udevice *dev, int addr, int devad, int reg,
+			u16 value)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+	int err = -ENOTSUPP;
+
+	switch (priv->type) {
+	case BUS_TYPE_SMI:
+		err = mvmdio_smi_write(dev, addr, devad, reg, value);
+		break;
+	case BUS_TYPE_XSMI:
+		err = mvmdio_xsmi_write(dev, addr, devad, reg, value);
+		break;
+	}
+
+	return err;
+}
+
+/*
+ * Name the device, we use the device tree node name.
+ * This can be overwritten by MDIO class code if device-name property is
+ * present.
+ */
+static int mvmdio_bind(struct udevice *dev)
+{
+	if (ofnode_valid(dev->node))
+		device_set_name(dev, ofnode_get_name(dev->node));
+
+	return 0;
+}
+
+/* Get device base address and type, either C22 SMII or C45 XSMI */
+static int mvmdio_probe(struct udevice *dev)
+{
+	struct mvmdio_priv *priv = dev_get_priv(dev);
+
+	priv->mdio_base = (void *)dev_read_addr(dev);
+	priv->type = (enum mvmdio_bus_type)dev_get_driver_data(dev);
+
+	return 0;
+}
+
+static const struct mdio_ops mvmdio_ops = {
+	.read = mvmdio_read,
+	.write = mvmdio_write,
+};
+
+static const struct udevice_id mvmdio_ids[] = {
+	{ .compatible = "marvell,orion-mdio", .data = BUS_TYPE_SMI },
+	{ .compatible = "marvell,xmdio", .data = BUS_TYPE_XSMI },
+	{ }
+};
+
+U_BOOT_DRIVER(mvmdio) = {
+	.name			= "mvmdio",
+	.id			= UCLASS_MDIO,
+	.of_match		= mvmdio_ids,
+	.bind			= mvmdio_bind,
+	.probe			= mvmdio_probe,
+	.ops			= &mvmdio_ops,
+	.priv_auto_alloc_size	= sizeof(struct mvmdio_priv),
+};
+