2018-05-07 06:58:06 +09:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2008-01-16 15:38:05 +09:00
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Kevin Lam <kevin.lam@freescale.com>
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* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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2009-06-10 05:25:30 +09:00
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#define CONFIG_HWCONFIG
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2008-02-09 04:15:55 +09:00
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/*
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* On-board devices
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*/
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#define CONFIG_VSC7385_ENET
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2008-10-16 22:01:15 +09:00
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/* System performance - define the value i.e. CONFIG_SYS_XXX
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2008-01-16 15:38:05 +09:00
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*/
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/* Arbiter Configuration Register */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
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2008-01-16 15:38:05 +09:00
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/* System Priority Control Regsiter */
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
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2008-01-16 15:38:05 +09:00
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/* System Clock Configuration Register */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
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2008-01-16 15:38:05 +09:00
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/*
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* System IO Config
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_SICRH 0x08200000
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#define CONFIG_SYS_SICRL 0x00000000
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2008-01-16 15:38:05 +09:00
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/*
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* Output Buffer Impedance
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_OBIR 0x30100000
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2008-01-16 15:38:05 +09:00
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/*
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* IMMR new address
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_IMMR 0xE0000000
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2008-01-16 15:38:05 +09:00
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2008-02-09 04:15:55 +09:00
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/*
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* Device configurations
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*/
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/* Vitesse 7385 */
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#ifdef CONFIG_VSC7385_ENET
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#define CONFIG_TSEC2
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/* The flash address and size of the VSC7385 firmware image */
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#define CONFIG_VSC7385_IMAGE 0xFE7FE000
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#define CONFIG_VSC7385_IMAGE_SIZE 8192
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#endif
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2008-01-16 15:38:05 +09:00
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/*
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* DDR Setup
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
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2008-01-16 15:38:05 +09:00
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#undef CONFIG_DDR_ECC /* support DDR ECC function */
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#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
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/*
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* Manually set up DDR parameters
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_SIZE 256 /* MB */
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2011-10-12 13:57:29 +09:00
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_WR_ONLY_CURRENT \
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| CSCONFIG_ROW_BIT_13 \
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| CSCONFIG_COL_BIT_10)
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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2008-01-16 15:38:05 +09:00
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00260802 */ /* DDR400 */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
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2008-01-16 15:38:05 +09:00
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| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (7 << TIMING_CFG1_CASLAT_SHIFT) \
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| (13 << TIMING_CFG1_REFREC_SHIFT) \
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| (3 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x3937d322 */
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2011-10-12 13:57:29 +09:00
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#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (5 << TIMING_CFG2_CPO_SHIFT) \
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| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x02984cc8 */
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2008-01-16 15:38:05 +09:00
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2009-08-22 06:33:15 +09:00
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#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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2008-01-16 15:38:05 +09:00
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/* 0x06090100 */
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#if defined(CONFIG_DDR_2T_TIMING)
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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2011-10-12 13:57:29 +09:00
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| SDRAM_CFG_SDRAM_TYPE_DDR2 \
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| SDRAM_CFG_32_BE \
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| SDRAM_CFG_2T_EN)
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/* 0x43088000 */
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2008-01-16 15:38:05 +09:00
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#else
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
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2011-10-12 13:57:29 +09:00
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| SDRAM_CFG_SDRAM_TYPE_DDR2)
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2011-10-12 13:57:19 +09:00
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/* 0x43000000 */
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2008-01-16 15:38:05 +09:00
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#endif
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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2009-08-22 06:33:15 +09:00
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#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
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2011-10-12 13:57:19 +09:00
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| (0x0442 << SDRAM_MODE_SD_SHIFT))
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/* 0x04400442 */ /* DDR400 */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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2008-01-16 15:38:05 +09:00
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/*
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* Memory test
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*/
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2008-10-16 22:01:15 +09:00
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x0ef70010
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2008-01-16 15:38:05 +09:00
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/*
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* The reserved memory
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*/
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2010-10-08 04:51:12 +09:00
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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2008-01-16 15:38:05 +09:00
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#else
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2008-10-16 22:01:15 +09:00
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#undef CONFIG_SYS_RAMBOOT
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2008-01-16 15:38:05 +09:00
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#endif
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2016-07-08 12:25:14 +09:00
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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2008-01-16 15:38:05 +09:00
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/*
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* Initial RAM Base Address Setup
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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2010-10-26 20:32:32 +09:00
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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2008-01-16 15:38:05 +09:00
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/*
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* Local Bus Configuration & Clock Setup
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*/
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2009-09-26 08:19:44 +09:00
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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2010-06-18 01:37:18 +09:00
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#define CONFIG_FSL_ELBC 1
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2008-01-16 15:38:05 +09:00
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/*
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* FLASH on the Local Bus
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
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2008-01-16 15:38:05 +09:00
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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2008-01-16 15:38:05 +09:00
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2008-03-24 23:40:23 +09:00
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/*
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* NAND Flash on the Local Bus
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*/
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2011-10-12 13:57:30 +09:00
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#define CONFIG_SYS_NAND_BASE 0xE0600000
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2019-01-21 17:18:01 +09:00
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2008-02-09 04:15:55 +09:00
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/* Vitesse 7385 */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_VSC7385_BASE 0xF0000000
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2008-01-16 15:38:05 +09:00
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2008-02-09 04:15:55 +09:00
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#ifdef CONFIG_VSC7385_ENET
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2019-01-21 17:18:01 +09:00
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2008-02-09 04:15:55 +09:00
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#endif
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2008-01-16 15:38:05 +09:00
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/*
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* Serial Port
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*/
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_BAUDRATE_TABLE \
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2011-10-12 13:57:19 +09:00
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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2008-01-16 15:38:05 +09:00
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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2008-01-16 15:38:05 +09:00
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2008-03-24 23:40:43 +09:00
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/* SERDES */
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_FSL_SERDES2 0xe3100
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2008-01-16 15:38:05 +09:00
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/* I2C */
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2012-10-24 20:48:22 +09:00
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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2008-01-16 15:38:05 +09:00
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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2008-01-16 15:38:05 +09:00
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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2011-10-12 13:57:19 +09:00
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#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
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#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
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2008-10-16 22:01:15 +09:00
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#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
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#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
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#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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2008-01-16 15:38:05 +09:00
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2009-02-20 00:20:52 +09:00
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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|
|
|
|
|
#define CONFIG_SYS_PCIE2_BASE 0xC0000000
|
|
|
|
#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
|
|
|
|
#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
|
|
|
|
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
|
|
|
|
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
|
|
|
|
|
2008-01-16 15:38:05 +09:00
|
|
|
#ifdef CONFIG_PCI
|
2013-05-30 16:06:12 +09:00
|
|
|
#define CONFIG_PCI_INDIRECT_BRIDGE
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
|
2008-01-16 15:38:05 +09:00
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TSEC
|
|
|
|
*/
|
2008-02-09 04:15:55 +09:00
|
|
|
#ifdef CONFIG_TSEC_ENET
|
2008-01-16 15:38:05 +09:00
|
|
|
|
2008-02-09 04:15:55 +09:00
|
|
|
#define CONFIG_GMII /* MII PHY management */
|
|
|
|
|
|
|
|
#define CONFIG_TSEC1
|
|
|
|
|
|
|
|
#ifdef CONFIG_TSEC1
|
|
|
|
#define CONFIG_HAS_ETH0
|
2008-01-16 15:38:05 +09:00
|
|
|
#define CONFIG_TSEC1_NAME "TSEC0"
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
|
2008-01-16 15:38:05 +09:00
|
|
|
#define TSEC1_PHY_ADDR 2
|
|
|
|
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
|
|
#define TSEC1_PHYIDX 0
|
2008-02-09 04:15:55 +09:00
|
|
|
#endif
|
2008-01-16 15:38:05 +09:00
|
|
|
|
2008-02-09 04:15:55 +09:00
|
|
|
#ifdef CONFIG_TSEC2
|
|
|
|
#define CONFIG_HAS_ETH1
|
|
|
|
#define CONFIG_TSEC2_NAME "TSEC1"
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_TSEC2_OFFSET 0x25000
|
2008-02-09 04:15:55 +09:00
|
|
|
#define TSEC2_PHY_ADDR 0x1c
|
|
|
|
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
|
|
#define TSEC2_PHYIDX 0
|
|
|
|
#endif
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
/* Options are: TSEC[0-1] */
|
|
|
|
#define CONFIG_ETHPRIME "TSEC0"
|
|
|
|
|
2008-02-09 04:15:55 +09:00
|
|
|
#endif
|
|
|
|
|
2008-03-29 04:31:23 +09:00
|
|
|
/*
|
|
|
|
* SATA
|
|
|
|
*/
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
2008-03-29 04:31:23 +09:00
|
|
|
#define CONFIG_SATA1
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_SATA1_OFFSET 0x18000
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
|
|
|
|
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
2008-03-29 04:31:23 +09:00
|
|
|
#define CONFIG_SATA2
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_SATA2_OFFSET 0x19000
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
|
|
|
|
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
2008-03-29 04:31:23 +09:00
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_SATA
|
|
|
|
#define CONFIG_LBA48
|
|
|
|
#endif
|
|
|
|
|
2008-01-16 15:38:05 +09:00
|
|
|
/*
|
|
|
|
* Environment
|
|
|
|
*/
|
2008-10-16 22:01:15 +09:00
|
|
|
#ifndef CONFIG_SYS_RAMBOOT
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_ENV_ADDR \
|
|
|
|
(CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
|
2008-09-11 05:48:06 +09:00
|
|
|
#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
|
|
|
|
#define CONFIG_ENV_SIZE 0x4000
|
2008-01-16 15:38:05 +09:00
|
|
|
#else
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
|
2008-09-11 05:48:06 +09:00
|
|
|
#define CONFIG_ENV_SIZE 0x2000
|
2008-01-16 15:38:05 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* BOOTP options
|
|
|
|
*/
|
|
|
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Command line configuration.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
|
|
|
|
2009-06-10 05:25:30 +09:00
|
|
|
#ifdef CONFIG_MMC
|
2011-01-04 18:23:05 +09:00
|
|
|
#define CONFIG_FSL_ESDHC_PIN_MUX
|
2009-06-10 05:25:30 +09:00
|
|
|
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
|
|
|
|
#endif
|
|
|
|
|
2008-01-16 15:38:05 +09:00
|
|
|
/*
|
|
|
|
* Miscellaneous configurable options
|
|
|
|
*/
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* For booting Linux, the board info and command line data
|
2010-09-11 07:42:32 +09:00
|
|
|
* have to be in the first 256 MB of memory, since this is
|
2008-01-16 15:38:05 +09:00
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
|
*/
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
|
2016-07-08 12:25:15 +09:00
|
|
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Core HID Setup
|
|
|
|
*/
|
mpc83xx: turn on icache in core initialization to improve u-boot boot time
before, MPC8349ITX boots u-boot in 4.3sec:
column1 is elapsed time since first message
column2 is elapsed time since previous message
column3 is the message
0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX
0.000 0.000:
0.000 0.000: Reset Status:
0.000 0.000:
0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.032 0.000: Board: Freescale MPC8349E-mITX
0.032 0.000: UPMA: Configured for compact flash
0.032 0.000: I2C: ready
0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
1.516 1.456: FLASH: 16 MB
2.641 1.125: PCI: Bus Dev VenId DevId Class Int
2.652 0.011: 00 10 1095 3114 0180 00
2.652 0.000: PCI: Bus Dev VenId DevId Class Int
2.652 0.000: In: serial
2.652 0.000: Out: serial
2.652 0.000: Err: serial
2.682 0.030: Board revision: 1.0 (PCF8475A)
3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic
3.080 0.000: TSEC0, TSEC1
4.300 1.219: IDE: Bus 0: .** Timeout **
after, MPC8349ITX boots u-boot in 3.0sec:
0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX
0.010 0.000:
0.010 0.000: Reset Status:
0.010 0.000:
0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz
0.017 0.000: Board: Freescale MPC8349E-mITX
0.038 0.020: UPMA: Configured for compact flash
0.038 0.000: I2C: ready
0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz)
0.260 0.222: FLASH: 16 MB
1.390 1.130: PCI: Bus Dev VenId DevId Class Int
1.390 0.000: 00 10 1095 3114 0180 00
1.390 0.000: PCI: Bus Dev VenId DevId Class Int
1.400 0.010: In: serial
1.400 0.000: Out: serial
1.400 0.000: Err: serial
1.400 0.000: Board revision: 1.0 (PCF8475A)
1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic
1.832 0.000: TSEC0, TSEC1
3.038 1.205: IDE: Bus 0: .** Timeout **
also tested on these boards (albeit with a less accurate
boottime measurement method):
seconds: before after
8349MDS ~2.6 ~2.2
8360MDS ~2.8 ~2.6
8313RDB ~2.5 ~2.3 #nand boot
837xRDB ~3.1 ~2.3
also tested on an 8323ERDB.
v2: also remove the delayed icache enablement assumption in arch ppc's
board.c, and add a CONFIG_MPC83xx define in the ITX config file for
consistency (even though it was already being defined in 83xx'
config.mk).
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2010-04-21 09:37:54 +09:00
|
|
|
#define CONFIG_SYS_HID0_INIT 0x000000000
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
|
|
|
|
| HID0_ENABLE_INSTRUCTION_CACHE)
|
2008-10-16 22:01:15 +09:00
|
|
|
#define CONFIG_SYS_HID2 HID2_HBE
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
|
|
#endif
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Environment Configuration
|
|
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
|
2008-03-15 05:20:18 +09:00
|
|
|
#define CONFIG_HAS_FSL_DR_USB
|
2014-10-20 20:01:01 +09:00
|
|
|
#define CONFIG_USB_EHCI_FSL
|
|
|
|
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
2008-03-15 05:20:18 +09:00
|
|
|
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_NETDEV "eth1"
|
2008-01-16 15:38:05 +09:00
|
|
|
|
2018-03-28 21:38:20 +09:00
|
|
|
#define CONFIG_HOSTNAME "mpc837x_rdb"
|
2011-10-13 22:03:47 +09:00
|
|
|
#define CONFIG_ROOTPATH "/nfsroot"
|
2011-10-12 13:57:19 +09:00
|
|
|
#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
|
2011-10-13 22:03:48 +09:00
|
|
|
#define CONFIG_BOOTFILE "uImage"
|
2011-10-12 13:57:19 +09:00
|
|
|
/* U-Boot image on TFTP server */
|
|
|
|
#define CONFIG_UBOOTPATH "u-boot.bin"
|
|
|
|
#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
|
2008-01-16 15:38:05 +09:00
|
|
|
|
2011-10-12 13:57:19 +09:00
|
|
|
/* default location for tftp and bootm */
|
|
|
|
#define CONFIG_LOADADDR 800000
|
2008-01-16 15:38:05 +09:00
|
|
|
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
2011-10-12 13:57:19 +09:00
|
|
|
"netdev=" CONFIG_NETDEV "\0" \
|
|
|
|
"uboot=" CONFIG_UBOOTPATH "\0" \
|
2008-01-16 15:38:05 +09:00
|
|
|
"tftpflash=tftp $loadaddr $uboot;" \
|
2012-09-24 00:41:24 +09:00
|
|
|
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" $filesize; " \
|
|
|
|
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" +$filesize; " \
|
|
|
|
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
|
|
|
" $filesize\0" \
|
2009-08-22 06:34:38 +09:00
|
|
|
"fdtaddr=780000\0" \
|
2011-10-12 13:57:19 +09:00
|
|
|
"fdtfile=" CONFIG_FDTFILE "\0" \
|
2008-01-16 15:38:05 +09:00
|
|
|
"ramdiskaddr=1000000\0" \
|
2011-10-12 13:57:19 +09:00
|
|
|
"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
|
2008-01-16 15:38:05 +09:00
|
|
|
"console=ttyS0\0" \
|
|
|
|
"setbootargs=setenv bootargs " \
|
|
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
|
|
|
|
"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
|
2011-10-12 13:57:19 +09:00
|
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
|
|
|
|
"$netdev:off " \
|
2008-01-16 15:38:05 +09:00
|
|
|
"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
|
|
|
|
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
|
|
"setenv rootdev /dev/nfs;" \
|
|
|
|
"run setbootargs;" \
|
|
|
|
"run setipargs;" \
|
|
|
|
"tftp $loadaddr $bootfile;" \
|
|
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
|
|
"setenv rootdev /dev/ram;" \
|
|
|
|
"run setbootargs;" \
|
|
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
|
|
"tftp $loadaddr $bootfile;" \
|
|
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
|
|
|
|
#endif /* __CONFIG_H */
|