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https://github.com/brain-hackers/u-boot-brain
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77 lines
1.3 KiB
Plaintext
77 lines
1.3 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #2 - protocol 11
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*
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* Some assumptions are made:
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* * 2 mezzanine cards M1/M4 are connected to IO SLOT 7 and IO SLOT 8
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* (sgmii for DPMAC 12, 13, 14, 16, 17, 18)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac12 {
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status = "okay";
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phy-handle = <&sgmii_phy7_2>;
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phy-connection-type = "sgmii";
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};
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&dpmac17 {
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status = "okay";
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phy-handle = <&sgmii_phy7_3>;
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phy-connection-type = "sgmii";
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};
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&dpmac18 {
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status = "okay";
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phy-handle = <&sgmii_phy7_4>;
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phy-connection-type = "sgmii";
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};
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&dpmac16 {
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status = "okay";
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phy-handle = <&sgmii_phy8_2>;
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phy-connection-type = "sgmii";
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};
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&dpmac13 {
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status = "okay";
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phy-handle = <&sgmii_phy8_3>;
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phy-connection-type = "sgmii";
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};
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&dpmac14 {
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status = "okay";
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phy-handle = <&sgmii_phy8_4>;
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phy-connection-type = "sgmii";
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};
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&emdio1_slot7 {
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sgmii_phy7_2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmii_phy7_3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmii_phy7_4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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&emdio1_slot8 {
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sgmii_phy8_2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmii_phy8_3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmii_phy8_4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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