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https://github.com/brain-hackers/u-boot-brain
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76 lines
1.4 KiB
Plaintext
76 lines
1.4 KiB
Plaintext
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 19
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*
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* Some assumptions are made:
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* * mezzanine card M11 is connected to IO SLOT1 (usxgmii for DPMAC 3,4)
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* * mezzanine card M13 is connected to IO SLOT6 (25g-aui for DPMAC 5,6)
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* * mezzanine card M7 is connected to IO SLOT2 (xlaui4 for DPMAC 2)
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*
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* Copyright 2020 NXP
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*
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*/
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#include "fsl-lx2160a-qds.dtsi"
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&dpmac2 {
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status = "okay";
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phy-handle = <&cortina_phy0>;
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phy-connection-type = "xlaui4";
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};
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&dpmac3 {
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status = "okay";
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phy-handle = <&aquantia_phy1>;
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phy-connection-type = "usxgmii";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&aquantia_phy2>;
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phy-connection-type = "usxgmii";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&inphi_phy0>;
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phy-connection-type = "25g-aui";
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};
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&dpmac6 {
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status = "okay";
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phy-handle = <&inphi_phy1>;
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phy-connection-type = "25g-aui";
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};
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&emdio1_slot1 {
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aquantia_phy1: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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aquantia_phy2: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x1>;
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};
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};
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&emdio1_slot2 {
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cortina_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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&emdio1_slot6 {
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inphi_phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x0>;
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};
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inphi_phy1: ethernet-phy@1 {
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compatible = "ethernet-phy-id0210.7440";
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reg = <0x1>;
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};
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};
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