2020-01-06 21:05:57 +09:00
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019-2020 NXP
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*
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* PCIe DT fixup for NXP Layerscape SoCs
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* Author: Wasim Khan <wasim.khan@nxp.com>
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*
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/soc.h>
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#include "pcie_layerscape_fixup_common.h"
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void ft_pci_setup(void *blob, bd_t *bd)
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{
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#if defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
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uint svr;
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svr = SVR_SOC_VER(get_svr());
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if (svr == SVR_LX2160A && IS_SVR_REV(get_svr(), 1, 0))
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ft_pci_setup_ls_gen4(blob, bd);
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else
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#endif /* CONFIG_PCIE_LAYERSCAPE_GEN4 */
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ft_pci_setup_ls(blob, bd);
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}
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2020-01-06 21:05:59 +09:00
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#if defined(CONFIG_FSL_LAYERSCAPE)
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#ifdef CONFIG_ARCH_LX2160A
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/* returns the next available streamid for pcie, -errno if failed */
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int pcie_next_streamid(int currentid, int idx)
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{
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if (currentid > FSL_PEX_STREAM_ID_END)
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return -EINVAL;
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return currentid | ((idx + 1) << 11);
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}
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#else
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/* returns the next available streamid for pcie, -errno if failed */
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int pcie_next_streamid(int currentid, int idx)
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{
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static int next_stream_id = FSL_PEX_STREAM_ID_START;
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if (next_stream_id > FSL_PEX_STREAM_ID_END)
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return -EINVAL;
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return next_stream_id++;
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}
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#endif
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#endif /* CONFIG_FSL_LAYERSCAPE */
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