u-boot-brain/board/phytec/pcl063/Kconfig

if TARGET_PCL063

config SYS_BOARD
	default "pcl063"

config SYS_VENDOR
	default "phytec"

config SYS_CONFIG_NAME
	default "pcl063"

endif

if TARGET_PCL063_ULL

config SYS_BOARD
	default "pcl063"

config SYS_VENDOR
	default "phytec"

config SYS_CONFIG_NAME
	default "pcl063_ull"

endif
imx: Add PHYTEC phyBOARD-i.MX6UL-Segin Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063). CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0 Working: - Eth0 - i2C - MMC/SD - NAND - UART (1 & 5) - USB (host & otg) Signed-off-by: Martyn Welch <martyn.welch@collabora.com> 2018-12-11 20:34:46 +09:00			`if TARGET_PCL063`

			`config SYS_BOARD`
			`default "pcl063"`

			`config SYS_VENDOR`
			`default "phytec"`

			`config SYS_CONFIG_NAME`
			`default "pcl063"`

			`endif`
imx: Extend PCL063 support for phyCORE-i.MX6ULL SOM Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063) with eMMC on SoM. CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 38C Reset cause: POR Model: Phytec phyBOARD-i.MX6ULL-Segin SBC Board: PHYTEC phyCORE-i.MX6ULL DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2C - MMC/SD - eMMC - UART (1 & 5) - USB (host & otg) Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com> 2019-04-10 23:35:32 +09:00
			`if TARGET_PCL063_ULL`

			`config SYS_BOARD`
			`default "pcl063"`

			`config SYS_VENDOR`
			`default "phytec"`

			`config SYS_CONFIG_NAME`
			`default "pcl063_ull"`

			`endif`