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https://github.com/brain-hackers/u-boot-brain
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122 lines
4.1 KiB
C
122 lines
4.1 KiB
C
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/* SPDX-License-Identifier: BSD-3-Clause */
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/**********************************************************************
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* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
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**********************************************************************
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* WARNING: This file is auto-generated using api-generator utility.
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* api-generator: 12.02.13bb8d5
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* Do not edit it manually.
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**********************************************************************
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* Cadence Core Driver for LPDDR4.
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**********************************************************************
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*/
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#ifndef LPDDR4_STRUCTS_IF_H
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#define LPDDR4_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_if.h"
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/** @defgroup DataStructure Dynamic Data Structures
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* This section defines the data structures used by the driver to provide
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* hardware information, modification and dynamic operation of the driver.
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* These data structures are defined in the header file of the core driver
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* and utilized by the API.
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* @{
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*/
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/**********************************************************************
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* Structures and unions
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**********************************************************************/
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/**
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* Configuration of device.
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* Object of this type is used for probe and init functions.
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*/
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struct lpddr4_config_s
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{
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/** Base address of controller registers */
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struct lpddr4_ctlregs_s* ctlbase;
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/** Information/warning handler */
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lpddr4_infocallback infohandler;
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/** Controller interrupt handler */
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lpddr4_ctlcallback ctlinterrupthandler;
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/** PHY Independent Module interrupt handler */
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lpddr4_phyindepcallback phyindepinterrupthandler;
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};
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/**
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* Structure contains private data for Core Driver that should not be used by
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* upper layers. This is not a part of API and manipulating of those data may cause
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* unpredictable behavior of Core Driver.
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*/
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struct lpddr4_privatedata_s
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{
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/** Base address of controller registers */
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struct lpddr4_ctlregs_s* ctlbase;
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/** Information/warning handler */
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lpddr4_infocallback infohandler;
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/** Controller interrupt handler */
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lpddr4_ctlcallback ctlinterrupthandler;
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/** PHY Independent Module interrupt handler */
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lpddr4_phyindepcallback phyindepinterrupthandler;
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};
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/** Structure to contain debug information reported by the driver. */
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struct lpddr4_debuginfo_s
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{
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/** PLL Lock error. */
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bool pllerror;
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/** I/O calibration error. */
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bool iocaliberror;
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/** RX offset error. */
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bool rxoffseterror;
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/** CA training error. */
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bool catraingerror;
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/** Write levelling error. */
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bool wrlvlerror;
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/** Gate Level error. */
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bool gatelvlerror;
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/** Read Level error. */
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bool readlvlerror;
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/** Write DQ training error. */
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bool dqtrainingerror;
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};
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/** Frequency Set Point mode register values */
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struct lpddr4_fspmoderegs_s
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{
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/** MR1 register data for the FSP. */
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uint8_t mr1data_fn[LPDDR4_MAX_CS];
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/** MR2 register data for the FSP. */
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uint8_t mr2data_fn[LPDDR4_MAX_CS];
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/** MR3 register data for the FSP. */
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uint8_t mr3data_fn[LPDDR4_MAX_CS];
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/** MR11 register data for the FSP. */
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uint8_t mr11data_fn[LPDDR4_MAX_CS];
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/** MR12 register data for the FSP. */
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uint8_t mr12data_fn[LPDDR4_MAX_CS];
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/** MR13 register data for the FSP. */
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uint8_t mr13data_fn[LPDDR4_MAX_CS];
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/** MR14 register data for the FSP. */
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uint8_t mr14data_fn[LPDDR4_MAX_CS];
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/** MR22 register data for the selected frequency. */
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uint8_t mr22data_fn[LPDDR4_MAX_CS];
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};
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/** Structure to hold data set to initalise registers. */
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struct lpddr4_reginitdata_s
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{
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/** Register initialisation data for the Controller. */
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uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT];
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/** Should be set to true, if the corresponding denaliCtlReg element has been updated. */
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bool updatectlreg[LPDDR4_CTL_REG_COUNT];
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/** Register initialisation data for PHY independent module. */
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uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
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/** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */
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bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
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/** Register initialisation data for the PHY. */
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uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT];
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/** Should be set to true, if the corresponding denaliPhyReg element has been updated. */
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bool updatephyreg[LPDDR4_PHY_REG_COUNT];
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};
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#endif /* LPDDR4_STRUCTS_IF_H */
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