u-boot-brain/arch/arm/cpu/armv8/fsl-lsch3/README

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# Copyright 2014 Freescale Semiconductor
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# SPDX-License-Identifier:      GPL-2.0+
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Freescale LayerScape with Chassis Generation 3

This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
for example LS2085A.
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC Freescale LayerScape with Chassis Generation 3 is a set of SoCs with ARMv8 cores and 3rd generation of Chassis. We use different MMU setup to support memory map and cache attribute for these SoCs. MMU and cache are enabled very early to bootst performance, especially for early development on emulators. After u-boot relocates to DDR, a new MMU table with QBMan cache access is created in DDR. SMMU pagesize is set in SMMU_sACR register. Both DDR3 and DDR4 are supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> 2014-06-24 07:15:54 +09:00			`#`
			`# Copyright 2014 Freescale Semiconductor`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`Freescale LayerScape with Chassis Generation 3`

			`This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,`
ARMv8/ls2085a_emu: Add LS2085A emulator and simulator board support LS2085A is an ARMv8 implementation. This adds board support for emulator and simulator: Two DDR controllers UART2 is used as the console IFC timing is tightened for speedy booting Support DDR3 and DDR4 as separated targets Management Complex (MC) is enabled Support for GIC 500 (based on GICv3 arch) Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Signed-off-by: J. German Rivera <German.Rivera@freescale.com> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> 2014-06-24 07:15:56 +09:00			`for example LS2085A.`