u-boot-brain/arch/x86/cpu/ivybridge/Makefile

#
# Copyright (c) 2014 Google, Inc
#
# SPDX-License-Identifier:	GPL-2.0+
#

obj-y += car.o
obj-y += cpu.o
obj-y += early_init.o
obj-y += lpc.o
obj-y += microcode_intel.o
obj-y += pci.o
obj-y += sdram.o
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 14:42:07 +09:00			`#`
			`# Copyright (c) 2014 Google, Inc`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`

			`obj-y += car.o`
			`obj-y += cpu.o`
x86: ivybridge: Add early init for PCH devices Many PCH devices are hard-coded to a particular PCI address. Set these up early in case they are needed. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 14:42:23 +09:00			`obj-y += early_init.o`
x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 14:42:15 +09:00			`obj-y += lpc.o`
x86: ivybridge: Perform Intel microcode update on boot Microcode updates are stored in the device tree. Work through these and apply any that are needed. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 14:42:21 +09:00			`obj-y += microcode_intel.o`
x86: ivybridge: Enable PCI in early init Enable PCI so we can access devices that need to be set up before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 14:42:13 +09:00			`obj-y += pci.o`
x86: Add chromebook_link board This board is a 'bare' version of the existing 'link 'board. It does not require coreboot to run, but is intended to start directly from the reset vector. This initial commit has place holders for a wide range of features. These will be added in follow-on patches and series. So far it cannot be booted as there is no ROM image produced, but it does build without errors. Signed-off-by: Simon Glass <sjg@chromium.org> 2014-11-13 14:42:07 +09:00			`obj-y += sdram.o`